JPH0464232A - Forming method of contact hole - Google Patents

Abstract

PURPOSE:To obtain high inter-layer breakdown strength by coating a semiconductor base body with an inter-layer insulating film, implanting ions to the inter- layer insulating film, anisotropic-etching said inter-layer insulating film after implantation and forming a contact hole to the semiconductor base body while being adjoined to a wiring layer. CONSTITUTION:Ions 21 are implanted into an SiO2 film 18 from the direction vertical to an Si base body 11. Consequently, the etching rate of a flat section in the film 18 is increased, and the etching rate of a stepped section is made relatively smaller than that of the flat section. Overall RIE to the film 18 is conducted until the surface of an element forming region 13 is exposed, and a sidewall spacer composed of the film 18 is formed to a polycrystalline Si film 15 and an SiO2 film 16. The etching rate of the stepped section in the film 18 is made relatively smaller than that of the flat section at that time, thus thickening the film thickness of particularly the shoulder section of the sidewall spacer consisting of the film 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a contact hole forming method for forming a contact hole in a semiconductor substrate adjacent to a wiring layer in a self-aligned manner.

[Summary of the Invention] The present invention provides a contact hole forming method as described above in which ions are added between layers to increase the etching rate. ! By implanting ions into the edge film and then anisotropically etching this interlayer insulating film, it is possible to achieve a high glabellar withstand voltage between the wiring layer and another wiring layer that contacts through the contact hole. It is.

[Conventional technology]

In order to reduce the memory cell area and improve the degree of integration of semiconductor memories, etc., a so-called self-line contact method in which contact holes are formed in a self-aligned manner has been considered (for example, as disclosed in Japanese Patent Laid-Open No. 62-206873). ).

FIG. 2 shows a conventional example of forming a contact hole for a storage node in a meser cell of a stacked capacitive DRAM in a self-aligned manner.

In this conventional example, as shown in FIG. 2A, the Si substrate 11
A 5in2 film 12 for element isolation is formed on the SiO□
On the surface of the element forming region 13 surrounded by the film 12, a SiO□ film 14 which becomes a gate insulating film is formed.

Then, polycrystalline Si film 15 containing impurities and SiO□
16 films and 6 film strips are then deposited, and these 16 SiO□ films and 6-crystalline Si film 15 are patterned into a word line pattern. Note that a silicide film, a polycide film, etc. may be used instead of the polycrystalline Si film 15. After that, impurities are introduced into the element formation region 13 using the SiO□ film 12.16 and the polycrystalline Si film 15 as a mask. do,
An impurity diffusion layer 17 is formed. Furthermore, SiOzM
18 is completely deposited by CVD to a thickness of about 3,000 to 4,000 layers.

Next, as shown in FIG. 2B, RIE is performed on the entire surface of the 5i02 film 18 until the surface of the element formation region 13 is exposed, and the polycrystalline Si film 15 and SiO□ film 16 film strip 6O□ film 18 film pairs Form sidewall spacers. Therefore, polycrystalline S
The i film 15 is covered with the SiO□ film 16 and the film strip 6, and is insulated from the storage node etc. by the SiO□ film 16 and the film strip 6.

After that, as is conventionally known, side wall spacers such as 5iO
Using the Z film 18, only a contact hole for contacting the storage node with the impurity diffusion layer 17 is formed in a self-aligned manner.

(Problem to be Solved by the Invention) However, in one conventional example as described above, the film thickness of the side wall spacer made of the 5i02 film 18 is thin, especially at the shoulder portion, as shown in 2nd Bl. Polycrystalline S
Interlayer breakdown voltage defects are likely to occur between the i-film 15 and storage nodes and the like.

[Means for Solving the Problems] A contact hole forming method according to the present invention includes a method for forming a contact hole in a wiring layer 15.
The semiconductor substrate 11 on which is formed is covered with an interlayer insulating film 18,
Ions 21 that increase the etching rate of the interlayer insulating film 18 are implanted into the interlayer insulating film 18, and after the ion implantation, the interlayer insulating film 18 is anisotropically etched to form a contact hole 24 to the semiconductor substrate 11. It is formed adjacent to the wiring layer 15.

[Function] In the contact hole forming method according to the present invention, by selecting the incident angle of the ions 21 with respect to the semiconductor substrate 11, the amount of ions implanted into the stepped portion due to the wiring layer 15 in the interlayer insulating film 18 can be changed to the flat portion. The amount of ion implantation can be made smaller than the amount of ion implantation.

As a result, the etching speed of the stepped portion of the interlayer insulating film 18 caused by the wiring layer 15 can be made lower than the etching speed of the flat portion.

Therefore, in combination with the anisotropic etching of the interlayer insulating film 18, the thick interlayer insulating film 18 can be left as a sidewall spacer of the wiring layer 15.

[Example] Hereinafter, an example of the present invention applied to the formation of a contact hole for a storage node in a memory cell of a stacked capacitive DRAM will be described with reference to the first example.

As shown in FIG. 1A, in this embodiment as well, the steps up to the deposition of the 5iOz film 18 are carried out in the same manner as in the conventional example shown in FIG.

However, in this example, after that, Ar', Phos''A
Ions 21 such as s'' are implanted into the 5iOz film 18 from a direction perpendicular to the Si substrate 11. Therefore, the ions 21 are
A large amount is implanted into the flat portion of the SiO□ film 18 film pair 8, and not so much into the step portion formed by the polycrystalline Si film 15 and the like.

As a result, the etching rate of the flat portion of the SiO□ film 18 film pair 8 increases, and the etching rate of the stepped portion becomes relatively smaller than the etching rate of the flat portion.

Next, as shown in FIG. 1B, RIE is performed on all the SiO□ films 18 and 8 until the surface of the element formation region 13 is exposed, and the polycrystalline Si film 15 and the SiO□ film 16 film strip 6
A side wall spacer consisting of 8 is formed.

At this time, as mentioned above, the etching speed of the stepped portion of the SiO□ film 18 film pair 8 is relatively small compared to the etching speed of the flat portion, so the film thickness of the side wall spacer made of the 5iOz film 18, especially at the shoulder portion, is reduced. It is thicker than the conventional example mentioned above.

After that, steps similar to those of conventionally known methods are performed. That is, as shown in FIG. 1C, a SiO□ film 22 is deposited by CVD to a thickness of about 1,000 to 2,000 layers, and the resist 23 is patterned to have an opening 23a corresponding to the storage node portion.

Then, using this resist 23 as a mask, R is applied to the 5iOz film 22 until the surface of the impurity diffusion layer 17 is exposed.
By performing IE, only the contact hole 24 for the storage node is formed in a self-aligned manner, as shown in FIG. 1D.

In this embodiment as described above, the thick SiO□ film 18 can be left as a sidewall spacer for the polycrystalline Si film 15, which is the word line, so a high glabellar withstand voltage can be achieved between the word line and the storage node, etc. can do.

[Effects of the Invention] In the contact hole forming method according to the present invention, it is possible to leave a thick interlayer insulating film as a sidewall spacer of the wiring layer, so there is a high interlayer insulating film between this wiring layer and another wiring layer that contacts through the contact hole. It is possible to realize pressure resistance.

[Brief explanation of the drawing]

1 and 2 are side sectional views sequentially showing an embodiment of the present invention and a conventional example, respectively. In addition, in the symbols used in the drawings, 11--------1----------5i Substrate 15-
-----------Polycrystalline Si film 18------
-------- SiO2 film 21-----
--Ion 24--111--This is a contact hole.

Claims (1)

[Scope of Claims] A semiconductor substrate on which a wiring layer is formed is covered with an interlayer insulating film, ions that increase the etching rate of the interlayer insulating film are implanted into the interlayer insulating film, and after the ion implantation, the interlayer insulating film is removed. A method for forming a contact hole, comprising anisotropically etching a contact hole to form a contact hole for the semiconductor substrate adjacent to the wiring layer.