JPH046476A - Logic analyzer - Google Patents

Abstract

PURPOSE:To realize cost reduction and simplification of use by converting an input data into NTSC system signal and transmitting to a TV receiver while at the same time writing the input data at a designated address. CONSTITUTION:Output from a display screen preparing section 2 is converted into an NTSC system image signal and transmitted from a transmitting section 7. A switching section 8 designates the writing address in a data memory section 6 and writes an input data at the designated address. When a data is written into the memory section 6, the switching section 8 is operated to designate the writing address for every channel and to write the data sequentially. The data is fed while being magnified with a set magnification, if any, otherwise fed as it is to the preparing section 2. The preparing section 2 then sets the displaying method of read out data, the transmitting section 7 converts the input data into NTSC system image signal and transmits the converted data which is then displayed simultaneously on external TV receivers.According to the invention, cost reduction and simplification of use can be achieved.

Description

[Detailed Description of the Invention] [Summary] Regarding the logic analyzer used when testing the operation of digital circuits, the purpose of this is to reduce costs and make it easy to use. The logic includes a data memory section in which input data written and read out is enlarged for 9 hours while a display enlargement signal is input, and a display screen creation section that sets a display method for the read data.・In the analyzer, specify the writing address of the transmitting section that converts the output of the display screen creation section into an NTSC image signal and sends it to the television receiver, and the data memory section, and transfer the input data to the specified address. The configuration is such that a switch unit for writing data is provided.

[Industrial application field]

The present invention relates to a logic analyzer used when testing the operation of digital circuits.

Generally, when designing and prototyping a digital circuit, it is necessary to verify that the prototype digital circuit operates as planned.

Therefore, operating waveforms at a plurality of points within the digital circuit to be verified may be displayed using, for example, a logic analyzer to check whether these parts are operating as designed.

At this time, it is necessary to reduce the cost of the logic analyzer and to make it easy to use.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an example of the configuration diagram of FIG. 4.

The operation shown in FIG. 4 will be explained below with reference to FIG. Here, since all the data memory sections surrounded by dotted lines in FIG. 4 operate in the same way, the operation of the data memory section 1 will be explained. Further, in FIG. 4, parts necessary for writing/reading, such as a writing/reading clock and an address generation part, are omitted.

First, a logic analyzer with the configuration shown in Figure 5 is used, for example, to test the operation of a digital circuit made up of multiple ICs, and allows you to check the operation of a digital circuit by visually viewing the waveform displayed on the screen. It is possible to confirm whether or not the circuit section is operating normally.

That is, a plurality of probes 42 are installed on the surface of the logic analyzer to measure the waveform of the portion to be checked in the logic circuit.
1, a display section 4 for displaying waveforms of multiple channels, a keyboard 41 for specifying display order, signal name insertion, clock insertion, etc. The electronic circuit portion shown in the block diagram shown in FIG. 4 is stored.

Data is then applied to input sampling portion 11 in FIG. 4 via probe 421 which contacts the portion to be checked within the logic circuit.

The input sampling section 11 samples input data using the sampling clock from the reference clock generation section 5, and sequentially writes the data into the data memory 12.

In other data memory sections, input data is similarly sampled and written into the corresponding data memory.

The sampling data written in each data memory is read out in accordance with the order set on the keyboard and the magnification set on the display magnification setting section 3, and transferred to the screen creation section 2.

The screen creation section arranges the input sampling data, clocks, signal names, etc. specified on the keyboard in the order in which they should be displayed, and then sends them to the display section 4 to display them at the same time.

[Problem to be solved by the invention]

Here, in order to display the waveform on the logic analyzer as described above, the desired IC pin that has been found is sandwiched between one probe protruding from the main body, and this is done for all probes.

After that, settings are made using the keyboard to obtain a desired screen, and one screen is displayed on the display unit.

That is, various adjustments are required before displaying one waveform, and it cannot be used easily. Furthermore, since it includes a display section, it is expensive, which is two problems.

The present invention aims at reducing costs and making it easier to use.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 6 is a data memory section in which input data sampled by the sampling clock is written and read out, but is enlarged for 2 hours while the display enlargement signal is input, and 2 is the data memory section that is read out. This is a display screen creation unit that sets the display method.

Further, 7 is a transmitter that converts the output of the display screen creator into an NTSC signal and sends it to the television receiver;
Reference numeral 8 denotes a switch unit that specifies a write address of the data memory unit and causes the input data to be written to the specified address.

[Effect]

The present invention provides a logic analyzer in which a write address of the data memory section is designated in addition to a data memory section and a display screen creation section, and a switch section that causes input data to be written to the designated address and an output of the display screen creation section are set to NTSC. It consists of four transmitting units that convert the image signals into standard image signals and send them out.

Then, when writing data to the data memory section, operate the switch section to specify the write address for each channel and write the data sequentially, but the written data will remain as long as the display magnification is set. If the magnification is not set, it is sent as is to the display screen creation section.

The display screen setting section sets the display method of the read data, and then simultaneously displays the screen on an external television receiver via the NTSC transmission section.

That is, since a television receiver is used, costs can be reduced, and data can be written by operating, for example, two switches, making it easy to use.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an example of the configuration diagram of FIG. 2.

Here, an input sampling section 61, a data memory section 62, a reference clock generation section 63, a display magnification setting section 6
4. Switch SW indicates a component of the data memory unit 6, and switches SW, , SW indicate a component of the switch 8. Note that the same reference numerals indicate the same objects throughout the figures. The operation shown in FIG. 2 will be explained below with reference to FIG.

First, connect the +5v clip, ground clip, and trigger pulse input probe shown in Figure 3 to the corresponding terminals in the logic circuit, and then turn the channel changeover switch SW,
Set to the specified channel (corresponding to the specified address). Further, the output of the reference clock generation section 63 is applied to the input sampling section 61 and the data memory section 62. Here, the trigger pulse is a pulse indicating the beginning of data, and this pulse is applied to the data memory section 62.

Now, when the probe of the logic analyzer is brought into contact with the measurement waveform output terminal (not shown) in the logic circuit and the data write switch SW3 is turned on, the input data sampled by the input sampling section 61 is stored in the data memory section. is written in the specified chamful.

Therefore, the probe is brought into contact with another measurement waveform output terminal by switching the switch SW, and data is written into another specified channel in the data memory section. After repeating this process and writing several channels of waveforms into the data memory section 62, they are added to the display screen creation section.

The display screen creation section sets a display method for the read data, and sends the read data to the transmitter according to the set display method.

The transmitter converts the input data into an NTSC signal and sends it to the television receiver, so that the receiver displays all the waveforms of several channels at the same time.

That is, the display section was removed from the logic analyzer so that it could be displayed on a television receiver and all operations could be performed at hand.

This has led to cost reduction and ease of use.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage of reducing costs and making it easier to use.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an example of the configuration of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. An example of the configuration diagram in FIG. 4 is shown. In the figure, 2 is a display screen creation section, 6 is a data memory section, 7 is a transmitting section, and 8 is a switch section. 7F Grandpa gf) Tora no Luxury n Tsuro 170γ 2 Recorder 5v 2nd [An example of D/l structure 8′ γ 3 Old dud BRf) Principle 70 Tsukumi 71 Picture promotion example / 170, 711D No. Kano No. 4 Old n Sei Yaguchi ρ-4 Yu 11 No. 5 Same

Claims (1)

[Claims] Input data sampled by a sampling clock is written and read out, and while a display enlargement signal is being input, the data memory section (6) is read out with time enlarged. In a logic analyzer that has a display screen creation section (2) that sets a data display method, a transmission section (7) that converts the output of the display screen creation section into an NTSC signal and sends it to a television receiver. and a switch section (8) that specifies a write address of the data memory section and causes the input data to be written to the specified address.
analyzer.