JPH0465449U - - Google Patents

Info

Publication number
JPH0465449U
JPH0465449U JP10848090U JP10848090U JPH0465449U JP H0465449 U JPH0465449 U JP H0465449U JP 10848090 U JP10848090 U JP 10848090U JP 10848090 U JP10848090 U JP 10848090U JP H0465449 U JPH0465449 U JP H0465449U
Authority
JP
Japan
Prior art keywords
chip
board
wire
sealing agent
thin plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10848090U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10848090U priority Critical patent/JPH0465449U/ja
Publication of JPH0465449U publication Critical patent/JPH0465449U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の実施例を示す図であり、第2
図は本考案の処理フローを示す図であり、第3図
は従来例を示す図である。 図において、1……基板、2…チツプ、3……
ワイヤ、4……封止剤、5……薄板、をそれぞれ
示す。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG.
The figure is a diagram showing the processing flow of the present invention, and FIG. 3 is a diagram showing a conventional example. In the figure, 1...substrate, 2...chip, 3...
A wire, 4... a sealant, and 5... a thin plate are shown, respectively.

Claims (1)

【実用新案登録請求の範囲】 基板1と、 該プリント基板1上に実装されるチツプ2と、 該基板1と該チツプ2とを接続するワイヤ3と
、 該チツプ2および該ワイヤ3を密閉した状態で
封止する高流動性の封止剤4と、 該封止剤4上に位置する薄板5と、 を有することを特徴とするペアチツプ実装構造。
[Claims for Utility Model Registration] A board 1, a chip 2 mounted on the printed circuit board 1, a wire 3 connecting the board 1 and the chip 2, and a hermetically sealed chip 2 and the wire 3. A paired chip mounting structure comprising: a highly fluid sealing agent 4 that seals in a state in which the chips are in contact with each other; and a thin plate 5 located on the sealing agent 4.
JP10848090U 1990-10-18 1990-10-18 Pending JPH0465449U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10848090U JPH0465449U (en) 1990-10-18 1990-10-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10848090U JPH0465449U (en) 1990-10-18 1990-10-18

Publications (1)

Publication Number Publication Date
JPH0465449U true JPH0465449U (en) 1992-06-08

Family

ID=31855504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10848090U Pending JPH0465449U (en) 1990-10-18 1990-10-18

Country Status (1)

Country Link
JP (1) JPH0465449U (en)

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