JPH0465477U - - Google Patents
Info
- Publication number
- JPH0465477U JPH0465477U JP1990109263U JP10926390U JPH0465477U JP H0465477 U JPH0465477 U JP H0465477U JP 1990109263 U JP1990109263 U JP 1990109263U JP 10926390 U JP10926390 U JP 10926390U JP H0465477 U JPH0465477 U JP H0465477U
- Authority
- JP
- Japan
- Prior art keywords
- surface mount
- solder
- adhesive
- view
- sopic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/011—Apparatus therefor
- H10W72/0113—Apparatus for manufacturing die-attach connectors
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Description
第１図はこの考案の一実施例によるＳＯＰＩＣ
の平面図、第２図は第１図の背面図、第３図はこ
の考案の他の実施例を示すチツプ部品の斜視図、
第４図は第３図の背面斜視図、第５図は従来のＳ
ＯＰＩＣの平面図、第６図は第５図の背面図、第
７図は従来およびこの考案共通のＳＯＰＩＣの斜
視図である。
図において、１はＳＯＰＩＣ、２は粘着剤を塗
布したＳＯＰＩＣの底面、第３図はチツプ部品、
４はチツプ部品３の電極端子、５は粘着剤を塗布
したチツプ部品３の底面、７はリード端子を示す
。なお、図中、同一符号は同一、又は相当部分を
示す。
Figure 1 shows a SOPIC according to an embodiment of this invention.
2 is a rear view of FIG. 1, and FIG. 3 is a perspective view of a chip component showing another embodiment of this invention.
Figure 4 is a rear perspective view of Figure 3, and Figure 5 is a conventional S
FIG. 6 is a plan view of the OPIC, FIG. 6 is a rear view of FIG. 5, and FIG. 7 is a perspective view of the SOPIC common to the conventional and this invention. In the figure, 1 is the SOPIC, 2 is the bottom of the SOPIC coated with adhesive, and Figure 3 is the chip parts.
Reference numeral 4 indicates an electrode terminal of the chip component 3, 5 indicates the bottom surface of the chip component 3 coated with an adhesive, and 7 indicates a lead terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
において、前記基板面に対向する表面実装用部品
の底面全体に半田溶融時の張力よりも強い粘力を
持つた粘着剤を塗布したことを特徴とする表面実
装用ＩＣ。 Surface mount IC mounted on a board using solder
A surface mount IC characterized in that an adhesive having a viscosity stronger than the tension at the time of melting the solder is applied to the entire bottom surface of the surface mount component facing the substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990109263U JPH0465477U (en) | 1990-10-16 | 1990-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990109263U JPH0465477U (en) | 1990-10-16 | 1990-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0465477U true JPH0465477U (en) | 1992-06-08 |
Family
ID=31856435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990109263U Pending JPH0465477U (en) | 1990-10-16 | 1990-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0465477U (en) |
-
1990
- 1990-10-16 JP JP1990109263U patent/JPH0465477U/ja active Pending
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