JPH0465575B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an elastic memory circuit that integrates a scrambler circuit/descrambler circuit.

(Prior Art) Fig. 2 shows a block diagram of a communication system that realizes conventional two-way digital communication using a time-division direction control transmission method (for example, "Easy Digital Transmission", Telecommunications Association, pp. 171-175). In the figure, 1 is a master side device such as a station, 2 is a slave side device such as a terminal, 3 to 6 are elastic (buffer) memories, 7 and 8 are scrambler circuits, and 9 and 1 are
0 is a descrambler circuit, 11 and 12 are burst synchronization control circuits, 13 and 14 are direction control switches,
15 is a cable, 16 is a data input terminal on the master side, 17 is a timing input terminal, 18 is a data output terminal on the master side, 19 is a data output terminal on the slave side, and 20 is a data input terminal on the slave side.

For signal transmission from the master side device 1 to the slave side device 2, a continuous transmission pulse train from the data input terminal 16 on the master side is temporarily stored in the elastic memory 3. After that, burst cycle control circuit 1
1, the pulses are read out from the elastic memory 3 at twice the speed or more every fixed period called a burst period, and converted into a burst-like pulse train (hereinafter referred to as a burst signal) (time axis compression).
The signal is sent to the cable 15 via a scrambler circuit 7 and a direction control switch 13, which will be described later. In the slave side device 2, the burst signal is once stored in the elastic memory 5 via a descrambler circuit 10, which will be described later, and then read out as a continuous signal and outputted to the data output terminal 19 on the slave side (time axis expansion). Similarly, signals are sent from the data input terminal 20 on the slave side to the master side device 1 by using the free time between the burst signals from the master side device 1, that is, the free time created by time axis compression. Perform similar operations. At this time, if the logic value "0" code continues for a long time on the transmission path, the timing will be lost on the receiving side, making it impossible to receive the data correctly. Therefore, scrambler circuits 7 and 8 are provided for the transmitted data, and the master side device Descrambler circuits 9 and 10 are provided on the receiving side of the data signal 1 and the slave device 2 to restore the data signal to a normal data signal.

As an example of the configuration of the scrambler circuits 7, 8 and descrambler circuits 9, 10, a reset type circuit in which the scrambler circuit and the descrambler circuit have the same shape is shown in FIG. ” Corona Publishing, P251-252). In the figure, 21a to 21e are shift register circuits;
2a and 22b are exclusive OR circuits, 23 is a data input terminal, 24 is a data output terminal, and 25 is a reset input terminal. Exclusive OR circuits 22a and 5
A scramble pattern is created by the stage feedback shift registers 21a to 21e.

In the case of a scrambler circuit, the original pulse train input from the data input terminal 23 is scrambled by performing an exclusive OR operation on the output of the exclusive OR circuit 22a in the exclusive OR circuit 22b. A pulse train can be obtained at the data output terminal 24. In the case of a descrambler circuit, the original pulse train is input to the data output terminal by performing an exclusive OR operation on the scrambled pulse train input from the data input terminal 23 and the output of the exclusive OR circuit 22a. You can get it on the 24th. FIG. 4 shows an example of the output logical value (scrambling pattern) of the exclusive OR circuit 22a. The figure is
This shows an example of a pattern consisting of 31 logical values. It is assumed that a reset input terminal 25 is connected to the shift register circuits 21a to 21e, and is reset every burst to set an initial logic value. In this example, the initial logical values are "01101" from the left of the sister register circuits 21a to 21e.

Therefore, in the system shown in FIG. 2, when the burst signal is sent from the master side device 1 to the slave side device 2, the aforementioned burst signal is randomized by the scrambler circuit 7, and then sent from the master side device 1 to the slave side device 2.
Upon receiving the randomized burst signal sent to the slave device 2, the descrambler circuit 10 restores the data signal to the original data signal, and then performs the above-described time axis expansion. When sending data from the slave side device 2 to the master side device 1, randomization and decoding are similarly performed in the scrambler circuit 8 and descrambler circuit 9.

(Problems to be Solved by the Invention) However, in the communication system with the above configuration,
elastic memory circuit, scrambler circuit,
Since each descrambler circuit is configured separately, the circuit scale is large, which is a disadvantage when implementing it into an LSI.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide an elastic memory circuit integrated with a scrambler circuit that can be realized with simple hardware.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an elastic memory circuit that performs time axis compression and time axis expansion by changing the read speed. The present invention comprises an elastic memory consisting of memory cells, and inverting means provided on the input side or output side of the memory cells in correspondence with a scramble pattern and inverting the polarity of serial digital data.

(Operation) The technical means of the present invention operates as follows. In the case where an inverting means (inverter) is provided on the output side of each memory cell corresponding to the scramble pattern, for example, when the scramble pattern indicates "1", the inverting means is provided on the output side of the memory cell, Since no inverting means is provided when the scramble pattern indicates "0", when data is read from each memory cell, the data is scrambled (randomized) by the inverting means and output. Furthermore, when this elastic memory circuit is used as a descrambler circuit, scrambled data is sequentially written to each memory cell. Since the polarity of the signal is inverted once again, the original data signal is restored.

On the other hand, if the inverting means is provided on the input side of each memory cell in correspondence with the scramble pattern, the inverting means scrambles or descrambles when sequentially writing to each memory cell.

Therefore, by providing inverting means on the input side or output side of the memory cell in accordance with the scramble pattern, the scrambler (or descrambler)
Since the functionality is provided in an elastic memory circuit, the problems of the prior art described above can be overcome.

(Embodiment) FIG. 1a is a block diagram of an elastic memory circuit showing a first embodiment of the present invention. In the figure, reference numeral 30 denotes an elastic memory, which is composed of 31 memory cells each having a capacity of 1 bit (hereinafter, this memory cell will be referred to as a first memory 30a to a 31st memory 30).
(referred to as f). 31 is the first memory 30a to the 31st memory;
32 is a write clock input terminal, 33 is a write counter that counts the write clock, and 34 is the first memory 30a to the 31st memory 30.
35 is a read clock input terminal, 36 is a read counter that counts the read clock, and 37 is an address decoder circuit provided corresponding to the output of the read counter 36 to decode the output of the write counter 33; 38 is a data output terminal that outputs the data selected by the data selector circuit 37; 39 is the first memory 30a to 31st memory 30;
This is an inverter provided between the output of f and the input of the data selector circuit 37 in correspondence with the scramble pattern. In this embodiment, the inverter 39
are provided corresponding to the scramble pattern shown in FIG.
d,..., an inverter 39 is provided at the output of the 30th memory 30e, and when the scramble pattern "0" is indicated, that is, the first memory 30a, the second memory 3
0b, . . , the output of the 31st memory 30f is directly connected to the input of the data selector circuit 37.

Next, the operation of the first embodiment will be explained.

By inputting a clock signal from the write clock input terminal 32, the write address counter 33 counts up, and according to the count result, the signal decoded by the address decoder circuit 28 is used as a data latch signal for the memory. . Therefore, the serial data input to the data input terminal 31 is written into one of the first memories 30a to 31st memories 30f to which a data latch signal is applied from the address decoder circuit 34. That is, according to the data latch signal,
Input data is written to each memory sequentially. In reading the data written in the elastic memory 30 in this way, first, the read clock applied to the read clock input terminal 35 is counted up by the read counter 36. Based on this count result, the data selector circuit 37 selects the
The output of the 31 memory 30f is selected, and the data resulting from the selection is output to the data output terminal 38. At this time, randomization is performed by an inverter 39 provided corresponding to the scramble pattern. That is, the first memory 30a, the second memory 30b,...
The output of the 31st memory 30f is the data selector circuit 3
The outputs of the third memory 30c, fourth memory 30d, . For example, when all data signals input from the data input terminal 31 have a logical value of "1", the first memory 30a outputs "1", the second memory 30b outputs "1", and the third memory 30c outputs "1". "0" from the fourth memory 30d, "0" from the fourth memory 30d, ..., the 30th memory 30e
"0" is output from the 31st memory 30f, and "1" is output from the 31st memory 30f, resulting in the same data as when the scramble pattern shown in FIG. 4 and the input data signal are just subjected to an exclusive OR operation. It will be output from memory. In other words, the same data is obtained at the data output terminal 38 as when the conventional scrambler circuit is used.

Similarly, the case of a descrambler circuit will be explained. For example, all sent data is logical value “0”
In this case, the logical value of the data obtained at the data input terminal 31 is the same as the scramble pattern shown in FIG. “0” from the first memory 30a, “0” from the second memory 30b, third memory 30c
"1" from the fourth memory 30d, "1" from the fourth memory 30d,
..., "1" will be output from the 30th memory 30e and "0" will be output from the 31st memory 30f, but the first memory 30a, the second memory 30b, ...
The 31st memory 30e is directly input to the data selector circuit 37, the 3rd memory 30c, the 4th memory 30
d,..., the 30th memory 30e outputs a logically inverted signal via the inverter 39, so all data read from each memory has a logical value of "0" and returns to the normal data signal at the data output terminal. Obtained at 38.

FIG. 1b is a block diagram of an elastic memory circuit showing a second embodiment of the present invention. In this figure, the same reference numerals as in FIG. 1a indicate the same components. In the first embodiment, the inverter 3
9 is provided on the output side of the first memory 30a to the 31st memory 30f corresponding to the scramble pattern, but in this embodiment, the inverter 39a is provided on the output side of the first memory 30a to the 31st memory 30f corresponding to the scramble pattern.
31 is provided on the input side of the memory 30f. That is, when the scramble pattern indicates "1", the input of the memory is connected to the data input terminal 31 via the inverter 39a, and when the scramble pattern indicates "0", the input of the memory is connected to the data input terminal 31. It is directly connected to the input terminal 31.

Next, the operation of the second embodiment will be explained. At the time of writing, data from the data input terminal 31 is sequentially selected and written into the first memory 30a to the 31st memory 30f in accordance with the data latch signal output from the address decoder circuit 34, as in the case of the first embodiment. It will be done. At this time, randomization is performed by an inverter 39a provided corresponding to the scramble pattern. That is, the first memory 30
a, the second memory 30b, . . . , the 31st memory 30e are directly input from the data input terminal 31, and the third
A logically inverted signal is input to the memory 30c, the fourth memory 30d, . . . , and the 30th memory 30f via the inverter 39a. Therefore, for example, when all data signals input from the data input terminal 31 have a logical value of "1", the first memory 30a
"1" in the second memory 30b, "0" in the third memory 30c, "0" in the fourth memory 30d, ..., "0" in the 30th memory 30e, "0" in the 31st memory 30e, etc. "1" is input to the memory 30f, and the same data is written into the memory as if the scrambling pattern shown in FIG. 4 and the input data signal were just subjected to an exclusive OR operation. Therefore,
The same data as when using the scrambler circuit according to the prior art is stored in the data selector circuit 37.
By reading data from each memory, data is obtained at the data output terminal 38.

Similarly, the case of a descrambler circuit will be explained. For example, if all transmitted data has a logical value of "0", the logical value of the data obtained at the data input terminal 31 will be the same as the scramble pattern shown in FIG. "0" in the first memory 30a, "0" in the second memory 30b, "1" in the third memory 30c, "1" in the fourth memory 30d, ..., "1" in the 30th memory 30e. ”, “0” will be input to the 31st memory 30f, but the first memory 3
0a, second memory 30b,..., 31st memory 30f
is input directly from the data input terminal 31, and a logically inverted signal is input to the third memory 30c, fourth memory 30d, ..., 30th memory 30e via the inverter 39a, so that it is written into each memory. All data have a logical value of "0". Therefore, the read data from each memory is returned to a normal data signal and is obtained at the data output terminal 38.

As described above, according to the first and second embodiments, the elastic memory circuit and the scrambler circuit are integrated with almost no change in the circuit scale of the elastic memory circuit. It is also advantageous when

(Effects of the Invention) As explained in detail above, according to the present invention,
By providing inverting means corresponding to the scramble pattern on the input side or output side of each memory cell, a scrambling function can be obtained in a normal elastic memory circuit, making it possible to significantly reduce the number of circuits and making it easier to integrate into LSI. .

[Brief explanation of the drawing]

1a and 1b are block diagrams of elastic memory circuits showing a first embodiment and a second embodiment of the present invention, respectively, FIG. 2 is a block diagram of a conventional communication system, and FIG. 3 is a block diagram of a conventional communication system. FIG. 4, a configuration diagram of the scrambler/descrambler circuit, is a diagram showing an example of a scramble pattern. 30...Elastic memory, 30a to 30f
...Memory (memory cell), 31...Data input terminal,
32...Write clock input terminal, 33...Write counter, 34...Address decoder, 35...Read clock input terminal, 36...Read counter, 37...Data selector circuit, 38...Data output terminal, 39, 39a...Inverter.

Claims (1)

[Scope of Claims] 1. An elastic memory circuit that performs time axis compression and time axis expansion by changing read speed, comprising: an elastic memory consisting of a plurality of memory cells with a 1-bit capacity; and an input of the memory cell. What is claimed is: 1. An elastic memory circuit with a scrambler function, characterized in that it is provided with inverting means for inverting the polarity of serial digital data, which is provided corresponding to a scramble pattern on the side or the output side.