JPH0465584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to an image data conversion device that can compress or restore image data at high speed.

[Conventional technology]

In conventional digital image processing devices, if the image is generally treated as a one-dimensional bit string in the main scanning direction from the input section to the processing section and from the processing section to the output section,
It is simple as it does not require converting the image data format, but it requires a large amount of memory. For example, B4
Approximately 2 megabytes of memory is required to store one page in size.

Therefore, in order to reduce the amount of data to be handled, a method has been considered in which the image data is compressed and taken into the processing section, the compressed data is processed, and then restored to a one-dimensional bit string and transferred to the output section. There is.

The present inventor previously filed a patent application for the representation method of image data in this processing section (Japanese Patent Application No. 1983-
No. 91406). The image data representation method described in this patent application can be briefly explained as follows.

Now, as shown in Figure 1, the width is M×p
Assuming that there is an image 1 consisting of N×q dots vertically, this image 1 is divided into p×q units. Then, a map memory having areas corresponding to each unit is created. This map memory is schematically expressed as shown in FIG.

This map memory 2 includes p×q unit memories, and each unit memory stores the following information.

1 The image information of the corresponding unit is all 0 (pure white)
, then 0 or a specific number 2. If the image information of the corresponding unit is not all 0, a pointer to the data memory where the image data of the corresponding unit is stored (for example, the start address of the data memory described later). ) FIG. 3 is an explanatory diagram of the data memory. The data memory 3 stores image information in units of M.times.N dots for the units shown in FIG. 1 whose image information is not all 0. The storage address is the location specified by the map memory.

For example, assuming that the (i, j) and (l, m) units on the screen in Figure 1 contain image information, the information for each (M x N) dot is stored in the memory in Figure 3. They are stored in areas 3-1 and 3-2, respectively. Then, (i,
j) Pointers to the memory areas are stored at the (l, m) positions, respectively.

As described above, in the above system, the entire image data is compressed by storing only when black pixels are included in the contents of the M.times.N dot matrix (unit).

By the way, as mentioned above, compression when reading,
If decompression is to be performed at the time of output, the speed of compression and decompression must be the same as or faster than the speed of input and output.

Therefore, high-speed compression and decompression is required, but no conventional device has been able to compress and decompress at a sufficiently high speed.

〔the purpose〕

An object of the present invention is to quickly determine whether or not the contents of an M×N dot matrix (unit) include black pixels, that is, whether or not the unit needs to be stored. The object of the present invention is to enable high-speed compression or restoration of image data.

〔overview〕

The present invention is characterized by first and second memory buffers each having a capacity of 2m x N (however, 2m≧M) when the number of words for one line of image data is M, and 1 word x N lines is one unit. First and second buffer address registers address each of the memory buffers, and a code indicating whether one unit of data read from the first and second memory buffers is all 0 or other is the unit. When the data of one unit is other than all 0s, the all 0s are stored in the area whose address is the code (pointer) recorded in the map memory.
2 m from the other memory buffer while writing the input image data into one of the first and second memory buffers in the direction of consecutive memory addresses. N at the old address
The key point is that the image data is compressed by reading out words in succession.

Another feature of the present invention is that when restoring the compressed image data, based on the compressed image data, N addresses are stored in one of the first and second memory buffers at intervals of 2m. The present invention is characterized in that while words are being written in succession, they are read from the other memory buffer in the direction of successive memory addresses.

〔Example〕

The present invention will be explained below by way of examples. Fourth
The figure shows an embodiment of the invention. Note that in this embodiment, one word consists of 16 bits, and one line consists of 16 bits.
It is assumed that an image consisting of 256 words is compressed and converted with 16 bits x 16 words as one unit, that is, M=N=16 and p=256 in FIG.

In the figure, 11 is an S/P (serial/parallel) converter that converts the read signal (RIS video) a that is input serially into parallel; 12a
and 12b are input line selection circuits in which the other is turned off when one is on, and 13a and 13b are first and second buffer address registers, respectively. Each of these buffer address registers 13a, 13b consists of a total of 12 bits, including lower 8 bits and upper 4 bits. Therefore, the buffer address registers 13a, 13
b is the lower 8 bits for each line break (2 ⁸ =
256) is cleared and the upper 4 bits are incremented by 1. Therefore, 1 line (=256 words)
When reading is completed, the lower 8 bits are cleared, and the upper 4 bits are cleared to 0 at intervals of 16 lines. 14 is the input line selection circuit 12
A and 12b, an input line selection signal b for selecting one of them is sent, and one pulse signal is sent to the buffer address register 1 each time one word is written to the memory buffer (described later).
This is a buffer control circuit for sending data to 3a or 13b.

Further, 15a and 15b are connected to first and second circuits having a capacity of 256 words x 16 lines, to which an input signal of 1 word and 16 bits that has passed through either one of the input line selection circuits 12a and 12b is input in parallel. It is a memory buffer. In other words, the first and second memory buffers 15a,
15b can each store 256 units of data at one time.

Reference numerals 16a and 16b each represent an output line selection circuit, and one of the output lines is selected by a read line selection signal c input from a CPU (not shown). 17 is a 0 detector that detects whether the 16-bit data passed through the output line selection circuit is all 0 or not.

18 is the memory buffer 15a or 15b
This is a register that temporarily stores 16 words (=1 unit) of data read from.

Further, 19 is a map address register, 20 is a data address register, 21 is a 16-bit 0 data generator, and 22 is a main memory including a map memory and a data memory. The map address register 19 has a 20-bit configuration and is connected to the memory address bus 23. The data address register 20 consists of lower 4 bits and upper 16 bits, and the upper 16 bits are connected to the memory write bus 24. Furthermore, the lower 4 bits and the upper 16 bits, totaling 20 bits, are connected to the memory address bus 23.

Next, the operation of this embodiment having the above configuration will be explained. First, the operation of storing input data converted into a 16-bit parallel signal by the S/P converter 11 in the memory buffer 15a or 15b will be explained in the fifth section.
This will be explained with reference to the flowchart shown in the figure. Note that the first and second memory buffers 15a, 1
5b, the lower 8 bits of the first and second buffer address registers 13a and 13b specify an address in the main scanning direction, and the upper 4 bits specify an address in the sub-scanning direction.

Step S1...By input line selection signal b,
For example, the input line selection circuit 12a is selected.

Step S2...The second buffer address register 13b is cleared and set to 0.

Step S3...One word of data is output from the S/P converter 11, and this data is sent to step S2.
is stored in the second memory buffer 15b corresponding to the address specified by.

Step S4: Add 1 to the second buffer address register 13b.

Step S5: It is determined whether a carry has been issued from the second buffer address register 13b.
If there is no carry, return to step S3.
Steps S3 and S4 are then repeated until it is determined in step S5 that a carry has been output from the second buffer address register 13b.
As a result, the second buffer 15b has 256
Word x 16 data is stored. step
If YES in S5, proceed to step S6.

Step S6: It is determined whether all of the image information has been input, and if YES, the process ends. If no, proceed to the next step S7.

Step S7...The input line selection circuit 12b is selected by the input line selection signal.

Step S8...The first buffer address register 13a is cleared and becomes 0.

Steps S9, S10, S11...The steps S3, S4,
Since the processing procedure is the same as S5, the explanation will be omitted. Note that if the answer is YES in step S11, 256×16 words of data are stored in the first memory buffer 15a.

Step S12: It is determined whether all of the image information has been input. If yes, end. If no, the process returns to step S1 and the same procedure as above is repeated again. In addition, the first
While the input information is being written to the second memory buffer 15a, the data input to the second memory buffer 15b is read out;
Of course, while the input information is being written to the first memory buffer 15b, the data input to the first memory buffer 15a is read out.

Next, the process of reading data from the first and second memory buffers 15a and 15b will be described with reference to the flowcharts in FIGS. 6a and 6b.

Step S21...In the map address register 19,
Set the first address of map memory in main memory 22. Also, the first address of the data memory is set in the data address register 20. In this case, the first address of the data memory carries the lower 4 bits of 0.

Step S22: The output line selection circuit 16b is selected by the read line selection signal c.

Step S23: Clear the first buffer address register 13a and set it to 0.

Step S24: One word is read from the first memory buffer 15a and stored in the 16-word register 18.

Step S25: Add 1 to the upper 4 bits of the first buffer address register 13a.

Step S26: It is determined whether a carry has occurred from the upper 4 bits of the first buffer address register 13a. If no, the process returns to step S24. If YES, proceed to the next step S27. It should be noted that when the answer is YES in step S26, it is clear that one unit of data has been transferred to the 16 word register 18 from the first memory buffer 15a.

Step S27...The 0 detector 17 determines whether the data input to the 16 word register 18 is all 0s. If no,
Proceed to step S28, if yes, proceed to step S28.
Proceed to S32.

Step S28: Write the pointer of the upper 16 bits of the data address register 20 to the map memory address in the main memory 22 specified by the map address register 19.

The reason why the upper 16 bits of the data address register 20 are used as the pointer to be written into the map memory is as follows. In this example,
Signal processing is performed in hexadecimal, and by using the value obtained by dividing the memory address of the data memory by 16 as the pointer input to the map memory, the address space of the data memory can be expanded. In other words, when specifying an address using 16 bits and not using the value obtained by dividing the memory address of the data memory by 16 as the pointer, the address space of the data memory is 0 to FFFF, as shown in Figure 7a. Until. On the other hand, if the value obtained by dividing the data memory address by 16 is used as the pointer as described above, then
10 (hexadecimal)/
Since 16=1, the address space of the data memory can be greatly expanded from 0 to FFFFF.

Returning again to the flowchart of FIG. 6, the operation of this embodiment will be explained.

Step S29: Write one word of the 16-word register 18 to the data memory address specified by all bits (20 bits) of the data address register 20.

Step S30...Set 1 to data address register 20
Add.

Step S31: It is determined whether a carry is output from the lower 4 bits of the data address register 20. If no, step S29
Steps S29 and S30 are repeated until step S31 returns YES. As a result, all data stored in the 16-word register 18 is transferred to the data memory.

Step S32...When it is determined in step S27 that the data stored in the 16 word register 18 is all 0, the 0 data generator 21 generates the data at the map memory address specified by the map address register 19. 0 is stored.

Step S33...Set 1 to map address register 19
Add.

Step S34: It is determined whether reading of all words from the first memory buffer 15a has been completed. If the answer is no, the process returns to step S24, and the aforementioned steps from step S24 to step S33 are repeated again. If the answer is YES in step S34, the process advances to the next step S35.

Step S35: It is determined whether new data has been input to the second memory buffer 15b. Here, if no, the process ends. On the other hand, if YES, the process advances to step S36.

Step S36... Select the output line selection circuit 16a.

Step S37...The second buffer register 13b is cleared and set to 0.

Step S38: One word is read from the second buffer 15b and stored in the 16-word register 18.

Thereafter, the same procedures as steps S25 to S33 are performed.

Step S39: It is determined whether all words have been read from the second memory buffer 15b. If no, return to step S38. If YES, proceed to the next step S40.

Step S40: It is determined whether new data has been input to the first memory buffer 15a. If YES, the process returns to step S22. If no, terminate.

As is clear from the above explanation, according to this embodiment, if the data of the unit is all 0, 0 is stored in the map memory area corresponding to each unit of the image shown in FIG. If all values are not 0, a pointer can be input. Further, all data of the unit can be stored in the data memory area corresponding to the pointer only when the unit contains data other than 0.

In this embodiment, two 256.times.16 word memory buffers are provided, and writing and reading are performed alternately, so that the image data compression process described above can be performed at high speed.

Next, another embodiment of the present invention that enables both data compression and restoration will be described with reference to FIG. 8th
In the figure, 25 is a memory read bus, 26 is a data bus, 27a and 27b are first and second read line selection circuits whose opening and closing are respectively controlled by a control signal e from the CPU, and 28a and 28b are respective first and second read line selection circuits. 1 and the second output line selection circuit, and 29 indicates a P/S (parallel/serial) converter. Further, other symbols indicate the same or equivalent items as in FIG. 4.

As is clear from the configuration shown in FIG. 8, the data compression process is the same as in the first embodiment, so its explanation will be omitted.

The operation of restoring data compressed by this embodiment will be explained with reference to the flowchart of FIG. Furthermore, the meaning of restoring is
From the compressed information stored in the map memory and data memory shown in FIGS. 2 and 3, the first
It goes without saying that the purpose is to create the original data shown in the figure.

First, the 0 data generator 21 and the main memory 22 are activated by the 0 (=NIL) data and pointer stored in the map memory in the main memory 22
The operation when accessing the data memory in the 0 data generator 21 and storing data read from the data memory into the first or second memory buffer 15a or 15b will be described.

Step S50...The start address of the map memory is input into the map address register 19. Also, 0 is input to the lower 4 bits of the data address register 20.

Step S51...One of the first and second read line selection circuits 27a and 27b, for example,
The read line selection circuit 27a is selected by a control signal c from a CPU (not shown).

Step S52: Clear the second buffer address register 13b and set it to 0.

Step S53: The map memory in the main memory 22 is accessed via the memory address bus 23 using the map address in the map address register 19.

Step S54: Determine whether the data in the map memory is 0 or not. If no, next step S55
Proceed to. If YES, the process advances to step S62.

Step S55...The map memory data, that is, the pointer, is transferred to the upper part of the data address register 20.
Set it to 16 bit.

Step S56...Access the data memory and
Read the word and place it in the 16 word register 18.

Step S57...Set 1 to data address register 20
Add.

Step S58: It is determined whether a carry has appeared from the lower four bits of the data address register 20 to its upper bit. If no, the process returns to step S56. Steps S56 and S57 are then repeated until step S58 becomes YES. As a result, 16 words of data corresponding to the pointer stored in the data memory are stored in the 16 word register 18.

Step S59...One word of data is transferred from the 16-word register 18 to the second memory buffer 15b via the first read line selection circuit 27a.

Step S60...1 is added to the upper 4 bits of the second buffer address register 13b.

Step S61: It is determined whether a carry has occurred from the upper 4 bits of the second buffer address register 13b. If no, step
Return to S59. Until step S61 becomes YES,
Steps S59 and S60 are repeated. As a result, one unit of data stored in the 16-word register 18 is transferred to the second memory buffer 15b by one word in the main scanning direction and 16 units in the sub-scanning direction.
Stored in the form of a line.

Step S62...If the data in the map memory is 0 in step S54, the 16-bit 0 is transferred from the 0 data generator 21 to the second memory buffer 15b.
Transfer to.

Step S63: Add 1 to the upper 4 bits of the second buffer address register 13b.

Step S64: It is determined whether a carry has occurred from the upper 4 bits of the second buffer address register 13b. If no, the process returns to step S62. Then, steps S62 and S63 are changed to step S64.
is repeated until the answer is yes. As a result, all 0s are transferred to the second memory buffer 1 in the form of 1 word in the main scanning direction and 16 lines in the sub-scanning direction.
5b.

Step S65...Set 1 to map address register 19
is added.

Step S66: It is determined whether a carry has occurred from the lower 8 bits of the second buffer address register 13b. If no, step
Returning to S53, steps S53 to S56 are repeated until step S66 becomes YES.
As a result, the second memory buffer 15b
Data of 256 words in the main scanning direction and 16 lines in the sub-scanning direction is stored. If YES in step S66, the process advances to the next step S67.

Step S67: It is determined whether the value of the map address register 19 has become larger than the value obtained by adding the number of units for one page to the top address set in step S50. If yes,
This means that one page worth of images has been read, so the process ends. If no, proceed to the next step S68.

Step S68...According to the control signal c from the CPU,
The read line selection circuit 27b is selected.
As a result, the first memory buffer 15a is selected.

Step S69: Clear the first buffer address register 13a and set it to 0. below,
The same procedures as steps S53 to S65 are performed.

Step S70: It is determined whether a carry has occurred from the lower 8 bits of the first buffer address register 13a. If no, step
Return to S69. If the answer is yes at step S70,
to the first memory buffer 15a in the main scanning direction.
This means that 256 words and 16 lines of data in the sub-scanning direction are stored.

Step S71...Similar to step S67, it is determined whether the value of the map address register 19 is greater than (starting address + number of units for one page), and if no, the process returns to step S51. The steps described above are then repeated again. If yes, end.

As described above, the compressed image data stored in the map memory and data memory is
The data is stored in the first and second memory buffers in an uncompressed format.

Next, the data stored in the state before compression is transferred to the first and second output line selection circuits 2.
8a and 28b and is output to the P/S converter 29 will be described with reference to the flowchart of FIG.

Step S80...Second output line selection circuit 28b
choose.

Step S81: Clear the first buffer address register 13a and set it to 0.

Step S82...One word is read from the first memory buffer 15a.

Step S83...Add 1 to the first buffer address register 13a.

Step S84: It is determined whether a carry has been output from the first buffer address register 13a. If no, the process returns to step S82. Step S82, until step S84 becomes YES.
S83 is repeated. As a result, 256 words in the main scanning direction are first read out, and when this reading is finished, the process moves to the sub-scanning direction, and 256 words are read out again in the main scanning direction. In this way, 256 words of data in the main scanning direction and 16 lines of data in the sub-scanning direction are read from the first memory buffer 15a.

Step S85: It is determined whether new data has been stored in the second memory buffer 15b. If no, terminate. If YES, proceed to the next step S86.

Step S86...Select the first output line selection circuit 28a.

Thereafter, the same procedures as steps S81 to S84 are performed. This allows 256 words in the main scanning direction and 16 words in the sub-scanning direction from the second memory buffer.
Lines are read out sequentially. When all data has been read from the second memory buffer 15b, the process advances to the next step S87.

Step S87: It is determined whether new data is input to the first memory buffer 15a. If yes, return to step S80,
The same procedure as described above is repeated again from step S80. If no in step S87, the process ends.

As described above, the data stored in the first and second memory buffers 15a and 15b is transferred to the P/S converter 29 one word at a time in the main scanning direction.
When the reading of 256 words is completed, it moves one line in the sub-scanning direction, and then the 256-word line moves in the main scanning direction again.
Words are read out word by word. In this way, 16 lines are read out in the sub-scanning direction. When the reading of one page of images is completed, the operation ends.

In the first and second embodiments described above, the 0 detector 17
and 16 word register 18 are provided, but these are not necessarily required. If 0 is detected on the CPU side, the 0 detector 17 can be omitted. In addition, the memory buffer 15a is 15
If data is transferred directly between the main memory 22 and the main memory 22, the 16-word register 18 can also be omitted.

Furthermore, in the above embodiment, the image data was explained as one unit of 16 dots x 16 words.
Of course, the present invention is not limited to this.
In this case, for example, as a memory buffer, if the number of words for one line of image data in the main scanning direction is L, and the number of lines in the sub-scanning direction constituting one unit is N, then 2m×N (however, 2m ≧L)
Use one with a capacity of Also, instead of the 16-word register 18, an N-word register is used.

〔effect〕

As described above, according to the present invention, 2m words×
Two memory buffers having a capacity of N lines are used, and while data is being read into one memory buffer, data is being read from the other memory buffer. Furthermore, when reading data from the memory buffer, the image data is read out for N lines (one unit) in the sub-scanning direction, and it is detected whether the data for one unit is all 0 or contains data other than 0. .

Therefore, the present invention has the advantage that image data can be compressed at high speed.

Further, if the present invention is used for compressing and restoring image data as in the second embodiment, it becomes possible to compress and restore image data at high speed.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing how an image is divided into units, Fig. 2 is a schematic diagram showing an example of a map memory, Fig. 3 is an explanatory diagram of a data memory, and Fig. 4 is a block diagram of an embodiment of the present invention. 5 and 6 are flowcharts for explaining the operation of FIG. 4,
FIG. 7 is a conceptual diagram of a data memory, FIG. 8 is a block diagram of a second embodiment of the present invention, and FIGS. 9 and 10 are flowcharts for explaining the operation of FIG. 8. 11...S/P converter, 12a, 12b...input line selection circuit, 13a, 13b...buffer address register, 14...buffer control circuit,
15a, 15b...Memory buffer, 16a, 16
b...Output line selection circuit, 17...0 detector, 18
...16 word register, 19...map address register, 20...data address register, 21...0
Data generator, 22... Main memory, 23... Memory address bus, 24... Memory write bus, 25
...Memory read bus, 27a, 27b...Read line selection circuit, 28a, 28b...Output line selection circuit, 29...P/S converter.

Claims (1)

[Claims] 1. The number of words for one line of image data is L, 1
When 1 unit is word x N lines, 2m x
first and second memory buffers having a capacity of N (however, 2m≧L), first and second buffer address registers that address each of the memory buffers, and a memory buffer that is read from the first and second memory buffers. a map memory in which a code indicating whether the data of one unit is all 0 or other is recorded corresponding to the unit;
A data memory is provided in which, when the one unit of data is other than all 0, one unit of image data other than the all 0 is written into an area whose address is a code (pointer) recorded in the map memory, and the first and while writing input image data into one of the second memory buffers in the direction of consecutive memory addresses, read N words continuously from the other memory buffer at addresses every 2m to compress the image data. An image data conversion device characterized by: 2. When restoring the compressed image data, based on the compressed image data,
one of the first and second memory buffers,
Image data conversion according to claim 1, characterized in that while N words are continuously written at addresses every 2m, reading is performed from the other side of the memory buffer in the direction of continuous memory addresses. Device.