JPH0465586B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a solid-state imaging device.

Photodiode or MIS (Metal-
2. Description of the Related Art Solid-state imaging devices are known that generate video signals by sequentially reading out signal charges accumulated in a group of photosensitive elements having an insulator-semiconductor structure by vertical and horizontal scanning. As a practical method for solid-state imaging devices, the 1974 IEEE Intercon
Interline transfer as shown in Technical Papers, Session 2-2
-line Transfer) method. According to this type of solid-state imaging device, a photodiode or
Signal charges for one screen accumulated in the MIS-structured photosensitive element for one frame period are read out to a vertical transfer stage consisting of a CCD during the vertical blanking period in each frame period, and vertically transferred line by line during the horizontal blanking period. is read into a horizontal transfer stage consisting of a CCD,
A video signal is obtained by being read out from the horizontal transfer stage during the horizontal scanning period. As a method for achieving high sensitivity as well as high density integration using this method, for example, the 1980 IEEE ISSCC Digest Vol.
3, session 2 pp34-35, “A Solid State
Color Image Sensor Using ZnSe−Zn(1−x)
Cdx Te Heterojunction Thin−Film
As shown in ``Photoconductor'', a method has been proposed in which the photosensitive area is stacked on the transfer area to increase the area of the photosensitive element.
A transfer stage technology for effectively reading out the amount of accumulated charge increased by increasing the area of the photosensitive element has not been established.

In general, the relationship between increasing the area of the photosensitive element to achieve higher sensitivity and increasing the transfer capacity of the vertical transfer stage that transfers it to the horizontal transfer stage is contradictory. In order to increase the sensitivity and increase the sensitivity, it is a challenge to increase the signal charge storage capacity and transfer capacity of the photosensitive element.

The present invention aims to solve such problems.

The solid-state imaging device according to the present invention temporarily stores signal charges that are sequentially read out at a frame period or field period from a photosensitive element row for one horizontal readout of a two-dimensionally arranged photosensitive element group at the same time within one horizontal period. By applying a predetermined voltage to the transfer electrodes of the multiple MIS structure rows to be transferred to the section, the MIS structure from which the signal charges have been read out, and the subsequent multiple MIS structures along the transfer direction of the signal charges, multiple of
A scanning means that forms a channel to the temporary storage section in the semiconductor substrate through the MIS structure and sequentially changes the voltage of the transfer electrode to a constant voltage along the transfer direction, and transfers signal charges from the temporary storage section to the horizontal transfer stage. It consists of a gate row that reads one horizontal readout at the same time and the horizontal transfer stage.

In this device, unlike interline transfer type solid-state imaging devices, signal charges are read out for one horizontal readout for each horizontal scan to multiple MIS structure columns for vertical transfer, and are passed through the MIS structure columns. It is transferred at high speed to the temporary storage unit within one horizontal period. The scanning pulse for vertically transferring signal charges forms a channel through a plurality of consecutive MIS structures, making it possible to transfer a large amount of signal charges. In addition, since the mode of charge transfer is based on diffusion within the channel, electric field drift occurring at the voltage change point of the transfer electrode during scanning, and movement of the voltage change point due to scanning, sufficient transfer efficiency can be obtained. I can do it.

Furthermore, the MIS structure array does not apply a transfer clock with repeated voltage changes to all transfer electrodes, unlike conventional charge transfer devices such as BBDs and CCDs.
A constant voltage is applied to a plurality of transfer electrodes at the same time, and during transfer, it is possible to drive the transfer electrodes by changing the voltage of, for example, one line, thereby reducing the power required for driving. below,
The present invention will be explained using examples.

FIG. 1 shows the configuration of an embodiment of the present invention. 1 in the figure accumulates optical information from the subject as signal charges, n (n is an even number) in the vertical direction and m in the horizontal direction.
(n/2<m) photodiodes arranged;
Reference numeral 2 indicates an MIS structure, and each MIS structure, as shown in FIG. 2, consists of a semiconductor substrate 101 that is the same as the photodiode 1, an insulating layer 102 formed on the substrate, and independent transfer electrodes 103.
In the semiconductor substrate (here, a P-type semiconductor) under each transfer electrode, a conductivity type opposite to that of the semiconductor substrate is placed on the transfer direction side so as to provide a potential gradient in the signal charge transfer direction (arrow A) of the MIS structure column. Impurity diffusion region 2a
is formed. Further, the thickness of the insulating layer under the transfer electrode 103 is also configured to be different for the same reason.

Reference numeral 3 denotes a line gate that reads out the signal charges accumulated in the photodiode 1 to the MIS structure corresponding to one line selected by the line selection circuit 4 at the same time.
In the field, line selection pulses φ _G1 , φ _G3 ,
Odd-numbered line gates 3 are opened by φ _G5 , ...φ _G (n-1), and even-numbered line gates are opened by line selection pulses φ _G2 , φ _G4 , φ _G6 , ..., φ _G n in the second field. are opened and read out to the same MIS structure 2. Reference numeral 5 indicates scanning pulses φ ₁ , φ ₂ , which are driven by the horizontal transfer clocks φ _H1 , φ _H2 from the pulse generation circuit 6 and are sequentially shifted at the horizontal transfer rate.
. . . A scanning pulse generation circuit that generates φ _N (N=n/2), 7 is a temporary storage region consisting of a row of capacitors 7a, 8 is a gate circuit section consisting of a row of MOS switches 8a, and 9 is a transfer electrode 9a, 9b. Two-phase drive with
This is a horizontal transfer stage consisting of CCD. The configuration of the parallel-to-serial conversion unit that transfers signal charges to the horizontal transfer stage is as shown in FIG. formed by
The MOS switch 8a connects the gate electrode 104 and the CCD
It is constituted by a diffusion region 105 under the transfer electrode 9a and a diffusion region 2a of the MIS structure 2.

The scanning pulse generation circuit 5 receives horizontal transfer clocks φ H1 and φ _H1 from the pulse generation circuit 6 as shown in FIG.
It is composed of a shift register 30 which uses φ _H2 (φ _H1 , φ _H2 in FIG. 4) as a driving pulse. The shift register 30 changes the outputs _{φ 1 , φ 2 ,}
..., _φN are all initialized to a high level, and the start pulse input terminal is grounded. In addition, in Figure 4
V _D shows the pulse waveform of the vertical synchronization pulse with its polarity inverted.

Before explaining the overall operation of this embodiment, charge transfer in the MIS structure array will be explained. Although FIG. 5A partially overlaps with FIG. 2, it shows a part of the structure of the MIS structure sequence. FIGS. 5B and 5C show a potential well formed by a high (H) level or low (L) level voltage applied to the transfer electrode,
FIG. 3 is a diagram schematically showing movement of signal charges. The scanning pulse is the (i-1)th (here iN-3)
The level up to the transfer electrode of MIS structure 2 becomes L level, and i
When the signal charge is at H level, as shown in FIG. 5B, the signal charge is mainly within the MIS structure to which φ _i is applied, and some of the signal charges are at φ _i+1 , φ _i+2 , . . .
is diffused into the MIS structure where is applied.
Next, when φ _i changes from the H level to the L level, the depth of the potential well decreases from the MIS structure to which φ _i is applied, as shown in C of the same figure, and the signal charge decreases due to the electric field drift at this time. adjacent
Move to MIS structure. Moreover, the excess charge further diffuses into the adjacent MIS structure. Here, a two-layer structure of an insulating layer along the transfer direction and a semiconductor substrate 1
The impurity diffusion region 2a having a conductivity type opposite to that of 01 is provided to effectively form a potential gradient.

Now, when reading the signal of the first field, all the output stages of the shift register 30 are initialized to H level by _HD corresponding to the selection of the first line, so that the scanning pulse generation circuit 5 Pulses φ ₁ , φ ₂ , ... φ _N all go to H level, and a potential well is formed in the MIS structure 2 for vertical direction (A) transfer, and a temporary well is formed along each MIS structure row. A channel is formed extending into the storage region 7. In this state, the signal charge of the first line is transferred to the photodiode by the first line selection pulse φ _G1 (φ _G1 in Fig. 4) generated within the horizontal blanking period (here, the latter half of the _{HD pulse} period). 1 to the corresponding MIS structure 2, and spread along the channel.
Next, when the horizontal transfer clocks φ _H1 and φ _H2 are applied to the shift register 30, since the start pulse input terminal is grounded, the outputs of each stage φ ₁ , φ ₂ , φ as shown in FIG. ₃ , ..., _φN sequentially changes to the L level (zero), and due to the electric field drift at this time, the signal charge moves inside the channel temporarily into the accumulation region 7.
is transferred to the capacitor 7a. Due to the Nth cycle horizontal transfer clocks φ _H1 and φ _H2 , the Nth stage output φ _N of the shift register 30 goes to L level.
At this time, the transfer of signal charges to the temporary storage region 7 is completed. Depending on the horizontal transfer clocks φ _H1 and φ _H2 from the subsequent (N+1)th cycle to the mth cycle, the state of each output stage of the shift register 30 remains unchanged and remains at the L level.

In this state, a gate pulse _φGH generated in the gate electrode 104 of the MOS switch 8a during the next horizontal blanking period (here, the first half of the _HD period) is applied to the gate electrode 104 of the MOS switch 8a.
When (φ _GH in FIG. 4) is applied, signal charges for one line are simultaneously read into the diffusion region 105 under the transfer electrode to which φ _H2 of the CCD of the horizontal transfer stage 9 is applied.
The signals are sequentially transferred by clocks φ _H1 and φ _H2 applied during the horizontal scanning period, and read out through the output terminal 10 to obtain one line of video signals. On the other hand, even in the horizontal period in which the signal charges of the first line are transferred through the horizontal transfer stage 9, the shift register 30 is initialized at the rising edge of _HD , and the first
Similarly to the line readout, a channel is formed along the MIS structure column, and the line gate 2 of the second line is opened by the second line selection pulse after the gate pulse φ _GH . A signal charge is read into the channel from the photodiode 2 of. Then, during the horizontal scanning period when the signal charges of the first line are read out through the horizontal transfer stage, the second
A scanning pulse φ ₁ from the shift register 30 in which the signal charges of the line are driven by the same transfer clock,
The data is transferred to the temporary storage area 7 within the MIS structure sequence by φ ₂ , . . . , φ _N.

Similarly, signals are sequentially read out from every other photodiode row to the corresponding MIS structure 2,
The signal is transferred at high speed to the temporary storage area 7 within one horizontal scanning period through each MIS structure column, and read out through the horizontal transfer stage 9 during the next horizontal scanning period, thereby obtaining a video signal for the first field. In _the second field, even-numbered line gates 3 are opened by line selection pulses φ _G2 , φ _G4 , φ _G6 , . The configuration of the line selection circuit 4 that operates as described above does not require any particular explanation, but for example, it is controlled by an N (n/2) stage shift register V _D whose output is sequentially shifted in synchronization with _HD . The output of each stage of this shift register is 1 for each field.
It can be constructed from switching circuits for applying to different ones of a pair of line gates.

According to this configuration, the signal charge from the photodiode 1 is read out to the channel extending to the temporary storage region 7 along the MIS structure row, so it is vertically transferred like in an interline transfer type solid-state imaging device. There is an advantage that the capacity can be increased regardless of the size of each bit cell of the vertical transfer CCD. Therefore, it becomes possible to narrow the width of the MIS structure, and it becomes possible to achieve higher integration or higher sensitivity by increasing the area of the photosensitive element. Also,
In the MIS structure, a high level is applied to all transfer electrodes at the beginning of each horizontal period, and only changes to a low level thereafter, so the vertical transfer clock is applied to all transfer electrodes, reducing the capacitive load. Compared to driven interline transfer type solid-state imaging devices, power consumption is lower.

The applied voltage waveform at the beginning of each horizontal period is pure at the rising edge due to the large capacitive load, but
There is no problem as long as a channel is formed in the MIS structure array when the line selection pulse is applied.

Although the above example shows that signal charge transfer through the MIS structure array is performed using diffusion and a single electric field drift, it is also possible to use two or more electric field drifts. An example of the scanning pulse generating circuit 5 of such an embodiment is shown in FIG.

In this embodiment, a monostable multivibrator (MM) 41, a counter 42 and an AND
The circuit 43 is replaced by the start pulse generating section of the scanning pulse generating circuit shown in FIG. In this embodiment, the MM41 is triggered by the _HD and generates a pulse that has a time width until approximately seven pulses of the horizontal transfer clocks φ _H1 and φ _H2 are generated (7th pulse).
figure). The counter 42 is a three-piece counter that is reset by the _HD and counts φ _H1 .
A start pulse as shown in FIG. 7 _φST is obtained from the AND circuit 43. As a result, the scanning pulses obtained from each stage of the shift register 30 are as shown in FIG. 7, φ ₁ ', φ ₂ ', . . . .

In this case, each MIS structure will continue during the extinction of the first potential well, and a second field drift will occur during the extinction of the potential well formed by the next positive pulse, which will cause the initial field drift to occur. It is possible to transfer the residual charges that remained untransferred.

In the above embodiment, the transfer clock pulses φ _H1 and φ _H2 of the horizontal transfer stage 9 are used as the driving pulses for the scanning pulse generating circuit 5. Although it is not necessarily necessary to use horizontal transfer clock pulses in the present invention, this embodiment has advantages such as being able to use a common clock source and not making noise countermeasures difficult. When the number m of picture elements in the horizontal direction is equal to or larger than the number n of picture elements in the vertical direction, the horizontal transfer clocks φ _H1 and φ _H2 are used as driving pulses for the scanning pulse generation circuit 5 by dividing the frequency to 1/2. You can also do that.

As shown in FIG. 8A, the MIS structure 2 for vertical transfer includes, in addition to the structure shown in FIG. An impurity region 2b is formed, as shown in FIG.
As shown in FIG. 2, the electric field drift effect can be enhanced by increasing the number of steps in the potential gradient along the signal charge transfer direction.

The diffusion region 2a or 2b under the transfer electrode of the MIS structure is not essential in the present invention.
As shown in FIGS. 9A and 9B, it is also possible to use an array of MIS structures without these diffusion regions.
The figure schematically shows the change in the potential well and the transfer of signal charges when the transfer electrode 105 or 103 of the i-th MIS structure changes from the H level state to the L level state. Figure 9A
In this case, the thickness of the insulating layer is constant throughout the MIS structure array, and in this case, the potential wells have little undulation, and signal charges can easily diffuse. In these cases, in order to enhance the electric field drift effect, the length of the MIS structure in the signal transfer direction is shorter than that of the configuration in Figure 1.
It is also possible to provide one or more MIS structures for one photosensitive element.

Furthermore, the channel formed when reading out one line of signal charges from the photosensitive element does not necessarily have to extend to the temporary storage region, but rather extends to multiple consecutive MIS structures, including one from which the signal charges are read out. Potential wells may be formed and short channels may be formed. In this case, the scanning circuit performs vertical signal charge transfer by moving a short channel during the horizontal scanning period, and also determines the position where the channel is formed for each line, corresponding to the selected line. It is necessary to shift the

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the solid-state imaging device according to the present invention, FIG. 2 is a cross-sectional view showing the schematic structure of the main parts of the device, and FIG. 3 is a diagram of the scanning pulse generation circuit in the device. A block diagram showing the configuration, FIG. 4 is a waveform diagram of the main parts of the device, FIG. 5 is a cross-sectional view and potential diagram to explain the operation of the MIS structure array, which is the main part of the device, and FIG. A block diagram showing the configuration of a scanning pulse generation circuit of a solid-state imaging device in another embodiment of the present invention, FIG. 7 is a waveform diagram of the main part thereof, and FIGS. 8 and 9 are still other embodiments of the present invention. FIG. 2 is a cross-sectional view and a potential diagram showing an MIS structure of a solid-state imaging device in FIG. 1...Photodiode, 2...MIS structure, 3
...Line gate, 4...Line selection circuit, 5...
...Scanning pulse generation circuit, 6...Pulse generation circuit,
7...Temporary storage area, 8...Gate circuit section, 9...
...Horizontal transfer stage.

Claims (1)

[Scope of Claims] 1. A photosensitive element group that accumulates signal charges according to the amount of incident light, and a plurality of photosensitive element groups that transfer signal charge trains read from the photosensitive element rows in the photosensitive element group within one horizontal period.
an MIS structure column; a first gate means for reading the signal charge column to the plurality of MIS structure columns for each horizontal scan; and a first gate means for temporarily accumulating the signal charge column transferred by the plurality of MIS structure columns. A temporary storage means, an MIS structure for reading signal charges within one horizontal period, and an MIS structure along the direction of signal charge transfer thereafter.
Applying a predetermined voltage to each transfer electrode of the structure to form a channel in the semiconductor substrate of each MIS structure row to the temporary storage means, and converting the voltage to another predetermined voltage different from the predetermined voltage. scanning means for sequentially changing the signal charge and transferring it to the temporary storage means; horizontal transfer means for transferring and outputting the signal charge read from the temporary storage means during the horizontal scanning period; and from the temporary storage means to the horizontal transfer means. A solid-state imaging device comprising: second gate means for transferring signal charges during a horizontal blanking period. 2. The first gate structure reads out signal charges accumulated for one frame period from the first photosensitive element group in the first field to the MIS structure, and 2. The solid-state imaging device according to claim 1, further comprising a second gate structure for reading signal charges accumulated for one frame period from a second photosensitive element group different from the photosensitive element group to the MIS structure. 3. The solid-state imaging device according to claim 2, wherein one or more MIS structures are provided for each photosensitive element in the group of photosensitive elements. 4. Claim 2 in which one MIS structure is connected to two photosensitive elements in a group of photosensitive elements
The solid-state imaging device described in Section 1. 5. Claims 1 and 2, in which the MIS structure has an impurity diffusion region of a conductivity type opposite to that of the semiconductor substrate in the semiconductor substrate on the side in the signal charge transfer direction.
The solid-state imaging device according to item 3 or 4. 6. Claims 1 and 2 in which the MIS structure has an impurity diffusion region of the same conductivity type as the semiconductor substrate in the semiconductor substrate on the opposite side to the direction of signal charge transfer.
3. The solid-state imaging device according to item 3, item 4, or item 4. 7 Claim 1 in which the thickness of the insulator of the MIS structure has a step where it becomes thinner in the direction of signal charge transfer.
The solid-state imaging device according to item 2, item 3, or item 4. 8 The scanning means scans all of the MIS structure arrays.
A predetermined voltage is applied to the electrodes of the MIS structure, and each MIS
A channel is formed in the semiconductor substrate along the structure row to reach the temporary storage means, and a signal is applied to the transfer electrode of the MIS structure row by sequentially changing the predetermined voltage to another different voltage from the side farther from the temporary storage means. 2. The solid-state imaging device according to claim 1, wherein the charge is transferred to temporary storage means.