JPH0465724A - interrupt processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a program interrupt processing device, and in particular, the present invention relates to a program interrupt processing device, and more particularly, to a program interrupt processing device that adjusts the interrupt period of a timer interrupt signal corresponding to a timer interrupt program according to the content of the program. Concerning the selected interrupt processing device.

[Prior Art] Currently, the processing speed of CPUs has become faster, so in many cases, the successive processing and writing processing for peripheral Ilo are much slower than for general memories.

In read processing and write processing for such slow things,
Each waits for successive processing cycles or write processing cycles (
WAIT) state and the above cycle is extended until the information is confirmed, but if there are multiple cycles that are too slow compared to the normal cycle,
The CPU will have a lot of idle time, resulting in inefficiency.

For example, in the case of a matrix key such as a touch panel, it may take nearly 100 microns (more than 100 times the usual time) to perform successive processing, and there are a plurality of keys (several tens to hundreds).

In order to solve the above-mentioned situation, it is conceivable to use timer interrupt processing to execute Ilo successive processing and writing processing. The data read by the timer interrupt processing is written in a table in a RAM that has a quick access time. In a normal program, the RAM table is considered to be a keyboard and successive processing is executed, and the timer interrupt cycle of the timer interrupt processing is set to be sufficiently longer than the key successive cycle.

[Problem to be solved by the invention]

However, when executing the timer interrupt processing as described above, in order to improve the response of the keys, the key is captured even when no human effort is required. , ■Key import processing,
(2) It is necessary to execute timer interrupt termination processing, and the existence of locations where key reading is unnecessary increases the load on the CPU, resulting in a problem that the overall processing speed decreases.

The present invention has been made in view of the above, and aims to reduce the burden on the CPU due to the existence of locations where key reading is not necessary, and to increase the overall processing speed.

[Means to solve the problem]

In order to achieve the above object, the present invention provides an interrupt vector table in which a program address at the time of an interrupt is written, and an interrupt vector table corresponding to the address of the interrupt vector table.
A storage means for storing a timer interrupt program divided into a plurality of blocks, and a timer interrupt signal having an interrupt period corresponding to the content of each timer interrupt program stored in the storage means is selectively generated. The present invention provides an interrupt processing device including a timer interrupt signal output means for outputting a timer interrupt signal.

[For production]

The interrupt processing device according to the present invention divides the timer interrupt program corresponding to the address of the program written in the CPU interrupt cover table into a plurality of blocks depending on the necessity of timer interrupt processing and necessary contents. and store it in memory.

A timer interrupt process is executed by selecting an interrupt period corresponding to the timer interrupt program stored in the memory and outputting the selected timer interrupt signal to the interrupt controller.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an interrupt processing device according to the present invention. an interrupt vector table 101;
A plurality of interrupt programs corresponding to the addresses in the interrupt vector table 101 are stored via a memory 102 and a data bus 104, which are divided into blocks according to the necessity of timer interrupt processing and necessary contents. and a timer interrupt signal output section 103.

The timer interrupt signal output unit 103 includes a latch circuit 105 that outputs a select signal according to input contents, and a clock signal output from a crystal oscillator (not shown), which is frequency-divided and divided into several ways. A frequency divider 106 and a counter 107 that generate an integrated clock, and an interrupt controller that selectively outputs the output from the frequency divider 106 and the plurality of outputs from the counter 107 as a timer interrupt signal using a select signal from the latch circuit 105. (not shown).

As shown in FIG. 2A, the program in the memory 102 shown in FIG. 1 is divided into several blocks depending on the necessity and necessary contents of timer interrupt processing. Execute.

In block A in the main routine, two of the lid table (step 201) and interrupt signal (202) are selected and set for interrupts as necessary at the beginning of block A. The normal routine was then executed (step 20
After 3), for example, the combination that is used most often throughout is set as the default (step 204), and the interrupt vector table 101 is returned to the default (step 204), and the interrupt signal is returned to the default ( Step 205) End the series of operations.

FIG. 3 is an explanatory diagram showing the configuration of the memory 102 (RAM), as shown in FIG. 3A (the memory 102 consists of an interrupt vector table group and a timer interrupt program; As shown in Figure 3B, the above interrupt vector table group includes interrupt vector table l and interrupt vector table 2.
... consists of interrupt vector table n, the timer interrupt program is an interrupt program called by the above interrupt vector table 1, an interrupt program called by the above interrupt vector table 2...the above interrupt vector table n It consists of an interrupt program that is called.

The operation of the above configuration will be explained.

In the timer interrupt signal output section 103, the clock signal from the crystal oscillator is divided by the frequency divider 106, and further by the counter 107 and the selector 108 is divided into 1/L 1/
Each timer interrupt signal having a timer interrupt frequency of 2.1/4.1/8.1/16 is made selectable.

In this state, the latch circuit 10 with a certain address
Selector 10 selects the interrupt clock with which period for 5.
8. Write your selection.

As a result, the output of the latch circuit 105 (select signal)
is input to the selector 108, and the timer interrupt signal written in the latch circuit 105 is output from the selector 108 to the interrupt controller.

Furthermore, although it is possible to rank only based on the contents of the blocks shown in FIG. By taking into account the amount of interrupts other than timer interrupts as a factor for ranking, more effective interrupt processing can be performed.

These two elements enable ranking, for example, as shown in Table 1 below.

Table 1 After the ranking is determined as shown in Table 1, the interrupt clock for the timer interrupt is selected according to the rank as follows.

Rank 1: Enable timer interrupts as usual (1/1).

Rank 2: Set the frequency of timer interrupt processing to 1/2.

Rank 3: Set the frequency of timer interrupt processing to 1/4.

Rank 4: Stop key capture and set the frequency of timer interrupt processing to 1/4.

With the above configuration, when looking at the time size as shown in FIG. 4A, compared to the conventional timer interrupt routine, the present invention eliminates unnecessary processing and The time required for judgment can be omitted and rapid program processing can be realized.

Also, looking at the time flow as shown in Figure 4B, rank 1 (normal (1/1), timer interrupts are allowed) and rank 2 (timer interrupt processing frequency is In the main routine processing, rank 2 (double cycle) takes less time t than rank 1.
You can spend more time processing.

Although the timer interrupt signal output section in the above embodiment is composed of a frequency divider, a latch circuit, a counter, and a selector, it is not limited thereto, and an LSI such as a programmable interval timer can also be used.

〔Effect of the invention〕

As explained above, according to the interrupt processing device of the present invention, the interrupt handler table in which the address of the program at the time of an interrupt is written, and the plurality of blocks corresponding to the addresses of the interrupt vector table. A storage means for storing divided timer interrupt programs, and a timer interrupt for selectively outputting a timer interrupt signal with an interrupt period according to the contents of each timer interrupt program stored in the storage means. Since the present invention is equipped with an input signal output means, it is possible to reduce the burden on the CPU due to the existence of locations where key reading is not necessary, and to increase the overall processing speed.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the configuration of an interrupt processing device according to the present invention, FIG. 2A is an explanatory diagram showing a state in which a program is divided into a plurality of blocks depending on the necessity of timer interrupts and necessary contents, FIG. 2B is a flowchart showing the operation of one block when the program is divided into multiple blocks, FIGS. 3A and B are explanatory diagrams showing the memory configuration shown in FIG. 1, and FIG. FIG. 4A is an explanatory diagram showing the effect of the time size of the present invention in comparison with a conventional timer interrupt routine, and FIG. 4B is an explanatory diagram showing the effect regarding the temporal flow in a normal cycle and a double cycle. . Explanation of symbols 101 - Interrupt vector table 102 - Memory 103 - Timer interrupt signal output section 104 - Data bus 105 - Latch circuit 106 -
-Frequency divider 10'l-Counter 1os---Selector

Claims (1)

[Scope of Claims] An interrupt vector table in which the address of a program at the time of an interrupt is written, and a memory that stores a timer interrupt program divided into a plurality of blocks corresponding to the addresses of the interrupt vector table. and timer interrupt signal output means for selectively outputting a timer interrupt signal with an interrupt cycle corresponding to the contents of each timer interrupt program stored in the storage means. Interrupt processing device.