JPH0465742A - Bus repeater - Google Patents

Abstract

PURPOSE:To prevent the simultaneous stop of the operation of all I/O control devices by providing the bus repeater with an extended bus arbitration circuit for inhibiting the application of bus using right to an I/O control device generating an error at the time of generating the error. CONSTITUTION:Information indicating which I/O control device 105 receives bus using permission is obtained from the extended bus arbitration circuit 118 and stored in a write control buffer 112. At the time of detecting abnormality in writing operation, a main storage device 104 outputs an abnormal response and the bus repeater 100 reads out the contents of the buffer 112, decides the I/O control device starting write transfer generating the error by an error control circuit 117, and controls an extended bus 102 by the circuit 118 so as not to apply bus use permission to a bus use request outputted from the I/O control device generating the error. Since only the I/O control device relating to abnormality can be disconnected, other I/O control devices can be prevented from being stopped at their operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus relay device, particularly a basic bus to which a central processing unit, a main storage device, and an input/output control device are connected, and an input/output control device to which the input/output control device is connected. The present invention relates to a bus relay device that relays bus transfer with an expansion bus.

[Conventional technology]

Conventionally, in this type of bus relay device, when a write transfer from the expansion bus caused an error on the basic bus and ended abnormally, the bus transfer on the expansion bus had already ended, so the device that started the bus transfer could not be notified of the occurrence of an error.

Therefore, to prevent processing inconsistencies, all input/output control devices under the expansion bus were stopped after the error occurred.

[Problem to be solved by the invention]

In the conventional bus relay device described above, when one input/output control device malfunctions, all other input/output control devices connected under the expansion bus also stop operating.

[Means to solve the problem]

The device of the present invention is a bus relay device that relays bus transfer between a basic bus to which a central processing unit, a main storage device, and an input/output control device are connected, and an expansion bus to which an input/output control device is connected. An address buffer that stores addresses for data write transfers to the basic bus, a data buffer that stores write data, and a control buffer that stores arbitration information that indicates which input/output control device on the expansion bus initiated the bus transfer. , an error control circuit that determines which input/output control device caused the error based on the output of the control buffer when a bus transfer on the basic bus ends abnormally due to an error; and an error control circuit that arbitrates the right to use the expansion bus. and an extended bus arbitration circuit that operates so as not to grant bus usage rights to input/output control devices instructed by the error control circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the bus relay device of the present invention.

A bus relay device 100 of the present invention is connected to a central processing unit 103 and a main storage device 104 via a basic bus 101. Further, the input/output control device 105 is connected to the bus relay device 100 via the expansion bus 102. Write transfer from the input/output control device 105 to the main storage device 104 is performed via the bus relay device 100.

First, the input/output control device 105 requests the expansion bus arbitration circuit 118 in the bus relay device 100 to use the expansion bus 102 in order to obtain the right to use the expansion bus 102.The expansion bus arbitration circuit 18 controls input/output of the expansion bus 102. It is determined whether the device 105 can be used, and if it is, permission to use the input/output control device 105 is given.

The input/output control device 105 that has been given permission to use is the expansion bus 102
Since the present invention relates to write transfer, only write transfer will be explained here, and explanations of other transfers will be omitted.

In the case of write transfer, the input/output control device 105 uses the expansion bus 1.
Outputs the transfer address and write data to 02.

The input/output device 105 waits for a response from the transfer destination, and ends the bus transfer when there is a normal or abnormal response from the transfer destination.

The final transfer destination of the bus transfer initiated by the input/output control device 105 is the main storage device 104, but in order to speed up the transfer, the bus relay device 100 does not receive transfer addresses and write data from the expansion bus 102. A normal response is output to the input/output control device 105 at the time the input/output control device 105 is received. When a normal response is returned, the input/output control device 105 determines that the write transfer has ended normally, and proceeds to the next process.

The bus relay device 100 stores the received transfer address and write data in the write address buffer 100 and write data buffer 111. At that time, the extended path arbitration circuit 118 transmits arbitration information indicating which input/output control device has been granted permission to use the bus.
and stores it in the write control buffer 113.

The expansion bus interface circuit 116 is a circuit that controls bus transfers on the expansion bus 102, and the basic bus interface circuit 114 is a circuit that controls bus transfers on the basic bus 101. Further, the transfer control circuit 115 is connected to the basic bus 10.
1 to the expansion bus 102 or from the expansion bus 102 to the basic bus 101.

The transfer control circuit 115 is the expansion bus interface circuit 11
4 receives a write transfer from the input/output control device 105, it issues a transfer request to the basic bus interface circuit 114. After obtaining the right to use the basic bus 101, the basic bus interface circuit 114 transfers the transfer address from the write address buffer 110 to the write data buffer 11.
The write data is read from 1 and output to the basic bus 100.

The main storage device 104 outputs a normal response to the basic bus 101 when the writing is completed normally. Bus relay device 10
When 0 receives a normal response from the basic bus 101, it ends the bus transfer and completes the bus transfer transmission operation.

When the main storage device 104 detects any abnormality in the write operation, it outputs an abnormal response to the basic bus 101 instead of a normal response. When the bus relay device 100 receives an abnormal response from the basic bus 101, it reads the contents of the write control buffer, and uses the error control circuit 117 to determine the input/output control device that started the write transfer in which the error occurred. The expansion bus arbitration circuit 118 controls the bus usage request from the input/output control device instructed by the error control circuit 118 so as not to grant permission to use the bus.

〔Effect of the invention〕

As explained above, when a write transfer is executed from the input/output control device on the expansion bus to the storage device on the basic bus using the bus relay device of the present invention, if an abnormality occurs on the basic bus, the related input/output This has the effect of allowing only the control device to be separated.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the bus relay device of the present invention. 100... Bus relay device of the present invention, 101... Basic bus, 102... Expansion bus, 103... Central processing unit, 104... Main storage device, 105... Input/output control device, 110...Write address buffer, 111...
...Write data buffer, 112...Write control buffer, 114...Basic bus interface circuit, 115...Transfer control circuit, 116...Expansion bus interface circuit, 117...Error control circuit,
118...Extended bus arbitration circuit.

Claims (1)

[Scope of Claim] A bus relay device that relays bus transfer between a basic bus to which a central processing unit, a main storage device, and an input/output control device are connected and an expansion bus to which an input/output control device is connected, comprising: An address buffer that stores addresses for data write transfers to the basic bus, a data buffer that stores write data, and a control buffer that stores arbitration information that indicates which input/output control device on the expansion bus initiated the bus transfer. , an error control circuit that determines which input/output control device caused the error from the output of the control buffer when a bus transfer on the basic bus terminates abnormally due to an error; and an error control circuit that arbitrates the right to use the expansion bus. an extended bus arbitration circuit that operates so as not to grant bus usage rights to input/output control devices instructed by the error control circuit.