JPH0465986B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed signal generation circuit that converts the pulse rate of a pulse encoder (hereinafter referred to as PG) into a speed signal in a servo system or the like.

[Conventional technology]

Conventionally, a small DC generator (tachogenerator) was used to detect the rotational speed of a motor, etc., but in order to make the device smaller and lighter,
The tachogenerator was omitted, and the output pulses of the pulse encoder used for position detection were converted into voltage by an F/V converter. However, F/
A servo system using a V converter had a large ripple component in the output voltage at low speeds, so it was considered impossible to use it for NC, etc.

Therefore, by generating clock pulses with a period of 1/16 of the PG output pulse interval and interpolating between the PG output pulses, we integrate these pulses in an analog manner to reduce the ripple component of the output voltage. A signal generating circuit has been devised (Utility Application No. 118297/1983).

[Problem to be solved by the invention]

However, in the above-mentioned conventional device that integrates pulses in an analog manner, the output voltage contains a considerable ripple component, and most of the circuits in the device are constructed of analog circuits.
The drawback was that accuracy deteriorated due to temperature drift, etc.

An object of the present invention is to provide a speed signal generation circuit that removes ripple components and generates a highly accurate speed signal.

[Means to solve the problem]

The speed signal generating circuit of the present invention has a reversible counter that counts output pulses of a pulse encoder, and an integrating means that outputs a reversible pulse rate proportional to the count value of the reversible counter, and the output of the integrating means is provided as a reversible counter. Of the two input terminals, the one that reduces the absolute value of the count is connected to the one that reduces the absolute value of the count.

[Effect]

The present invention creates a reversible pulse rate proportional to the pulse rate output from the PG, and tracks and compares these pulse rates with a reversible counter.

Count value of reversible counter (digital speed signal)
When converted into an analog voltage by a D/A converter, pulse ripple at low speeds will not be a problem at all, the output with respect to speed can be perfectly linear, and the accuracy of temperature drift etc. is D. This is due to the characteristics of the /A converter only.

Note that the count value of the reversible counter can be input to a CPU or the like and used for other digital calculations.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a follow-up comparison type speed signal generation circuit according to an embodiment of the present invention.

Reversible counter 1 has up terminal UP and down terminal
By inputting a pulse to DOWN, it is incremented and decremented respectively, and the most significant bit (hereinafter referred to as
A count value N in which a plus/minus sign (“0” when positive and “1” when negative) is attached to the MSB is output to the data bus 12. The D/A converter 2 converts the count value N on the data bus 12 into an analog voltage V and outputs it. Arithmetic circuit (hereinafter referred to as ALU)
3 is the count value N on data bus 12 and data bus 1
4 is added to the output value of the D flip-flop 4, and the calculation result is output to the data bus 13, and the carry C generated as a result of the calculation is output from the carry terminal _CO . The D flip-flop 4 transfers the data on the data bus 13 when the clock pulse CP is applied to the data bus 1.
Output to 4. The AND circuit 5 performs a logical product of the MSB of the count value N on the data bus 12, the inverted signal of the clock pulse CP by the inverter 11, and the inverted signal of the carry C from the ALU 3 by the inverter 7, and outputs an up pulse _PU . The AND circuit 6 outputs the inverted signal from the inverter 8 of the MSB of the count value N on the data bus 12 and the clock pulse CP.
The inverted signal from inverter 11 and the carry C from ALU 3 are ANDed and a down pulse is generated.
Output P _D. NOR circuits 9 and 10 take a NOR between a positive pulse +P and an up pulse P _U and a negative pulse -P and a down pulse _PD generated from a PG (not shown), respectively. Here, ALU3,
D flip-flop 4, inverter 7, 8, 1
1. AND circuits 5 and 6 constitute an integrating means.

Next, the operation of this embodiment will be explained.

First, when positive direction pulses +P are continuously input from PG to the NOR circuit 9, the count value N of the reversible counter 1 is increased. At this time, since the count value N is positive, the MSB is "0". This count value N
is added to the data on the data bus 14 by the ALU 3, and the result of this addition is added to the data bus 14 by the D flip-flop 4 at every clock pulse CP.
It is outputted to the count value N and added to the count value N again. In this way, when a carry C is generated as a result of addition in ALU3, this carry C is a carry terminal.
Input from C _O to AND circuit 6, down pulse P _D
is input to the down terminal DOWN of the reversible counter 1 through the NOR circuit 10, so the reversible counter 1
The count value N is decremented by 1.

As the pulse rate of the pulse +P from PG increases, the count value N increases and the carry C is output more frequently from the ALU 3, so the pulse rate of the down pulse P _D also increases. In this way, the count value N
is in a balanced state, and a stable output voltage can be obtained from the D/A converter 2.

Furthermore, when a negative direction pulse -P is input from PG, the count value N becomes negative, so the MSB becomes "1", and the up pulse P _U is input from the AND circuit 5.
passes through the NOR circuit 9 to the up terminal of the reversible counter 1.
Entered into UP. Therefore, the count value N becomes balanced in the same way as when the positive direction pulse +P is input from PG.

Incidentally, since the pulse rates of the up pulse _PU and the down pulse _PD are proportional to the frequency of the clock pulse CP, the gain of the output voltage can be changed by changing this frequency.

In this embodiment, instead of generating the up pulse P _U and the down pulse _PD using the ALU 3, D flip-flop, AND circuits 5, 6, and inverters 7, 8, and 11, as shown in FIG.
Bidirectional as disclosed in Utility Application No. 58-56266
BRM circuit 15 and D flip-flop 16
A similar effect can be obtained by creating an up pulse P _U and a down pulse _PD using The bidirectional BRM circuit 15 and the D flip-flop 16 constitute an integrating means. Here, the D flip-flop 16 is provided to prevent the input data to the binary rate multiplier 15a from changing before one cycle of the bidirectional BRM circuit 15 is completed.

In addition, by installing a digital pulse width conversion circuit before the D/A converter 2 shown in FIGS. 1 and 2, it becomes possible to isolate the digital part and analog circuit, and also to It is also possible to omit the converter 2 and directly take out the digital speed signal and use it for other digital calculations by the CPU or the like.

〔Effect of the invention〕

As explained above, the present invention creates a reversible pulse rate proportional to the pulse rate output from the PG, and by tracking and comparing these pulse rates with a reversible counter, an analog speed signal is obtained using a D/A converter. In this case, it is possible to generate a highly accurate speed signal from which ripple components have been removed, and the digital speed signal can also be used for other calculations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a follow-up comparison type speed signal generation circuit according to one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment. 1... Reversible counter, 2... D/A converter, 3... ALU, 4, 16... D flip-flop, 5, 6... AND circuit, 7, 8, 11...
...Inverter, 9,10...NOR circuit, 12,1
3, 14...Data bus, 15...Bidirectional BRM
Circuit, 15a...Binary rate multiplier, 15b...Demultiplexer.

Claims (1)

[Claims] 1. A speed signal generation circuit that converts a pulse rate output from a pulse encoder into a speed signal, comprising: a reversible counter that counts output pulses of the pulse encoder; and a speed signal that is proportional to the count value of the reversible counter. and an integrating means for outputting a reversible pulse rate, the output of the integrating means being connected to one of the two input terminals of the reversible counter that reduces the absolute value of the count. Signal generation circuit.