JPH04660A - Inter-processor communication method - Google Patents

Abstract

PURPOSE:To improve the communication efficiency between processors by executing the transmission by a single transmission request, in the case a transmitting message from the processor of a processing request origin is transmitted simultaneously to plural processors. CONSTITUTION:In the system in which a system controller 100, a first - a fourth CPUs 101-104, a shared memory 1, and an I/O controller 110 are connected to a high speed bus 6, at the time of inter-processor communication between a first - a fourth CPUs 101-104, addresses of processors of plural processing request destinations are put in advance in a message of a processing request. In such a state, an address of the processing request destination processor contained in a processing request from a processing request origin is checked up, and when there are plural request destinations, all the processors are informed of the processing request. In such a way, an efficient multi-processor system can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inter-processor communication method in a multiprocessor system.

[Conventional technology]

-g The purpose of a multiprocessor system is to perform high-speed processing by dividing the functions of the system and assigning each function to a dedicated processor.

In a multiprocessor system, communication between processors is essential, and how efficiently communication between processors can be performed is an issue for multiprocessor systems.

Conventionally, there have been the following types of inter-processor communication.

Figures 5 and 6 are, for example,
5 is a block diagram of a multiprocessor system, and FIG. 6 is an operational diagram of inter-processor communication.

In FIG. 5, 1 is a shared memory, 2 is a job processor, 3 is a file control processor, and 4 is an I10
a control processor, 5 a communication control processor, 6 a high-speed bus, 7 an input/output device,
8 is a ring bus, 9 is an input/output device, 10 is a communication circuit, 1
1 is another system.

Further, in FIG. 6, 22 is a communication buffer, 23 is a device control table, 24 is an inter-processor communication queue pointer for the I10 control processor 4, and 25 is an inter-processor communication queue pointer for the job processor 2.

Next, the operation will be explained. First, in FIG. 5, various input/output devices 9 are connected via the ring bus 8.
Here, an I10 control processor 4 and a job processor 2 for interrupt processing and driving the input/output device 9 are shown.
We will explain the input/output method between.

Further, FIG. 6 is an operation related diagram showing an overview of inter-processor communication in this case, in which solid arrows indicate the flow of data, and dashed arrows indicate the flow of control signals.

In the job process 72 that processes the user task, the control job necessary for input/output execution is sent to the communication buffer 2 by the input/output request macro instruction issued by the user task.
2, connect to the inter-processor communication queue pointer 24 for I10 control processor 4 (see API)
, an inter-processor communication side connection (see AR2) is applied to the I10 control processor 4. Thereafter, the user task waits for the end of input/output execution in order to synchronize program processing and input/output execution processing, and control is transferred to another task.

When the I10 control processor 4 receives an inter-processor communication side request (see AR2) from the job processor 2, it receives a request from the communication buffer 22 connected to the inter-processor communication queue pointer 24 for the I10 control processor 4. Extract the I10 device number.

Then, it is checked by the device control table 23 whether the input/output device 9 is in use. Therefore, if the input/output device 9 is vacant, input/output operation commands to be transferred to the input/output device 9 and data for input/output device operation are created from the control information stored in the communication buffer 22 ( (See AR3)
, outputs a start command to the input/output device 9 (see AR4).

When the input/output operation is completed, the input/output device 9 returns an input/output completion report to the I10 control processor 4 (see AR5). Then, upon receiving the input/output completion report from the input/output device 9, the I10 control processor 4 connects the input/output result to the inter-processor communication queue pointer 25 of the job processor 2 in the communication buffer 22 (
(see AR7), and an inter-processor communication connection (see AR8) is applied to the job processor 2.

When the job processor 2 receives an inter-processor communication request from the I10 control processor 4, it deletes the communication buffer 22 connected to the inter-processor communication queue pointer 25 for its own processor from the queue (see AR9), input/output. The processing result is returned as a return code to the I/O request macro instruction issuing task, and the task is released from the I/O execution completion waiting state. This operation completes a series of I/○ input/output execution controls.

[Problem to be solved by the invention]

Conventional inter-processor communication methods are configured as described above, so when sending the same processing request to multiple processors, it is necessary to issue as many processing requests as there are requesting destinations, which makes efficient multiprocessor communication possible. There was a problem that the system could not be configured.

The present invention has been made in view of these points, and its purpose is to transmit the same processing request to multiple processors by sending the processing request only once. An object of the present invention is to provide an efficient communication method between multiprocessors that allows processing requests to be made at the same time.

[Means to solve the problem]

In order to achieve such an object, the present invention is such that addresses indicating a plurality of processors to which processing requests are made are included in a processing request message.

[Effect]

In the inter-processor communication method according to the present invention, the address of the processing request destination processor included in the processing request from the processing request source is checked, and when there are multiple request destinations, the processing request is notified to all the processors. This is what I did.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a multiprocessor system to which an embodiment of the present invention is applied, and FIG. 2 is an explanatory diagram showing an example of a method for connecting data to a queue in interprocessor communication.

In Figure 1, 1 is a shared memory, 6 is a high-speed bus, and 10 is a shared memory.
0 is a system controller, 101 to 104 are processors (CPUs), 110 is an I10 controller, 111
, 112 are input/output devices.

In addition, in Fig. 2 (al, (bl, (C)), 2
2a is a first communication buffer, 22b is a second communication buffer, 22c is a third communication buffer, 24a is a first queue pointer, 24b is a second queue pointer, and 24C is a third queue pointer. , 26a, 26b and 26C are mailbox management tables.

Next, the operation will be explained. In this embodiment, in order to simplify the explanation, an example in which the number of processors is limited to four will be described.

In a system in which a system controller 100, first to fourth CPUIs 01 to 104, shared memory 1, and I10 controller 11O are connected to a high-speed path 6 as shown in FIG. The inter-processor communication method between processors 104 is performed as follows. That is, the system controller 100 performs overall control in this embodiment, and controls the CPUI O1 to O1.
04, for example, input/output devices 111, 11
Load the program from 2 and send the program to the CPU
It has the function of loading to IO1-104.

Now, work A is sent to the first CPUI 01, and the second CPU
It is assumed that work B1 is given to 102, work C1 is given to third CPU 103, and work is given to fourth CPU 104.

Here, work A processes the input data from the I10 controller 110 and passes the results to work B and work C.
Assume that job C processes input data from job A and passes the results to the job, and job C processes input data from job B and job C and passes the results to the I10 controller 110.

The system controller 100 is CPUI 01 to 104
A queue of processing requests is generated in the shared memory 1 in response to a request from. The processing requesting CPU requests the system controller 100 to generate a mailbox, and each of the processing requesting CPUs requests the system controller 100 to generate a queue related to the mailbox.

Now, a request for mailbox generation is made by the first CPUI O1, second CPU 102, and third CPUI O3, which are the processing request sources, and the second CPU 102. If a request is made from the third CPU 103 and fourth CPU 104 to create a queue regarding the mailboxes, the system controller 100 causes mailboxes 26a, 26b, 26C1 corresponding to these mailboxes to be created in the shared memory l. first, second and third queue pointers 24a;
24b and 24C are generated.

The system controller 100 also has a function of transmitting and receiving processing requests (messages). That is, the system controller 100
When receiving a message transmission request from ~104, the message is stored in the communication buffer in the shared memory 1.

When a reception request is received from CPLIIO1~104, the contents of the communication buffer are taken out and sent to CPUIIO1~104.
104.

Next, actual inter-processor communication will be explained with reference to FIG.

Work A on the first CPU 101 is the I10 controller 1
Process the input data from 10 and send the result to 2nd (7)
A request is made to the system controller 100 to send a message to the CPU 102 and the third CPU IO 3. At this time, the message contains the logical addresses of the second CPUIO2 and third CPUIO3, which are the processing request destinations. Therefore, the system controller 10
0 examines the address of the system to which the process is requested and stores the message in the first communication buffer 22a of the first queue pointer 24a and the second communication buffer 22b of the second queue pointer 24b.

When the job A on the first CPU Ol receives the above-mentioned completion, it continues to receive input data from the I10 controller 110 and processes the data.

Next, when job B on the second CPUI O2 makes a message reception request to the system controller 100, the system controller 100 retrieves the message from the first communication buffer 22a of the first queue pointer 24a. It is passed to the second CPU 102. The second CPU 102 that received the message performs processing based on the message, and the result is sent to the fourth CPU 10.
4, requests the system controller 100 to send the message. Similarly, job C on the third CPU 103 issues a message reception request to the system controller 100, receives the message, performs processing based on the message, and sends the result to the fourth CPU 104.
The system controller 100 requests the system controller 100 to send the message in order to pass the message to the system controller 100. system controller 100
is the message from the second CPU 102 or the third CPU 102.
The message from the fourth CPU 103 is sent to the fourth CPU 104.
It is stored in the third communication buffer 22c of the third queue pointer 24c for passing to the upper worker.

Next, when the fourth CPU 104 requests the system controller 100 to receive a message, the system controller 100 uses the third queue pointer 24
The message is taken out from the third communication buffer 22C of CPU 104 and passed to the fourth CPU 104. The fourth CPU 104 that receives the message performs processing based on the message and sends the result to the I10 controller 110.
output to the second CPU 102 or the third CPU
Wait for a message from PU103.

At this time, the system controller 100 operates in the order shown in FIG. That is, when an interrupt from another CPU is detected (step 5T1), it is determined what type of request the interrupt is (step 5T1).
T2). As a result, if it is a transmission request from the processing request source CPU to the processing request destination CPU, the request destination address in the transmission message is checked (step 5T3), and all corresponding transmission messages are queued in a queue. (Step 5T4), and notifies the process requesting CPU of the end of the process (Step 5T5).

If the interrupt is a reception request from the processing request destination, the message is taken out from the queue and notified to the processing request destination CPU (step 5T6). system controller 100
repeats the above process.

In this way, from the first CPUI 01 to the second CPU
UI O2 and third CPU 103, second (7) CP
Fourth CPU1 from U102 and third CPU103
Communication to 04 is performed.

In the above embodiment, when specifying a plurality of processing request destinations, the processing request destination address is stored in the processing request message, but the processing request destination address is stored in the mailbox 26a. You can. The flow of processing at that time is shown in FIG. In this case, the process is the same as the above embodiment except that the address of the processing request destination is determined by checking the mailbox 26a (step 5T3a).

〔Effect of the invention〕

As explained above, in the present invention, when transmitting a message from a processor requesting processing to multiple processes at the same time, the same data can be transmitted to multiple processes by executing the message with a single transmission request. When configuring a system in which two processors perform the same processing and compare the results, the effect is that the communication efficiency between the processors is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing a multiprocessor system to which an embodiment of the inter-processor communication method according to the present invention is applied;
FIG. 2 is an explanatory diagram showing an example of a method for connecting data in inter-processor communication to a queue; FIGS. 3 and 4 are flowcharts for explaining the operation of the system in FIG. 1;
The figure is a block diagram showing a multiprocessor system to which the conventional method is applied, and FIG. 6 is an operational diagram for explaining the conventional method. ■...Shared memory, 6...High speed bus, 100...
System controller, 101-104... Processor, 111.112... Input/output device.

Claims (1)

[Claims] It includes a plurality of processors, a shared memory whose contents can be commonly referred to and updated by the plurality of processors, and a system controller that manages the plurality of processors. A plurality of communication buffers are provided for storing the contents of a processing request transmitted from a processor to a request destination processor, and a queue pointer is provided that sequentially connects the plurality of communication buffers to form a queue. In a multiprocessor system in which a request is transmitted from a request source processor to a request destination processor via a communication buffer, multiple addresses of the process request destination processors are stored in the processing request, and the same processing request is notified to multiple processors. An inter-processor communication method characterized in that the process is executed with one processing request.