JPH0467191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit for display, and more particularly to a semiconductor integrated circuit for liquid crystal display having a dot matrix structure.

An object of the present invention is to provide a semiconductor integrated circuit for liquid crystal display with a high degree of display freedom.

Another object of the invention is to provide a highly versatile semiconductor integrated circuit for liquid crystal display.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of one embodiment of the invention. In the figure, a portion surrounded by a dotted line is formed on one semiconductor substrate using a known MOS (metal-insulator-semiconductor) integrated circuit technology.

In this embodiment, although not particularly limited, a circuit for forming display signals for signal (segment) lines arranged in a matrix with respect to scanning (common) lines of a liquid crystal display device having a dot matrix structure is formed of a single semiconductor. It is composed of integrated circuits. Therefore, the timing signal for the scanning line of the liquid crystal display device is generated by another circuit.

Semiconductor integrated circuit for liquid crystal display of this example Y-
The IC is composed of the following circuit blocks.

RAM is a random access memory that holds pixel data corresponding to dots on a liquid crystal display device. In this embodiment, although not particularly limited, the RAM includes four memory arrays RAM ₁ to
The RAM is divided into ₄ parts, each of which has 8 bits in the vertical direction and 50 bits in the horizontal direction.

Therefore, 32×50 bits of pixel data can be held as a whole.

The address counter CTR1 selects an address for exchanging pixel data between a signal source such as a microprocessor and the RAM, and includes an address decoder circuit. In this address counter CTR1, 8 bits (1 byte) of memory cells are simultaneously selected by one address setting, and 8 bits of data are written/read in parallel.

Therefore, this address counter CTR1 has X address signals X ₁ to X ₄ that perform 1/4 selection in the vertical direction (selection of RAM ₁ to RAM ₄ ), and a Y address signal that performs 1/50 selection in the horizontal direction. Y ₁ to Y ₅₀ are formed. Among the address signals, address signals _Y1 to _Y50 are automatically incremented sequentially each time the 8-bit pixel data is input/output by their up or down count operation.

The flip-flop _FF1 holds the control signal U/D for the counter operation. For example, if the control signal U/D is "1", it performs an up-count operation, and if it is "0", it performs a down-count operation. It is something that can be done.

By automatically incrementing the address signal in this way, it is no longer necessary to input the address signal each time when writing pixel data. Therefore, writing operations are facilitated.

Further, each memory cell of the RAM is provided with a read-only output circuit. The output data from this output circuit is used as the above-mentioned display data.

The address counter CTR2 selects an address for reading out the pixel data for display, and serves as an address decoder circuit.
It includes a DEC and a counter circuit CUT. This address counter CTR2 generates address signals _Z1 to _Z32 that select 1/32 in the vertical direction. Therefore, with one address setting,
50-bit memory cells arranged horizontally are selected at the same time.

These 50 bits of pixel data read out at the same time are each temporarily held by the latch circuit _FF3 .

The counter circuit CUT is a 5-bit binary counter, the upper two bits of which are preset to an arbitrary starting address held by the latch circuit _FF2 .

For example, if the top two bits are “0” and “0”,
The first address is Z ₁ (RAM ₁ ), and “0” and “1”
Then, the first gaddress is Z ₉ (RAM ₂ ) and “1”
If it is “0”, the first address is Z ₁₇ (RAM ₃ ),
If it is "1" or "1", the first address is set to Z ₂₅ (RAM ₄ ).

The address decoder circuit DEC receives the output from the 5-bit binary counter CUT, and
A Z address signal corresponding to the state of this binary counter is output. For example, as mentioned above, when the state of the binary counter is "00000", the address signal
When it is " ₀₁₀₀₀ " it outputs address signal ₉ , when it is "10000" it outputs address signal Z ₁₇ , and when it is "11000" it outputs address signal Z ₂₅ . Output. Furthermore, when the binary counter is “11111”,
The above address decoder circuit DEC is an address signal
Output Z ₃₂ .

This address counter CTR2 operates in response to scanning timing signals M and FRM. As shown in FIG. 2, the timing signal M is a timing signal for selecting N scanning lines, and upon receiving this signal M, the address counter CTR2 performs a counter operation. The timing signal FRM is a frame signal, and is the first scanning line selection timing signal _M1 mentioned above.
formed in synchronization with This frame signal FRM
In response, the lower 3 bits of the counter circuit CUT are cleared and the upper 2 bits are set to the latch circuit.
The holding address of FF ₂ is preset.

For example, if "0" and "0" are set in the latch circuit _FF2 , by receiving the frame signal FRM, the upper two bits of the counter CUT are preset to "0" and "0". bottom 3
The bit is cleared. Therefore, at this time, the address counter CTR ₂ is the first address corresponding to the state "00000" set in the binary counter CUT.
Output Z ₁ .

From then on, each time the timing signal M is applied,
The above counter CUT continues to count up.
Along with this, from address counter CTR2,
Address signals that are sequentially counted up are output.

When the number of scanning lines is 32, after the address signal _Z32 is output from the address counter CTR2, the frame signal FRM is output to the counter CTR2.
Applied to CUT and latch circuit _FF2 . Therefore, after the address signal _Z32 is output from the address counter CTR2, the counter CUT is again set to the state corresponding to the first address,
Thereafter, the same operation as above is repeated.

The counter CUT is counting the timing signal M, and even after the state becomes "11111", if the timing signal M is applied without the frame signal FRM being applied, the counter CUT is , returns to the state of "00000" and continues counting the timing signal M.

Therefore, for example, when the counter circuit CUT is set to the state "10000" corresponding to the start address Z ₁₆ , the address counter CTR2 chronologically reads the address signals Z ₁₆ to Z ₁₈ in accordance with the timing signal M. Output. That is, the address counter CTR2 first sequentially outputs address signals from _Z16 to _Z32 , and then sequentially outputs address signals from _Z1 to _Z18 .

Also, as will be explained later using FIG. 5, if the number of scanning lines is set to 16, then the number of addresses after the set start address corresponding to the number of scanning lines will be After the address signal is output from address counter CTR2, the frame signal
FRM is applied to the counter CUT and the latch circuit _FF2 .

For example, when latch circuit FF ₂ is set to “0” or “1”, the start address is as described above.
Set to Z ₉ . For this reason, the address counter
The CTR 2 outputs address signals Z ₉ to Z ₂₄ in chronological order according to the timing signal M. After this, the frame signal FRM is
Applied to the counter CUT and latch circuit _FF2 . As a result, the counter CUT is again preset to a state corresponding to the first address.

When this start address is set to _Z9 as described above, the address counter CTR2 outputs address signals _Z9 to _Z24 in time series by the same operation as described above. On the other hand, if the start address is set to a different address, for example _Z17 , that is, if the latch circuit _FF2 is set to "1" or "0", the frame signal
By FRM, counter CUT is address signal
Preset to state “10000” corresponding to Z ₁₇ . Therefore, the address counter CTR2 outputs address signals _Z17 to _Z32 in time series according to the timing signal M. After this, the frame signal FRM is applied again, and the same operation as described above is repeated.

Note that when the latch circuit _FF2 is set to "1" or "1", that is, when the first address is set to _Z25 , the address counter CTR2 receives the address signal in chronological order according to the timing signal M.
Outputs Z ₂₅ to Z ₈ . That is, in this case,
Address counter CTR2 first receives an address signal.
Output sequentially from Z ₂₅ to Z ₃₂ , then address signal
Output sequentially from Z ₁ to Z ₈ .

DV ₁ to DV ₅₀ are liquid crystal driving circuits that receive pixel data from the latch circuit FF ₃ and form segment driving signals S ₁ to S ₅₀ , respectively.
These drive circuits DV ₁ to DV ₅₀ receive the four-value power supply voltages V ₁ to V ₄ , the timing signal M, and the pixel data from the latch circuit FF ₃ , for example, 1 Segment drive signals S ₁ to S ₅₀ are respectively formed by the /5 bias method.

I/O is an input/output interface, and data D,
A control signal C is sent and received. This control signal C includes a chip select (system address) signal,
It includes a read/write signal R/W to RAM, a data/command signal D/I, and a timing signal E. If the data/command signal D/I is "1", it indicates that the 8-bit data D is pixel data for display.
If it is "0", it indicates that it is an instruction code.

This instruction code allows flip-flop
The state of _FF1 , the state of latch circuit _FF2 , or the state of X address and Y address to address counter CTR1 are set. For example, the latch circuit _FF2 is set to one of the four states mentioned above according to the instruction code. Note that the Y address can also be automatically advanced as described above. Further, the control circuit CONT performs control such as starting and stopping display according to the instruction code. That is, when the control circuit CONT stops the display according to the instruction code, the control circuit CONT activates the latch circuit _FF3.
generate a signal that resets the

FIG. 3 shows a circuit diagram of an embodiment of the memory cell M-CEL constituting the RAM.

Memory cell M-CEL includes inverters IV ₁ and IV ₂
A _flip -flop _consisting of
It is composed of. The pair of input/output lines D', ' of the memory cells are shared by 50 memory cells arranged in the horizontal direction.

The above input/output lines D′,′ are transmission gates
Common data line D ₁ , through MOSFETQ _X1 , Q _X2
Connected to _D1 .

A Y address selection signal Y ₁ is applied to the gates of the transmission gate MOSFETs Q _Y1 and Q _Y2 .
This Y address selection signal _Y1 is applied to similar transmission gates of 32 memory cells arranged vertically.
Commonly applied to MOSFETs.

An X address selection signal _X1 is applied to the gates of the transmission gate MOSFETs _QX1 and _QX2 .
This X address selection signal _X1 is commonly applied to eight pairs of similar transmission gate MOSFETs arranged in the vertical direction. In other words, this X address signal
X ₁ is given to the memory array RAM ₁ divided into four. Therefore other memory arrays
RAM ₂ to RAM ₄ are similarly supplied with X address selection signals X ₂ to X ₄ , respectively.

Further, the memory cell M-CEL is provided with a read-only clocked inverter _IV3 .

The output terminal of this clocked inverter IV ₃ is
It is shared with the output terminals of the remaining 31 memory cells arranged in the vertical direction, and is used as an output line _R1 having a wired-OR configuration. Also, the above inverter IV ₃
The clock terminal of 50 memory cells arranged horizontally is shared by the Z address selection signal _Z1.
is commonly applied.

Further, the common data line D is shared between the corresponding input/output lines in the divided memory arrays RAM ₁ to RAM ₄ .

As a result, either memory array RAM _{1 to} RAM ₄ can be specified by setting the X address, and 8 memory cells in the vertical direction can be selected by setting the Y address, so 8-bit data can be exchanged. can be performed in parallel.

Also, by setting the Z address, the pixel data of 50 memory cells arranged horizontally can be transferred to the above 8
Bits can be read in parallel independently of data exchange.

FIG. 4 shows a block diagram of an embodiment of a liquid crystal display system using the semiconductor integrated circuit for liquid crystal display according to the present invention.

This embodiment shows an example in which a liquid crystal display device LCD suitable for the pixel data holding capacity of the RAM is used. Therefore, a liquid crystal display device LCD with 32 dots in the vertical direction and 50Xn dots in the horizontal direction is used.

Further, in this embodiment, other semiconductor integrated circuits X-IC ₁ and X-IC ₂ are prepared in order to form the selection timing of the 32 horizontally arranged scanning lines.

Since this semiconductor integrated circuit X-IC ₁ has the ability to drive a maximum of 20 scanning lines, in the above case of 32 scanning lines, a similar semiconductor integrated circuit X-IC ₂ is added.

This semiconductor integrated circuit X-IC ₁ forms a reference frequency signal for defining scanning timing using an external resistor and a capacitor, and forms a scanning line timing signal based on this.

When used as an expansion device like _{the above} semiconductor integrated circuit The remaining 12 scanning line selection timing signals are formed in synchronization with the frequency signal.

Moreover, this semiconductor integrated circuit X-IC ₁ (X-IC ₂ )
also forms the frame signal FRM and timing signal M based on the reference frequency signal described above.

In this embodiment, the frame signal FRM and timing signal M are applied to n semiconductor integrated circuits Y-IC from semiconductor integrated circuit X- _IC1 .

Moreover, this semiconductor integrated circuit X-IC ₁ (X-IC ₂ )
is equipped with a display duty switching function, allowing you to selectively switch between five display duties: 1/8, 1/12, 1/18, 1/24, and 1/32.

In accordance with this switching of the display duty, the timing of the frame signal FRM etc. is also switched within the semiconductor integrated circuit X- _IC1 . That is,
For example, when the display duty is set to 1/32, the frame signal FRM is set to be generated once when the timing signal M is generated 32 times. Similarly, for example, if the display duty is set to 1/16, the timing signal M
When the frame signal FRM is generated 16 times, the frame signal FRM is 1
It is set to occur twice.

As described above, in the liquid crystal display device LDC having 32 scanning lines, the display duty is set to 1/32 accordingly.

Therefore, if there are 24 or 32 scanning lines,
The scanning line selection timing signal is formed by two semiconductor integrated circuits X-IC ₁ and X-IC ₂ , and when there are 8, 12 or 16 scanning lines, one semiconductor integrated circuit IC ₁ forms the scan timing signal. Furthermore, the display duty is also set accordingly.

On the other hand, the signal lines arranged in the vertical direction of the liquid crystal display device LCD include the semiconductor integrated circuit Y-IC.
A display signal is supplied according to the pixel data formed by the pixel data. The above-mentioned semiconductor integrated circuit Y-IC has the ability to drive 50 signal lines, so that n similar semiconductor integrated circuits Y-IC ₁ to Y-IC _o can be used.
Display signals of 50×n signal lines can be formed. Furthermore, the MPU is a microprocessor that serves as a signal source. In this embodiment, the display system configured as described above uses the scanning line selection timing (1/
Corresponding to 32), since 50×n pixels are displayed, any figure can be displayed on the display screen which is composed of 32×50×n dots as a whole.

In addition, in the case of numbers and alpha bets,
If one character is composed of 5 x 7 dots, one line is 10 x
Four lines can be displayed with n characters. In addition,
One dot is used as the line spacing.

FIG. 5 shows a schematic block diagram when a 16.times.50 dot liquid crystal display device LCD is driven using the semiconductor integrated circuit of this embodiment.

In this embodiment, for an LCD with a 16×50 dot configuration, one semiconductor integrated circuit X-IC ₁ and
One semiconductor integrated circuit Y-IC ₁ is used.
Further, as in the embodiment shown in FIG. 4, the control of the Y-IC ₁ and the like is performed by the microprocessor MPU. Note that the external resistor and capacitor used for forming the reference frequency signal are omitted in this figure. In this example, the number of scanning lines is 16, so the display duty is 1/16.
is set to

Therefore, the RAM of semiconductor integrated circuit Y-IC ₁
, only 1/2 of the pixel data is used for display. However, in this embodiment, as described above, since the upper two bits of the binary counter in the address counter CTR2 can be changed freely, the start address output from the address counter CTR2 can be easily changed. For this reason,
RAM ₁ and RAM ₂ , RAM ₂ and RAM ₃ , RAM ₃ and
The pixel data of RAM ₄ and RAM ₄ and RAM ₁ can be selectively switched and displayed.

This can be achieved, for example, by the following display method.

For example, when displaying a message over two or more lines, first display the message consisting of two lines using RAM ₁ and RAM ₂ , and then:
By switching to RAM ₂ and RAM ₃ , the display lines can be sequentially moved so that the second and third lines are displayed.

By sequentially performing this display switching and updating new display data, a message spanning multiple lines can be displayed in an extremely natural manner.

Also, for the pixel data of RAM ₁ and RAM ₂ ,
By preparing pixel data in which black and white are inverted in RAM ₃ and RAM ₄ and displaying them by switching them alternately, a black and white inverted flashing display can also be performed.

Furthermore, even when drawing a moving image, by sequentially performing the above-described display switching and updating of display data, it is possible to display the moving image in a natural manner.

In this way, in the semiconductor integrated circuit Y-IC according to this embodiment, even when the storage capacity of the RAM is used for a liquid crystal with a smaller number of dots, it can be used effectively without waste, and as a result, the display The degree of freedom can be increased.

In addition, by adding such functions, even if RAM is configured in a semiconductor integrated circuit, it will not be wasted, and it can be used in various dot-structured liquid crystal display devices, increasing versatility. can be increased.

Further, when the RAM is provided with a read-only output terminal, pixel data can be changed while displaying according to the pixel data, so an easy-to-use display system and high display quality can be obtained.

Furthermore, as in this embodiment, when the display circuits for the scanning system and the signal system are each divided into a semiconductor integrated circuit, it can be applied to liquid crystal display devices with various dot configurations. It is possible to mass-produce integrated circuits, resulting in lower costs for producers and easier system changes for users.

The invention is not limited to the above embodiments.

The start address of the binary counter (Z register) may be such that all bits are preset. Also, the configuration of RAM,
And its capacity or its dividing method can be changed in various ways.

Further, the address setting for data transfer to and from the RAM may be automatically advanced sequentially in the vertical direction.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a semiconductor integrated circuit showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing an example of its timing signal, and Fig. 3 is an embodiment of a memory cell constituting a RAM. 4 is a block diagram of a display system showing one embodiment of the present invention, and FIG. 5 is a schematic block diagram of a display system according to another embodiment.

Claims (1)

[Claims] 1. RAM that holds pixel data in a dot configuration
and an addressing circuit for writing and reading pixel data in the RAM;
An internal bus for writing and reading pixel data in the RAM, and a circuit for sequentially reading out pixel column data corresponding to the scanning electrodes of a liquid crystal display device with a dot matrix configuration in synchronization with the selection timing of the pixel data in the RAM. , a start address designation circuit that divides the RAM into a plurality of memory arrays with the same number of columns and can specify the start address of the pixel column data of each memory array via the internal bus; A latch circuit that inputs and holds data in parallel, a liquid crystal drive circuit that receives pixel column data from the latch circuit in parallel and forms a liquid crystal drive signal, and starts display according to an instruction code that is input via the internal bus. Alternatively, a control circuit for controlling display stop and an input/output interface for transmitting and receiving the pixel data from the outside to the internal bus or inputting the instruction code to the internal bus are included on a single semiconductor substrate. Characteristics of semiconductor integrated circuits for liquid crystal displays. 2. The liquid crystal display semiconductor according to claim 1, wherein the head address designation circuit includes an address counter circuit, and a specific bit of the address counter circuit is preset based on an external signal. integrated circuit. 3 The RAM has a first group of selection lines and a second group of selection lines for writing and reading from the RAM, and a third group of selection lines for reading out the pixel column data in parallel, and The number of selection lines in one group is equal to the number of the memory arrays, the number of selection lines in the second group is equal to the number of bits in the pixel column read out in parallel, and the number of selection lines in the third group of each memory array is equal. 2. A semiconductor integrated circuit for liquid crystal display according to claim 1, wherein the number of lines and the bit width of said internal bus are equal. 4. Claim 1, wherein the storage capacity of the RAM is larger than the number of dots in the dot matrix liquid crystal display device.
A semiconductor integrated circuit for liquid crystal display as described in . 5. A semiconductor integrated circuit for liquid crystal display according to claims 1 to 4, a semiconductor integrated circuit that forms the timing of scanning electrodes, and a liquid crystal display device having a dot matrix structure. LCD display system. 6. A liquid crystal display device comprising a semiconductor integrated circuit for liquid crystal display according to a plurality of claims 1 to 3, a semiconductor integrated circuit that forms the timing of scanning electrodes, and a liquid crystal display device having a dot matrix structure. A liquid crystal display system, characterized in that a timing signal formed by a semiconductor integrated circuit that forms the timing of the scanning electrode is commonly input to the plurality of liquid crystal display semiconductor integrated circuits.