JPH0467197B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vibrato device for an electronic musical instrument.

Traditionally, tone generators, etc., have been used to add vibrato to the output musical sounds of electronic musical instruments.
When implemented as an LSI, this is done by changing the oscillation frequency of the clock generator that generates the master clock to operate the LSI, but this method requires a dedicated analog circuit. However, there was a problem with frequency accuracy, and improving the accuracy required an expensive circuit configuration, resulting in increased costs.

To add vibrato using another method, for example, the musical waveform is divided into multiple steps and stored, and when the stored waveform data is read out, only specific steps are lengthened or shortened to change the frequency. However, there was a problem that a good vibrato effect with a smooth frequency change was not applied, and in particular, the vibrato was not applied equally to all scales.

This invention was made in view of the above circumstances, and its purpose is to provide a good vibrato with smooth frequency changes when reading out a musical sound waveform that has been divided into multiple steps and stored, and to provide a good vibrato for each musical scale. To provide a vibrato device for an electronic musical instrument capable of imparting a uniform vibrato to a musical instrument.

In order to achieve the above object, the present invention comprises a first memory means for storing frequency information for determining a clock generation time width, and a second memory means for storing a music waveform consisting of waveform data of a predetermined number of steps. and a clock generating means that repeats the operation of generating a clock when the data obtained by receiving the frequency information from the first memory means and executing a predetermined calculation reaches a predetermined value, and from this clock generating means. waveform reading means for sequentially reading waveform data for one step from the second memory means every time a clock is generated; and a detection unit for detecting that the waveform reading means has read the waveform data for a desired step from the second memory means. a change control means for periodically varying the number of desired steps detected by the detection means; The present invention is characterized by comprising: changing means for changing the frequency information from the first memory means calculated by the generating means based on the frequency information obtained by shifting this frequency information.

The present invention will be described in detail below based on an embodiment shown in the drawings.

FIG. 1 shows a block circuit, in which reference numeral 1 denotes a frequency information generator. For example, a key operation on a keyboard is detected by a CPU, and a key code corresponding to the key operation is given. Then, frequency information corresponding to that key code is output. That is, this frequency information generating device 1 consists of a ROM, and frequency information corresponding to each musical scale is stored. Note that this frequency information is a value given by the fundamental frequency of calculation divided by (scale frequency x number of waveform steps constituting one period (in this embodiment, "8")).

The frequency information output from this frequency information generator 1 is given to a scale clock generator 2. As will be described in detail later, this scale clock generator 2 uses the frequency information as a set value, repeatedly performs a predetermined calculation on this set value, and when the value satisfies a predetermined condition, reads out a waveform. Outputs the clock for

Furthermore, the scale clock generator 2 is supplied with the output of an AND gate 3. This AND gate 3 outputs an AND condition signal of the vibrato switch SW output and the output of the vibrato addition address designation circuit 4.

The vibrato counter 5 is an octal counter as will be described later, and the step speed of this counter 5 determines the vibrato period.

The output of the vibrato counter 5 is input to the vibrato addition address designation circuit 4. Further, the vibrato addition address designating circuit 4 is supplied with the output of the waveform address counter 6, that is, a signal designating a waveform step address. As a result, the vibrato addition address designation circuit 4 comes to designate a step with a time different from the original step length, and when the waveform address counter 6 specifies just such a step, the vibrato addition address designation circuit 4 The output of is "1".

The waveform address counter 6 receives the read clock output from the scale clock generator 2.
Its contents are incremented, and it consists of a 3-bit counter. The output of this waveform address counter 6 is then supplied to a waveform memory 7. In this waveform memory 7, the waveform of a musical tone is divided into eight steps (steps "0" to "7") and digitally stored.

The musical waveform signal output from the waveform memory 7 is amplitude-modulated by, for example, an envelope signal output from an envelope signal generator (not shown), and then converted into an analog signal by a D/A converter and then emitted. Ru.

Next, the scale clock generator 2 will be explained in detail with reference to FIG. The frequency unit output from the frequency information generator 1 is expressed in 10 bits, and is latched by a latch 8. The read clock φA of this latch 8 is given from the CPU. The 10-bit output of latch 8 is applied to input terminals A ₀ -A ₉ of full adder 10 of 10-bit capacity via OR gates 9-1 - 9-10. The signals output from the S ₀ to _{S 9} output terminals of the full adder 10 are read into the latch 11 using the clock φ _CLK . This clock φ _CLK is the basic clock of this embodiment.

The output of this latch 11 is then judged by a NOR gate 12 as to whether all bits are "0" or not. If all bits are "0", it is supplied to the waveform address counter 6 as a read clock.

Further, the output of this NOR gate 12 is transmitted via an inverter 13 to transfer gates Tγ-1 to
It is supplied to Tγ-4 and functions as its gate signal. Furthermore, the output of the inverter 13 is commonly supplied to OR gates 9-1 to 9-10. Therefore, when the read clock is not generated from the NOR gate 12, the input terminal of the full adder 10
_A0 to _A9 have all “1” data, that is, “-1”
The value of will be supplied.

The output of the latch 11 is applied to the B ₀ -B ₉ input terminals of the full adder 10. The four least significant bits are applied to the _B0 to _B3 input terminals via the transfer gates T.gamma.-1 to T.gamma.-4. Furthermore, the outputs of the four bits below the most significant bit of the latch 8 are input to the B ₀ to B ₃ input terminals via AND gates 14-1 to 14-4.
Furthermore, it is supplied via transfer gates Tγ-5 to Tγ-8. Furthermore, this AND gate 14-1
. . . 14-4 are supplied with the output of the AND gate 3, and the transfer gates Tγ-5 to Tγ-8 are supplied with the output of the NOR gate 12.

Therefore, when the read clock is output from the NOR gate 12, the transfer gate Tγ-
Since AND gates 14-1 to 14-4 are open, the upper 4 bits of frequency information from latch 8 are shifted to the B input terminal of the full adder. i.e. "2 ^-6 "
The supply will be doubled.

Furthermore, when the AND gates 14-1 to 14-4 are not opened, that is, when the vibrato switch SW is in the off state, or even when the vibrato switch SW is in the on state, the output of the vibrato addition address designation circuit 4 is In the case of “0”, all “0” data is applied to the B input terminal of the full adder 10.

Next, the configurations of the vibrato addition addressing circuit 4 and the vibrato counter 5 will be described in detail with reference to FIG.

A 3-bit count output is obtained from the vibrato counter 5, and the clock φv determines the rate of change, and this clock φv is
It has a frequency eight times the vibrato frequency (for example, about 7Hz). Then, the 3-bit latch 15 performs a read operation by this clock φv. Of the outputs of the 3-bit latch 15, the least significant bit LSB becomes its own input via the inverter 16, and is also input to one input of the exclusive OR gate 17 that supplies the second bit input signal. This further becomes one input of the AND gate 18. The output of the second bit of the latch 15 becomes the other input of the exclusive OR gate 17 and the other input of the AND gate 18. And this AND gate 18
The output becomes the input to the exclusive OR gate 19. Furthermore, the most significant bit of the latch 15
MSB is the above exclusive or gate 19
, and its output becomes its own input.

In this way, the contents of this 3-bit latch 15 are changed to "000", "000",
"001", "010", "011", "100", "101", "110"
”,
It changes as "111", "000", etc. The output thereof is then supplied to inverters 20 to 22 of the vibrato addition addressing circuit 4.

This vibrato addition addressing circuit 4 includes:
Furthermore, the 3-bit output of the waveform address counter 6 mentioned above is provided. This 3-bit output specifies the address of the waveform from "000" to "111".

Then, this 3-bit output is sent to the inverter 2.
3 to 25. The outputs of the inverters 23 to 25 and the inverters 20 to 22
The output of is supplied to the Noah matrix circuit 26,
The output of this NOR matrix circuit 26 is supplied to the AND gate 3 via an inverter 27.

That is, this Noah matrix circuit 26 includes three vertical lines, of which the output of line _l1 is 3.
The most significant bit MSB of bit latch 15 is “1”
In this case, the output of the waveform address counter 6 is "001",
Data “0” only when “011”, “101”, “111”
Output. Therefore, the output of inverter 27 becomes "1". Similarly, when the _second bit of the 3-bit latch 15 is "1", the output of the line l2 is "0" when the output of the waveform address counter 6 is "010" or "110"; As a result, the output of the inverter 27 becomes "1" only in that case.
Furthermore, when the least significant bit LSB of the output of the 3-bit latch 15 is "1", "0" is output only when the output of the waveform address counter 6 is "000", and as a result, the output of the inverter 27 is Only in that case, it becomes "1".

Next, the operation of this embodiment will be explained.

When the frequency information based on the key code is output from the frequency information generator 1, it is read into the latch 8 in the scale clock generator 2. From then on, according to the frequency information set in this latch 8,
A clock for reading out the waveform in waveform memory 7 is generated. As mentioned above, the waveform memory 7 has
A predetermined waveform is divided into eight steps and stored. FIG. 4 shows one such example.

When the vibrato switch SW is off, the waveform information of each step is read out so that the time width of each step is uniform or approximately uniform in relation to scale accuracy.

That is, since the vibrato switch SW is off, the AND gates 14-1 to 14- in FIG.
4 is always a "0" output. Therefore, when the NOR gate 12 outputs a read clock to the waveform address counter 6, the output of the latch 8 is supplied to the input terminal of the full adder 10A. On the other hand, all "0" data is supplied to the B input terminal of the full adder 10. Then, the addition result output is read into the latch 11 whose read operation is performed by the clock φ _CLK .

Since the output is not all "0", the output of the NOR gate 12 is "0", and therefore the output of the inverter 13 is "1". As a result, the output of the latch 11 is applied to the B input terminal of the full adder 10, and at the same time, the outputs of the OR gates 9-1 to 9-10 are applied to the A input terminal of the inverter 13.
Since the output of 1 becomes all "1", all "1" data is provided.

Therefore, the full adder 10 performs an operation of adding all "1"s to the output of the latch 11, in other words, performs a "-1" operation, and applies the result to the latch 11 again.
Output to 1. Similarly, "-1" operation is performed on the output of latch 11, and the operation result is re-inputted to latch 11 several times, and as a result, NOR gate 12 outputs "1". Then, instead of calculating "-1", the frequency information of the latch 8 is preset to the full adder 10.

In this way, subtraction is repeated a number of times equal to the frequency information, and the read clock outputted as a result is supplied to the waveform address counter 6, and its contents are incremented by "+1".

Therefore, the waveform information of each step is sequentially outputted from the waveform memory at a period corresponding to the designated scale.

Next, the operation when the vibrato switch SW is turned on will be explained. That is, when the vibrato switch SW is turned on, the output of the vibrato addition address designation circuit 4 is passed through the AND gate 3 to the AND gate 1 in the scale clock generator 2.
4-1 to 14-4.

As a result, if the output of the vibrato addition address designation circuit 4 is "0", the scale clock generator 2 performs exactly the same operation as when no vibrato is applied, but if the output of the vibrato addition address designation circuit 4 is When it becomes "1", the frequency information input to the full adder 10 at the time the readout clock is output is _{N +} 2 ^{- 6} _N , that is, (1
+2 ^-6 ) _N is the changed frequency information.

That is, the frequency information of the latch 8 is applied to the A input terminal of the full adder 10, and at the same time, the AND gate 14 is applied to the B ₃ to B ₀ input terminals of the B input terminals.
-1 to 14-4 and transagate Tγ-5 to
The frequency information is shifted by 6 bits and applied via Tγ-8.

Therefore, the full adder 10 adds this input data and supplies it to the latch 11. The subsequent processing is exactly the same as described above, and the full adder 10 repeats the "-1" operation until the value becomes all "0".

Therefore, the time width of the read clock obtained this time is 1+ ^2-6 times longer. Therefore, the frequency becomes lower than when no vibrato is added.

By the way, vibrato addition addressing circuit 4
, the time-varying signal is passed through AND gate 1
4-1 to 14-4. That is, only at a specific step address among the waveform addresses output by the waveform address counter 6, the output of the vibrato counter 5 shown in FIG.
A "1" signal is output from the vibrato addition address designation circuit 4. FIG. 5 shows this relationship. For example, when the contents of the vibrato counter 5 are all "0", the vibrato addition address designation circuit 4 outputs a "1" signal at any waveform address. Therefore, the waveform of the frequency corresponding to the frequency information given from the frequency information generator 1 is accessed from the waveform memory 7. However, when the output of the vibrato counter 5 becomes "001", the vibrato addition address designation circuit 4 outputs a "1" signal when the waveform address is "0", and only when the waveform address is "0", the signal "1" is outputted.
The waveform is accessed over a longer time span than in other steps. Thereafter, when the contents of the vibrato counter 5 change sequentially, there will be 2 to 7 steps having a longer time width than the original time width. Therefore, the vibrato counter 5
As the content of the waveform changes sequentially, the frequency of the waveform gradually decreases. In this way, frequency modulation is applied to the finally obtained musical tone according to the contents of the vibrato counter 5.

Although the above embodiment has been explained for a monophonic electronic musical instrument, it can be implemented similarly for a polyphonic electronic musical instrument, and in that case, the latch 8,
For example, 11 may be a shift register to perform time-division processing of a plurality of channels.

Further, in the above embodiment, the vibrato counter 5
According to the output of Modified frequency information is obtained by subtracting the frequency information obtained by shifting, or selectively adding and subtracting, for example, according to the output of the vibrato counter 5, and a waveform readout clock is generated in accordance with this modified frequency. You can also do it. In that case, the musical tone obtained based on the changed frequency information will have a higher, lower, or higher frequency than the musical tone obtained based on the original frequency information.

Furthermore, in the above embodiment, the vibrato counter 5
Although the steps for generating the waveform readout clock with the changing frequency are gradually increased depending on the contents of
The frequency changes more smoothly into a triangular or sine wave pattern.

As described in detail above, according to the present invention, when a musical tone is generated by sequentially reading out a musical waveform divided into a plurality of steps for each waveform step based on a clock corresponding to a musical scale, the clock generation interval can be set as desired. Since the configuration is such that when a waveform step is read out, it is changed in accordance with the scale at that time, so that a uniform vibrato can be added to the original frequency of any scale.

Furthermore, according to the present invention, vibrato is added by temporally changing the number of steps for obtaining a waveform readout clock based on the changed frequency information, so the frequency of the musical tone changes smoothly, resulting in an optimal sound. It becomes possible to obtain a vibrato effect.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; FIG. 1 is a block circuit diagram, FIG. 2 is a detailed diagram of the scale clock generator of FIG. 1, and FIG. 3 is a vibrato addition addressing circuit of FIG. 1. and a detailed diagram of the vibrato counter, FIG. 4 is an explanatory diagram of waveform information stored in the waveform memory, and FIG. 5 is an explanation of changes in the signal output from the vibrato addition addressing circuit based on the output of the vibrato counter and the waveform address. This is a diagram for DESCRIPTION OF SYMBOLS 1... Frequency information generator, 2... Scale clock generation circuit, 4... Vibrato addition address designation circuit, 5... Vibrato counter, 7... Waveform memory, 9-1 to 9-10... OR gate, 10...
...Full Adder, 12...Noah Gate, 14-1~
14-4...and gate, 15...latch, 2
6...Noah matrix circuit, Tγ-1 to Tγ-8...
...transfer gate.

Claims (1)

[Scope of Claims] 1. A first memory means for storing frequency information for determining a clock generation time width; a second memory means for storing a musical sound waveform consisting of waveform data of a predetermined number of steps; A clock generating means that repeats an operation of generating a clock when data obtained by receiving frequency information from the memory means and executing a predetermined calculation reaches a predetermined value, and each time the clock is generated from the clock generating means. a waveform reading means for sequentially reading waveform data for one step from the second memory means; a detection means for detecting that the waveform reading means has read out waveform data for a desired step from the second memory means; detection control means for periodically varying the number of desired steps detected by the means; and a detection control means for periodically varying the number of desired steps detected by the means; A vibrato device for an electronic musical instrument, comprising: changing means for changing frequency information from the first memory means based on frequency information obtained by shifting this frequency information.