JPS6120877B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument in which musical waveform signals are stored in advance over a fairly large number of cycles. Conventional electronic musical instruments equipped with musical sound waveform memory usually store in advance the minimum unit of repetition of musical sound waveforms (for example, one cycle), and obtain continuous musical sound waveform signals by repeatedly reading this. .
Therefore, the shape of the musical sound waveform obtained is the same from the beginning of the sound to the end of the sound, and as it is, it lacks interest. The waveform shape of the musical sounds generated by natural musical instruments is not always constant, but changes over time from the time the sound is produced until the time it is silenced. In particular, the change is remarkable at the rise (beginning) of the sound. In conventional electronic musical instruments, in order to imitate the timbre of such natural instrument sounds, the characteristics of the timbre filter are changed over time, or the amplitude envelope of each harmonic component that makes up the musical tone is individually and independently adjusted. However, there are drawbacks such as the manner in which the timbre (i.e., musical waveform shape) changes over time is monotonous and lacks complexity, and control is complex and troublesome. Ta. This invention was made in view of the above-mentioned points,
It is an object of the present invention to provide an electronic musical instrument in which musical sound waveforms are stored in advance in a memory over a large number of cycles, and the stored musical sound waveforms are sequentially read out over time. Since musical sound waveforms are stored over a large number of cycles, it is possible to reliably imitate musical sounds whose waveform shapes change in a complex manner over time. By the way, even if musical sound waveforms are stored in memory over many cycles, the number of storage addresses in memory is finite, so in any case, the entire sound generation time from the start of sound generation to the end of sound can be covered by the musical sound waveforms stored in memory. There is no guarantee that it will be possible. This is because, when generating a sustained tone type musical tone that continues to be produced while a key is pressed, the sound generation time varies depending on the length of the key depression time. Therefore, in the present invention, if the musical tone waveforms stored in the memory are read out and the sound continues to be produced, the stored musical tone waveforms of that period are repeatedly read out. Hereinafter, the present invention will be explained in detail based on the embodiments shown in the accompanying drawings. The electronic musical instrument shown in FIG. 1 is capable of simultaneously producing a plurality of sounds based on the sound generation assignment in the sound generation assignment circuit 11. The pronunciation assignment circuit 11 is
It detects the key being pressed on the keyboard 10 and assigns the sound of that key to one of the number of sound channels corresponding to the maximum number of simultaneous polyphony (for example, 12). It can be configured according to a known allocation circuit called "SetSer". In the sound generation allocation circuit 11, each sound generation channel is distinguished by a time-division time slot, and each time slot is formed based on a clock pulse φ. Assuming that the period of the clock pulse φ is 1 μs, time slots corresponding to each sound generation channel are formed at intervals of 1 μs, and if the number of channels is 12, the repeating period of the time slots of the same channel is 12 μs. The sound generation assignment circuit 11 generates a signal (octave code B ₁ to _{B 3 )} that identifies the key assigned to each channel.
and note codes N ₁ to N ₄ ) and a key-on signal KON indicating that the key is being pressed are output in a time-division manner in the time slot of the channel. Octave codes B ₁ to _{B 3} represent an octave range, and note codes N ₁ to _{N 4} represent note names (C to B) within one octave. key on signal
KON is “1” when the key is pressed and “0” when the key is released.
becomes. The sound generation allocation circuit 11 also generates a reference pulse _SY1 representing the reference timing of the time-division time slots of each channel. This reference pulse _SY1 occurs, for example, in synchronization with the time slot of the first channel, and by looking at the timing of generation of this reference pulse _SY1 , the correspondence relationship between each time slot and channel can be determined. In the electronic musical instrument shown in FIG. 1, tone generator section 1 corresponds to each sound generation channel #1 to #12.
2-1 to 12-12 are provided in parallel. Individual tone generator sections 12-1 to 1
Reference numeral 2-12 denotes a single tone generation type tone generator, which generates only the tone assigned to its own channel. Each tone generator section 12-1
12-12 have the same configuration, and only one tone generator section 12-x corresponding to an arbitrary channel #x among them is shown in detail. The octave codes B ₁ to B ₂ and note codes N ₁ to _{N 4} and key-on signal KON of the sounds assigned to each channel, which are output in a time-divisional manner from the sound generation assignment circuit 11, are output from each tone generator section 12-1 to 12. -12, respectively, and distributed to tone generator sections 12-1 to 12-12 corresponding to the channel based on the reference pulse _SY1 . That is, the tone generator section 12-x
, latch circuits 14, 15, and 16 are provided corresponding to octave codes B ₁ to B ₃ , note codes N ₁ to _{N 4} , and key-on signal KON, respectively. Octave codes B1 to _B3 and note codes _N1 to _B3 sent from the sound generation assignment circuit 11
N ₄ , key-on signal KON is applied to the latch circuit 14, 1
5.16. This latch circuit 14,1
The reference pulse SY ₁ is used as a signal to control the timing at which input data is taken in by the input signals 5 and 16. Each tone generator section 12-1 to 12-
12 is a shift means (12-x
A delay flip-flop 17) is provided, through which the reference pulse _SY1 is sequentially shifted corresponding to the time slot of each channel. The tone generator section 12-x uses the pulse SYx shifted to the time slot corresponding to channel #x as a strobe pulse for each latch circuit 14, 15, 16 as a result of the above shift. Therefore, the octave codes B ₁ to B ₃ , the note codes N 1 to N 4 , and the note codes N ₁ to _{N 4} of the key assigned to channel #x,
and key-on signal KON to each latch circuit 14, 1
5 and 16, respectively, and output as a continuous signal (not time-divided). The note codes _N1 to _N4 latched in the latch circuit 15 are added to the selection control input of the note select circuit 18, and are used to select a divided signal of a frequency corresponding to the note name of the pressed key. The octave codes B ₁ -B ₃ latched in the latch circuit 14 are applied to the octave selection control input of the octave selection and address generation circuit 19. The octave select and address generation circuit 19 inputs the frequency-divided signal selected by the note select circuit 18, processes this frequency-divided signal according to the octave range represented by the octave codes _B1 to _B3 , and outputs the processed frequency-divided signal. Address signal for reading continuous tone waveform memory 20 based on the signal
Generate ADRS. The frequency-divided signal selected by the note select circuit 18 is generated from the superimposed frequency-divided signal generator 13. The superimposed frequency-divided signal generating section 13 includes superimposed frequency-divided signal generating circuits 13C having the configuration shown in FIG. 2, respectively, corresponding to each of the 12 note names C to B within one octave. The circuit 13C in FIG. 2 is a circuit for generating, for example, a C-tone superimposed frequency-divided signal. The oscillator 21 is
A clock pulse P having a considerably high frequency corresponding to the frequency of the C sound (however, the period of φ<<the period of P) is oscillated. This clock pulse P is applied to the count input of, for example, a 20-bit binary counter 22 and is counted there. The count outputs Q ₁ to _{Q 20} of each bit of the counter 22 are supplied to a serialization circuit 23. The outputs Q ₁ to _{Q 20} are frequency-divided signals of the clock pulse P, Q ₁ repeats "1" and "0" at a frequency of 1/2 of the clock pulse P, and Q ₂ is a frequency of 1/4, ......Q ₂₀
is repeated at a frequency of 1/2 ²⁰ . The binary weight value is
If Q ₁ is 1, then Q ₂ is 2 ¹ , Q ₂₀ is 2 ¹⁹ . The serialization circuit 23 is, for example, a serial shift register whose shift is controlled by a clock pulse φ, and a signal obtained by shaping the pulse width of a clock pulse P corresponding to the pitch name frequency into one period of the clock pulse φ by a differentiating circuit 24 (the frequency is (same as P) is used as the load command. When a load command is given from the delay flip-flop 24, the pulse signal P' synchronized with the clock pulse P given via the delay flip-flop 24 and the outputs Q ₁ to _{Q 20} of the counter 22 are sent to the serialization circuit 23 in parallel. Then, according to the clock pulse φ, P,
Q ₁ , Q ₂ , Q ₃ , Q ₂₀ are output in series in this order. In this way, the divided signal Q ₁ corresponding to the pitch name frequency
~ _Q20 are superimposed in series with pulse signal P' at the beginning. The superimposed frequency-divided signals P', Q ₁ -Q ₂₀ are generated once every cycle of the clock pulse P. Table 1 shows the data contents of the superimposed frequency-divided signals _Q1 to _Q20 .
The numbers 1, 2, 3, . . . on the right side of Table 1 represent the frequency of the clock pulse P.

【table】

[Table] The note select circuit 18 selects the note codes N ₁ to N from among the 12 types of superimposed frequency divided signals (corresponding to note names C to B) generated from the superimposed frequency divided signal generator 13 as described above. A single superimposed frequency-divided signal (P′, Q ₁ to _{Q 20} ) corresponding to the note name content of No. ₄ is selected. Octave select and address generation circuit 19
_is configured as shown in _FIG . ₁ is entered. The 21 stage/1 bit serial input/parallel output type shift register 25 sequentially performs a serial shift operation from the first stage _S1 to the final stage _S21 . Therefore, the pulse signal
The superimposed frequency-divided signals, which were serialized in the order of Q ₁ to Q ₂₀ with P' at the beginning, are parallelized in this shift register 25. The signal obtained by inverting the output of the first stage S1 of the shift register ₂₅ by the inverter 26 and the second stage
The outputs of the 21st stage S ₂ to S ₂₁ are input to the NOR circuit 27. This NOR circuit 27 is for detecting the pulse signal P' (that is, for detecting the arrival of the superimposed frequency-divided signal with P' at the beginning). Further, the outputs of the first stage S ₁ to the 20th stage S ₂₀ of the shift register 25 are input to the latch circuit 28 . The timing for reading parallel data from S ₁ to S ₂₀ into this latch circuit 28 is determined by the AND circuit 2.
commanded by a signal from 9. The arrival of the clock pulse signal P', that is, the arrival of the superimposed frequency-divided signals _Q1 to _Q20 , is detected as follows. Since the frequency-divided signals Q ₁ to _{Q 20} are always sent after the pulse signal P', the signals do not appear (they are "0") for at least 20 bit times immediately before the pulse signal P' appears. . Therefore, when the pulse signal P' is read into the first stage _S1 of the shift register 25, the outputs of the second stage _S2 to the 21st stage _S20 , which represent the signal state of the previous 20 bit times, are all "0". It is. Therefore, the shift register 25
When the pulse signal P' is read into the first stage S1 of the inverter ₂₆ , the outputs of the stages _S2 to _S21 are all "0" and the output of the stage _S1 is also "1".
Since the signal is inverted at , the condition of the NOR circuit 27 is satisfied. In this way, in response to the arrival of the pulse signal P', the output of the NOR circuit 27 becomes "1", and this
It is added to the set input S of the flip-flop 30,
Set state. The set output Q of the flip-flop 30 is applied to the AND circuit 29 after being delayed by one clock pulse φ in the delay flip-flop 31. The output of the final stage _S21 of the shift register 25 is added to the other input of the AND circuit 29 and the reset input R of the R-S flip-flop 30. Since the pulse signal P' precedes the frequency-divided signals Q ₁ to _{Q 20} , when this pulse signal P' arrives at the stage S ₂₁ , the first reset signal is sent to the flip-flop 30 .
supplied to At the same time, the condition of the AND circuit 29 is satisfied, and the output "1" of the AND circuit 29 is applied to the load command input of the latch circuit 28. When flip-flop 30 is reset, the output of delay flip-flop 31 becomes "0" one clock later, and even if "1" is generated from stage _S21 thereafter, AND circuit 29 does not operate. Therefore, the latch circuit 28 accurately latches the divided signals Q ₁ to Q ₂₀ that are present in the stages S ₁ to S ₂₀ when the pulse signal P' arrives at the stage S ₂₁ . Thus, the superimposed frequency divided signals Q ₁ -Q ₂₀ are parallelized and output from the latch circuit 28 as a continuous signal. Since the contents Q ₁ to _{Q 20} of this latch circuit 28 are rewritten every cycle of the clock pulse P,
Binary signals Q ₁ to _{Q 20} are output from the latch circuit 28 in exactly the same state as the output of the counter 22 (FIG. 2). The outputs Q ₁ to Q 20 of the latch circuit 28 are applied to the binary value shift circuit 32, and the outputs Q 1 to _{Q 20} of the latch circuit 28 are applied to the binary value shift circuit 32 and output from the latch circuit 14 (first
The binary bit position is shifted to the left or right according to the octave range represented by the octave codes B ₁ to _{B 3} supplied from the address signal
Output as ADRS. Address signal ADRS
is configured, for example, as 16-bit data A ₁ to A ₁₆ . Table 2 shows an example of the contents of shifts in the binary value shift circuit 32 according to each octave range.

[Table] As is clear from Table 2, the divided signals Q ₁ to _{Q 16} selected as the address signals A ₁ to A ₁₆
The repetition frequency of numerical changes as 16-bit binary values from Q ₅ to _{Q 20} becomes twice, four times, eight times, etc. as the octave range becomes higher, and satisfies the octave relationship. Lower 4 bits of address signal ADRS A ₁ ~
_A4 is applied to the interpolation circuit 33 as an interpolation address signal. The upper seven bits _A5 to _A11 are added to the continuous tone waveform memory 20 as a signal specifying each sample point address within one period of the tone waveform signal.
Further, the higher five bits _A12 to _A16 are added to the continuous tone waveform memory 20 as a signal specifying which waveform in the continuous tone waveform should be read out. However, signals _A12 to _A16 are connected to the final waveform hold circuit 34.
Normally, it passes through this hold circuit 34 as is, and is held in this hold circuit 34 only when the final waveform is repeatedly read out, as will be described later. The continuous tone waveform memory 20 continuously stores tone waveforms spanning quite a large number of cycles from the beginning of the sound. In this example, a 32-cycle waveform is converted into 12-bit binary address signals _A5 to _A16 . Correspondingly 2 ¹² =
It is divided into 4096 sample points and stored. In other words, one period waveform consisting of 2 ⁷ = 128 sample points corresponding to the lower 7 bits of address signals A ₅ to A ₁₁ is
2.sup.5 =32 address signals _A.sub.12 to A.sub.16 are successively stored corresponding to the upper five bits of address signals ^A12 to _A16 . This 32-cycle continuous musical sound waveform accurately imitates a musical tone signal of a desired tone over 32 cycles from the beginning of the sound, and the waveform shape of each cycle is appropriately different. This continuous tone waveform memory 20 has a configuration that reads out an analog waveform amplitude value voltage in response to a digital address input, or a configuration that converts the read digital waveform amplitude value into _an analog voltage. Not only the waveform amplitude value voltage _V1 of the sample point corresponding to the value of _A16 but also the waveform amplitude voltage _V2 of the next sample point is read out at the same time. This is because the interpolation circuit 33 interpolates the waveform amplitude values between adjacent sample points to improve the waveform resolution. The interpolation circuit 33 is configured as shown in FIG. 4, for example. The interpolation function memory 35 consists of a resistive voltage divider circuit that stores a predetermined interpolation function (for example, one part of a cosine wave) at 16 sample points, and the memory 35 has a resistor voltage divider circuit that stores a predetermined interpolation function (for example, one part of a cosine wave) at 16 sample points, and the memory 35 has a resistor voltage divider circuit that stores a predetermined interpolation function (for example, one part of a cosine wave) at 16 sample points. Waveform amplitude voltages V ₁ and V ₂ are applied,
The difference between both voltages V ₁ and V ₂ is divided into 16. The output of each voltage division point is connected to each analog gate of the analog gate section 36, and the output sides of these analog gate sections 36 are commonly connected. The lower four bits A ₁ to _{A 4} of the address signal ADRS are applied to a decoder 37, and the decoded outputs thereof corresponding to decimal values 0 to 15 are applied to gate control inputs of individual analog gates of the analog gate section 36. While the decode output changes sequentially from 0 to 15, each division point output is gated in order from the voltage division point closest to the preceding sample point voltage V ₁ to the next sample point voltage V ₂ . It's getting old. The musical tone signal MV taken out to the output side of the analog gate section 36 is supplied to an opening/closing circuit 38. The switching circuit 38 is configured as shown in FIG. 5, for example. The key-on signal KON, which is continuously output from the latch circuit 16 (FIG. 1) in response to the key press, is applied to the gate control input of the analog gate 39, and continuously conducts the gate 39 while the key is being pressed. and supplies a voltage +V to the capacitor 40 and the gate control input of the analog gate 41. Therefore, while the key is being pressed, the analog gate 41 is conductive, and the musical tone signal MV supplied from the analog gate section 36 of the interpolation circuit 33 passes through the analog gate 41 and is output from the opening/closing circuit 38. When the key is released, the key-on signal KON becomes "0" and the analog gate 39 becomes non-conductive. As a result, the charge on the capacitor 40 is transferred to the resistor 4.
2, and the analog gate 41 is gate-controlled by the discharge waveform. Therefore, the amplitude envelope of the musical tone signal MV input to the analog gate 41 is controlled by the discharge waveform, and the attenuation envelope is controlled, so that the amplitude is gradually attenuated and the sound is silenced. It should be noted that the continuous tone waveform memory 20 stores the tone waveform signal itself that is actually produced over a considerable period of time from the beginning of the sound.
Naturally, the waveform including the attack envelope at the beginning of the sound is stored. Therefore, it is not necessary to specifically provide an attack envelope to the switching circuit 38. However, if necessary,
A small resistor may be placed in series with analog gate 39 and capacitor 40 to further provide an attack envelope. The musical tone signals output from the opening/closing circuit 38 are mixed with those of other channels (#1 to #12), and then are outputted via the sound system 43. Details of the final waveform hold circuit 34 are shown in FIG. The address signals A ₁₂ to A ₁₆ are respectively applied to five OR circuits 44 and supplied to the continuous tone waveform memory 20 via the OR circuits 44 . Therefore, normally, the address signals A ₁₂ -A ₁₆ simply pass through the hold circuit 34. While the amplitude voltage at each sample point of the final (32nd) one-cycle waveform of the continuous tone waveform stored in the continuous tone waveform memory 20 is being read, the address signal is
The values of A ₁₂ to _{A 16} are “11111” representing the final waveform. The 5-input type AND circuit 45 inputting the address signals _A12 to _A16 outputs a signal "1" when the value representing the final waveform is "11111", and the R
-S flip-flop 46 is set. The set output Q of this flip-flop 46 is input to all five OR circuits 44. Therefore, even if reading of one cycle of the final waveform is completed and the values of the address signals A ₁₂ to _{A 16} become all "0", the set output Q held in the flip-flop 46 causes the output from the OR circuit 44 to be output. An all-1 address signal specifying the final waveform is output and readable. Therefore, if the key is still pressed even after reaching the final waveform, the amplitude voltage at each sample point in one cycle of the final waveform is read out repeatedly according to the address signals _A5 to _A11 , and the final waveform is repeated. Occur. Then, when the key is released, a damping envelope is applied by the opening/closing circuit 38 as described above to muffle the sound. Of course, if the key is released before the final waveform is reached, a damping envelope is applied at that stage and the sound is muted. The key-on signal KON output from the latch circuit 16 is applied to a differentiation circuit 47, and one differentiation pulse is generated at the rising edge of the key-on signal KON. The R-S flip-flop 46 is reset by this differential pulse. Therefore, the flip-flop 46 is reset just before producing the sound. The embodiment shown in FIG. 1 is an example in which the present invention is applied to an electronic musical instrument configured to read out a musical waveform memory using a frequency-divided signal corresponding to the note name of a pressed key as an address signal. Of course, this invention can be applied to. For example, even in an electronic musical instrument configured to repeatedly accumulate a constant proportional to the frequency of a musical tone to be generated and read out the musical waveform memory using the accumulated result as an address signal, the continuous musical waveform memory 20 described in the above embodiment, A circuit similar to the final waveform hold circuit 34, the switching circuit 38 that applies only an attenuation envelope, or even the interpolation circuit 33 can be applied.
Alternatively, the present invention can also be applied to an electronic musical instrument in which a shift register or ring counter is driven by a clock pulse corresponding to a musical tone frequency, and sequential pulses output from each stage of the shift register or ring counter are used as an address signal. In this case, the final waveform hold circuit is configured to circulate the final stage output of the shift register or ring counter to a plurality of address stages corresponding to the final waveform. Further, it is also possible to use one continuous tone waveform memory 20 and share this memory among the respective sound generation channels in a time-division manner. Furthermore, the interpolation circuit 33 is not necessarily required. However, if the interpolation method is used, the capacity of the continuous tone waveform memory 20 can be reduced, so when a large number of tone waveforms are stored continuously as in the present invention, it is advantageous in terms of reducing the memory capacity. In the above embodiment, the continuous tone waveform memory 20 has 32
Although periodic waveforms are stored, the number is not limited to this number. Further, in the embodiment, the final waveform is held as the final one-cycle waveform, but a plurality of waveforms may be held as the final waveform and read out repeatedly. In addition, tone generator sections 12-1 to 12-1
Instead of providing a plurality of 2 channels in parallel, only one series may be provided, and this may be time-divisionally shared by each channel. As explained above, according to the present invention, a musical waveform signal that continues over a considerable number of cycles from the beginning of the sound is stored and read out, so that the timbre changes complexly over time. It is also possible to imitate musical tones with great precision. Furthermore, since the final waveform of the continuous tone waveforms is repeatedly read out, it is possible to deal with variations in the length of key press time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument according to the invention, and FIG. 2 is an example of a superimposed frequency division signal generation circuit corresponding to one note name included in the superposition frequency division signal generation section of FIG. 1. Figure 3 is a Breck diagram showing the 1st
4 is a circuit diagram showing an example of the interpolation circuit in FIG. 1; FIG. 5 is a circuit diagram showing an example of the opening/closing circuit in FIG. 1; 6
FIG. 1 is a circuit diagram showing an example of the final waveform hold circuit in FIG. 1. 20, 48, 67...Continuous musical sound waveform memory, 3
3... Interpolation circuit, 34... Final waveform hold circuit, 13C... One tone name superimposed frequency division signal generation circuit in the superimposed frequency division signal generation section 13, 19... Octave selection and address generation circuit.

Claims (1)

[Claims] 1. Pitch specifying means for specifying the pitch of a musical tone to be generated, and a memory that stores musical waveform data over a plurality of cycles, and based on the data read from the memory. a musical tone signal generating means for generating a musical tone signal; and a reading means for generating an address signal that changes at a speed corresponding to the pitch specified by the pitch specifying means and reading out data stored in the memory using the address signal. , when it is detected from the contents of the address signal that a set of stored data has been read out from the memory, the address signal indicates that data corresponding to one or more predetermined periods of the musical waveform is stored. control means for controlling the address signal so as to repeatedly designate the address of the memory; and generating an attenuated envelope waveform based on a signal instructing to stop sound generation, and controlling the amplitude of the musical tone signal using the attenuated envelope waveform. An electronic musical instrument equipped with a means for muting the sound. 2. The electronic musical instrument according to claim 1, wherein the musical tone signal generation means includes interpolation means for interpolating the amplitude between adjacent sample points of the musical tone signal. 3 Sound generation assignment that assigns a pressed key to one of a specific number of sound generation channels and outputs information representing the key assigned to each sound generation channel and a signal representing the press or release of the key corresponding to each sound generation channel. and a tone generator section that generates musical tone signals corresponding to keys assigned to each of the sound generation channels based on the output of the sound generation assignment means, and the tone generator section generates musical sound waveform data. and a memory that stores the musical tone waveform data stored in the memory over a plurality of cycles, and based on information representing the key assigned to each channel output from the sound generation assignment means, the data of the musical sound waveform stored in the memory is associated with the key. reading means for generating an address signal for sequential reading at a speed corresponding to a musical tone frequency; and after reading all the data stored in the memory in response to the address signal from the reading means, A control means for controlling the address signal so as to repeatedly read waveform data of one or more predetermined periods among the musical sound waveforms, and generating an attenuated envelope waveform based on a signal representing a key release given from the sound generation allocation means. and means for controlling the amplitude of the musical tone signal generated based on the data read from the memory corresponding to the channel in which the signal representing the key release is generated, by the attenuation envelope waveform, so as to cause the sound to be muted. An electronic musical instrument equipped with