JPH0467334B2 - - Google Patents

Info

Publication number
JPH0467334B2
JPH0467334B2 JP57038471A JP3847182A JPH0467334B2 JP H0467334 B2 JPH0467334 B2 JP H0467334B2 JP 57038471 A JP57038471 A JP 57038471A JP 3847182 A JP3847182 A JP 3847182A JP H0467334 B2 JPH0467334 B2 JP H0467334B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor
plane
layer
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57038471A
Other languages
Japanese (ja)
Other versions
JPS58155720A (en
Inventor
Akio Yoshikawa
Takashi Sugino
Masaru Kazumura
Kazunari Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57038471A priority Critical patent/JPS58155720A/en
Publication of JPS58155720A publication Critical patent/JPS58155720A/en
Publication of JPH0467334B2 publication Critical patent/JPH0467334B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421Arsenides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2907Materials being Group IIIA-VA materials
    • H10P14/2911Arsenides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202Materials thereof
    • H10P14/3214Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3221Arsenides

Landscapes

  • Recrystallisation Techniques (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 本発明は、表面に段差、溝などの凹凸部が形成
された基板上に結晶層が形成されてなる半導体装
置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a crystal layer is formed on a substrate whose surface has irregularities such as steps and grooves.

半導体装置を作製する方法の一つにエピタキシ
ヤル成長法が挙げられる。これはある基板の面上
にそれと異種の材料、或いはそれと同種の材料に
より、半導体層を形成するものである。この半導
体層形成の際に、以下の問題点がある。
Epitaxial growth is one of the methods for manufacturing semiconductor devices. In this method, a semiconductor layer is formed on the surface of a certain substrate using a material different from the substrate or a material of the same type as the substrate. When forming this semiconductor layer, there are the following problems.

基板面内で半導体エピタキシヤル成長層の厚
みがばらつくことがあり、時には半導体エピタ
キシヤル成長面に、四角すい形のピラミツド、
段差、渦巻きと通常呼ばれている様なものが生
ずる。以上の事より、ある基板上への均一な半
導体エピタキシヤル成長層の形成が妨げられ
る。
The thickness of the semiconductor epitaxial growth layer may vary within the substrate plane, and sometimes the semiconductor epitaxial growth surface has a square pyramid shape,
What is usually called a step or swirl occurs. As a result of the above, the formation of a uniform semiconductor epitaxial growth layer on a certain substrate is hindered.

段差、溝およびそれに類する凹凸部を表面に
形成した基板においては、上記問題点に加え
て、その基板上に形成した半導体エピタキシヤ
ル成長層の成長断面形状が基板面に沿つた方向
で著しくばらつく。
In addition to the above-mentioned problems, in a substrate having steps, grooves, and similar unevenness formed on the surface, the growth cross-sectional shape of the semiconductor epitaxial growth layer formed on the substrate varies significantly in the direction along the substrate surface.

上記問題点に加えて、同一の段差、溝およ
びそれに類する凹凸部に形成した半導体エピタ
キシヤル成長膜の断面形状が第1図、第2図に
示すように非対称になる。なお、第1図は表面
に段部が形成されたGaAs単結晶基板12であ
り、前記段部上から半導体成長層31が形成さ
れている。段部の左右における半導体成長層は
図より明らかなように左右非対称になつてい
る。
In addition to the above-mentioned problems, the cross-sectional shape of a semiconductor epitaxially grown film formed on the same step, groove, or similar unevenness becomes asymmetrical as shown in FIGS. 1 and 2. Note that FIG. 1 shows a GaAs single crystal substrate 12 with a stepped portion formed on its surface, and a semiconductor growth layer 31 is formed from above the stepped portion. As is clear from the figure, the semiconductor growth layers on the left and right sides of the stepped portion are asymmetrical.

また、第2図は表面に溝が形成されたGaAs単
結晶基板12を示しており、前記溝の上部から半
導体成長層31が形成されているが、溝内外の半
導体成長層は図より明らかなように左右非対称に
なつている。
FIG. 2 shows a GaAs single crystal substrate 12 with grooves formed on its surface, and a semiconductor growth layer 31 is formed from the top of the groove, but the semiconductor growth layer inside and outside the groove is clearly visible from the figure. The left and right sides are asymmetrical.

上記問題点を解決する1つの方法として、気
相成長法において、Si単結晶基板およびGaAs単
結晶基板で100面より数度の面指数ずれをもつ
た面を成長面として用い、均一な厚みの成長層を
得て、半導体装置を作製した例がある。
As one method to solve the above problems, in the vapor phase growth method, a plane with a plane index deviation of several degrees from the 100 plane is used as the growth plane of a Si single crystal substrate or a GaAs single crystal substrate, and a uniform thickness is obtained. There is an example of obtaining a growth layer and manufacturing a semiconductor device.

しかしながら、前記問題点〜を全て解決す
る方法は示されておらず、しかも段差、溝および
それに類する凹凸部を表面に形成した基板におい
て前記問題点を解決した例がない。
However, no method has been proposed to solve all of the above-mentioned problems, and furthermore, there is no example in which the above-mentioned problems have been solved in a substrate having steps, grooves, and similar unevenness formed on the surface.

本発明は、段差、溝およびそれに類する凹凸部
を面に形成した基板において、その段差、溝およ
びそれに類する凹凸部の形状を用い、その基板上
に半導体層を形成し、その半導体層の形状を制御
する事により、所望の電気的・光学的性質をもつ
半導体装置を作製する事を目的としたものであ
る。つまり、段差、溝およびそれに類する凹凸部
を表面に形成した基板を用いた半導体装置におい
て、その基板表面が100,111,110又は
これと同等の表面〔moo,nnm,kko;ただし、
m,n,kは2以上の整数〕に対し、二方向の面
指数ずれを指定する。すなわち、前記段差、溝等
の稜線方向の面指数ずれθ2が、上記稜線方向に垂
直方向の面指数ずれθ1よりも大きいことを特徴と
する半導体装置を提供するものである。
The present invention involves forming a semiconductor layer on the substrate using the shape of the steps, grooves, and similar unevenness on the surface of the substrate, and determining the shape of the semiconductor layer. The purpose is to manufacture semiconductor devices with desired electrical and optical properties through control. In other words, in a semiconductor device using a substrate having steps, grooves, and similar unevenness formed on the surface, the substrate surface is 100, 111, 110 or an equivalent surface [moo, nnm, kko;
m, n, k are integers of 2 or more], specify the surface index deviation in two directions. That is, the present invention provides a semiconductor device characterized in that the surface index deviation θ 2 of the step, groove, etc. in the ridgeline direction is larger than the surface index deviation θ 1 in the direction perpendicular to the ridgeline direction.

以下に実施例をあげて、本発明を具体的に説明
する。
The present invention will be specifically described below with reference to Examples.

ここでは、基板面として100面を用いてい
る。第4図a,bの平面および断面図に示す様に
基板面上に、その断面形状が逆メサとなる様に段
差をつけ、第3図、第4図a,bに示す様に、段
差の稜線方向の100面からの面指数ずれをθ2
段差の稜線方向に垂直方向の100面からの面指
数ずれをθ1とする。
Here, 100 planes are used as the substrate planes. As shown in the plane and cross-sectional views of Figures 4a and 4b, a step is formed on the substrate surface so that the cross-sectional shape becomes an inverted mesa, and as shown in Figures 3 and 4a and b, the step is The plane index deviation from the 100 plane in the ridge direction is θ 2 ,
Let θ 1 be the plane index deviation from the 100 plane in the direction perpendicular to the ridgeline direction of the step.

GaAs単結晶基板は、GaAsのインゴツトを治
具で固定し、これにより結晶面を決め、正確に切
り出される。100結晶面を利用する本発明の半
導体装置のGaAs単結晶基板では、〈011〉方
向およびそれに垂直な〈011〉方向の100結
晶面からのずれを、それぞれ、θ1およびθ2とす
る。これらθ1およびθ2の設定は、予め固定したイ
ンゴツトから切り出したGaAs基板の表面をX線
回折により解析して、θ1′とθ2′との各値を見定
め、次に、これらの値に基づいて、インゴツト固
定治具により調整して、θ1′→θ1,θ2′→θ2になる
ように設定して基板の切り出しを行なう。そして
この100結晶面に対して、段差の稜線方向をθ2
に合わせることにより、二方向の面指数の各ずれ
角θ1,θ2を確定することができる。
GaAs single-crystal substrates are cut out accurately by fixing a GaAs ingot with a jig and determining the crystal plane. In the GaAs single crystal substrate of the semiconductor device of the present invention that utilizes the 100 crystal plane, the deviations from the 100 crystal plane in the <011> direction and the <011> direction perpendicular thereto are defined as θ 1 and θ 2 , respectively. The settings of θ 1 and θ 2 are determined by determining the values of θ 1 ′ and θ 2 ′ by analyzing the surface of a GaAs substrate cut out from an ingot fixed in advance by X-ray diffraction, and then determining the values of θ 1 ′ and θ 2 ′. Based on this, the ingot fixing jig is adjusted so that θ 1 ′→θ 1 and θ 2 ′→θ 2 are set, and the substrate is cut out. And for these 100 crystal planes, the ridgeline direction of the step is θ 2
By adjusting the angles θ 1 and θ 2 of the plane indices in the two directions, it is possible to determine the deviation angles θ 1 and θ 2 of the plane indexes in the two directions.

ところで、第5図は、上述の第4図の様に段差
のついたGaAs単結晶基板面上に、液相結晶成長
法により、作製した段差基板型半導体レーザ(以
下TSレーザとよぶ)の断面形状を示す。結晶成
長開始温度は、850℃で、以下0.5C/分の冷却速
度で結晶成長を行なつた、10は、段差を形成す
るために基板表面に形成した面で、11は100
面から、θ1およびθ2だけの面指数ずれがある
GaAs単結晶基板面である。12はGaAs単結晶
基板、17はn型Gax1-xAsクラツド層、1
8はGay1-yAs活性層、19はp型Gax1-
Asクラツド層、20はn型GaAs層、21はn
型Gaz1-zAs層であり、5層構造の半導体レ
ーザ素子である。破線23で囲んだ円内の部分が
レーザ発振領域である。22で示す距離dは、
TSレーザの電気的・光学的特性上重要な距離で
ある。
By the way, FIG. 5 shows a cross section of a stepped substrate type semiconductor laser (hereinafter referred to as TS laser) manufactured by liquid phase crystal growth on a GaAs single crystal substrate surface with steps as shown in FIG. 4 above. Show shape. The crystal growth initiation temperature was 850°C, and the crystal growth was performed at a cooling rate of 0.5C/min. 10 is the surface formed on the substrate surface to form a step, and 11 is the surface of 100°C.
There is a plane index deviation of θ 1 and θ 2 from the plane.
This is the surface of a GaAs single crystal substrate. 12 is a GaAs single crystal substrate, 17 is an n-type Ga x A 1-x As cladding layer, 1
8 is Ga y A 1-y As active layer, 19 is p-type Ga x A 1-
x As clad layer, 20 is n-type GaAs layer, 21 is n
It is a Ga z A 1-z As layer, and is a semiconductor laser device with a five-layer structure. The area within the circle surrounded by the broken line 23 is the laser oscillation area. The distance d indicated by 22 is
This distance is important for the electrical and optical characteristics of the TS laser.

成長条件が全く同じで、GaAs単結晶基板の成
長面の100面からの面指数ずれθ1およびθ2
様々な値をとると、段差基板上に成長する層の段
差付近の成長層形状が、第6図aから第6図bに
示す様に変化していく。この様な変化は、段差上
に多層の結晶成長を行なつた時にも、第5図の半
導体レーザ素子のp型Gax1-xAsクラツド層
19の22に示す距離dの変化となつて表われ、
この素子の電気的・光学的特性を損い、期待しう
る半導体装置が得られないこととなる。
If the growth conditions are exactly the same, but the plane index deviations θ 1 and θ 2 from the 100 plane of the growth plane of the GaAs single crystal substrate take various values, the shape of the grown layer near the step of the layer grown on the step substrate will change. , changes as shown in FIG. 6a to FIG. 6b. Such a change also occurs when multilayer crystal growth is performed on a step, resulting in a change in the distance d shown at 22 of the p-type Ga x A 1-x As cladding layer 19 of the semiconductor laser device in Fig. 5. It appears,
This impairs the electrical and optical characteristics of this element, making it impossible to obtain a promising semiconductor device.

そこで、100面からの様々な面指数ずれの値
の組(θ1,θ2)を持つたGaAs単結晶基板面上に、
第5図のTSレーザ素子を作製したところ、以下
の事が明らかとなつた。
Therefore, on a GaAs single crystal substrate surface with various sets of plane index deviation values (θ 1 , θ 2 ) from the 100 plane,
When the TS laser device shown in Fig. 5 was fabricated, the following things became clear.

第7図a,b,c,dは、用いたGaAs単結晶
基板面の100面からの面指数ずれの値の組
(θ1,θ2)の代表的な一例を示している。100
面よりの面指数ずれの値の組に θ1<θ2 なる関係のある成長基板面上に第3図のTS型半
導体レーザを作製した時第7図a,bの方が、2
2の距離dは5μm以上にはほとんどならず、dの
バラツキもθ1>θ2なる関係をもつ場合第7図c,
dに比べて少ない。
FIGS. 7a, b, c, and d show a typical example of a set of plane index deviation values (θ 1 , θ 2 ) from the 100 plane of the GaAs single crystal substrate used. 100
When the TS type semiconductor laser shown in Fig. 3 is fabricated on the growth substrate surface where the set of plane index deviation values from the plane has a relationship of θ 1 < θ 2 , the TS type semiconductor laser shown in Fig. 7 a and b is 2
If the distance d of 2 is almost never more than 5 μm, and the variation in d has the relationship θ 1 > θ 2 , then Fig. 7c,
It is less than d.

従つて、実験的に100面より、θ1<θ2なる関
係のある面指数ずれの値の組(θ1,θ2)をもつた
GaAs単結晶基板面上に結晶成長を行なう方が、
段差を有する基板において、段差付近の形状を利
用する素子の作製には、例えば22の距離dでみ
られる様に、半導体層形状の制御性と再現性の良
さから、最適である事が、実験により種々試みた
結果わかつた。なお、第7図の面指数ずれの値の
組(θ1,θ2)は、一例で、θ1<θ2なる関係を満た
す全ての(θ1,θ2)で適用可能でθ1≦1pで特に効
果が著しい。
Therefore, from 100 planes, we experimentally found a set of plane index deviation values (θ 1 , θ 2 ) with the relationship θ 1 < θ 2 .
It is better to grow crystals on the GaAs single crystal substrate surface.
Experiments have shown that on a substrate with a step, it is optimal for manufacturing elements that utilize the shape near the step due to the controllability and reproducibility of the semiconductor layer shape, as seen for example at a distance d of 22. After various attempts, I found out. Note that the set of surface index deviation values (θ 1 , θ 2 ) shown in FIG. 7 is an example, and can be applied to all (θ 1 , θ 2 ) that satisfy the relationship θ 1 < θ 2 , and θ 1 ≦ The effect is particularly remarkable at 1 p .

また、面指数ずれの値の組(θ1,θ2)のθ1及び
θ2の正負により、結晶成長に与える影響を実験に
より求めたところ、第1図に示す様に段差(また
第2図に示すように溝内外)の両側で、半導体成
長層形状に非対称性があり、これらの非対称性の
程度は、θ1の正負と絶対値の大きさ、θ2との大小
関係により変わる。θ1<θ2の条件下では、第8
図、第9図の様に対称に半導体成長層が形成され
る事が、実験より明らかとなつた。
In addition, when we experimentally determined the effects on crystal growth depending on the positive and negative values of θ 1 and θ 2 of the set of plane index deviation values (θ 1 , θ 2 ), we found that the difference in level difference (and As shown in the figure, there is an asymmetry in the shape of the semiconductor growth layer on both sides (inside and outside the trench), and the degree of this asymmetry changes depending on the sign and negative of θ 1 , the magnitude of the absolute value, and the magnitude relationship with θ 2 . Under the condition θ 1 < θ 2 , the eighth
It has become clear from experiments that semiconductor growth layers are formed symmetrically as shown in FIGS.

半導体材料は、本例ではGaAsの場合を取り上
げたが、他のSiやGeおよび化合物半導体等他の
半導体材料でも同様に適用できる事が容易に類推
できる。以上説明したように本発明の半導体装置
は次の利点がある。
Although GaAs is used as the semiconductor material in this example, it can be easily inferred that other semiconductor materials such as Si, Ge, and compound semiconductors can be similarly applied. As explained above, the semiconductor device of the present invention has the following advantages.

段差、溝およびそれに類する凹凸部を表面に
形成した基板において、その基板上に形成した
半導体エピタキシヤル成長層の断面形状を、同
一成長条件下では、再現性よく半導体装置を作
製する事ができる。
In a substrate having steps, grooves, and similar unevenness formed on the surface, a semiconductor device can be manufactured with good reproducibility under the same growth conditions with the cross-sectional shape of a semiconductor epitaxial growth layer formed on the substrate.

第1図、第2図を例とする様な段差、溝およ
びそれに類する凹凸部の近傍での半導体エピタ
キシヤル成長層の断面形状が対称な半導体装置
を作製する事ができる。
It is possible to fabricate a semiconductor device in which the cross-sectional shape of the semiconductor epitaxial growth layer is symmetrical in the vicinity of steps, grooves, and similar uneven portions as shown in FIGS. 1 and 2 as examples.

基板上への多層成長の場合には、基板上の層
の成長形状の制御以外に、基板とは直接接して
いない層の成長形状をも制御でき、これを応用
した半導体装置が作製できる。
In the case of multilayer growth on a substrate, in addition to controlling the growth shape of layers on the substrate, it is also possible to control the growth shape of layers that are not in direct contact with the substrate, and a semiconductor device can be manufactured by applying this.

段差、溝およびそれに類する凹凸部を表面に
形成した基板を用いる場合、段差、溝などの影
響を余り受けない基板平坦部において、半導体
成長層の厚みを均一にする事ができ、所望の厚
みを再現性良く形成した半導体装置を作製する
事ができる。
When using a substrate with steps, grooves, and similar unevenness formed on the surface, the thickness of the semiconductor growth layer can be made uniform on the flat portion of the substrate that is not affected by the steps, grooves, etc., and the desired thickness can be achieved. A semiconductor device formed with good reproducibility can be manufactured.

なお、以上述べた実施例からもわかる様に、
本発明は半導体三次元集積回路、光集積回路を
はじめとする半導体集積回路に適用可能であ
る。
Furthermore, as can be seen from the examples described above,
The present invention is applicable to semiconductor integrated circuits including three-dimensional semiconductor integrated circuits and optical integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は、面指数ずれの値の組(θ1
θ2)でθ1>θ2なる時の、段差、溝の近傍での半導
体成長層の非対称な形状を示す従来の半導体装置
の断面図、第3図は、100面からの面指数ずれ
の値(θ1,θ2)の定義を示す図、第4図a,bは
本発明の実施例で用いた段差を付けたGaAs単結
晶基板の平面図および断面図、第5図は、本発明
の一実施例における半導体装置である段差基板型
半導体レーザの断面図、第6図a,bは、GaAs
単結晶基板面の100面からの面指数ずれの値
(θ1,θ2)により、段差付近の成長形状が変わる
事を示す断面図、第7図a,b,c,dは、面指
数擦れの値(θ1,θ2)により、レーザの電気的・
光学的性質の性能指数の1つとしての距離dの大
きさの分布と、そのバラツキの範囲を示す図、第
8図、第9図は、面指数ずれの値の組(θ1,θ2
でθ1>θ2なる時の段差、溝の近傍での半導体成長
層の対称な形状を示す断面図である。 10……段差を形成するのに堀つた面、11…
…100面からの面指数ずれを有するGaAs単結
晶基板面、12……GaAs単結晶基板、15,1
6,31……半導体成長層、17……n型Gax
1-xAsクラツド層、18……Gay1-yAs活性
層、19……p型Gax1-xAsクラツド層、2
1……n型Gaz1-zAs層、20……GaAs層、
22……距離d、23……レーザ発振領域。
Figures 1 and 2 show a set of plane index deviation values (θ 1 ,
Figure 3 is a cross-sectional view of a conventional semiconductor device showing the asymmetrical shape of the semiconductor growth layer near the step and groove when θ 1 > θ 2 at θ 2 ). A diagram showing the definition of the values (θ 1 , θ 2 ), FIG. FIGS. 6a and 6b are cross-sectional views of a stepped substrate type semiconductor laser which is a semiconductor device according to an embodiment of the invention.
Figure 7 a, b, c, and d are cross-sectional views showing that the growth shape near the step changes depending on the plane index deviation value (θ 1 , θ 2 ) from the 100 plane of the single crystal substrate plane. The value of friction (θ 1 , θ 2 ) determines the electrical
Figures 8 and 9, which show the distribution of the size of distance d as one of the figures of merit of optical properties and the range of its dispersion, show the set of surface index deviation values (θ 1 , θ 2 )
FIG. 2 is a cross-sectional view showing the symmetrical shape of the semiconductor growth layer near the step and groove when θ 12 . 10... Surface excavated to form a step, 11...
...GaAs single crystal substrate surface with plane index deviation from 100 plane, 12...GaAs single crystal substrate, 15,1
6, 31... Semiconductor growth layer, 17... n-type Ga x A
1-x As clad layer, 18...Ga y A 1-y As active layer, 19...p-type Ga x A 1-x As clad layer, 2
1... n-type Ga z A 1-z As layer, 20... GaAs layer,
22...Distance d, 23...Laser oscillation area.

Claims (1)

【特許請求の範囲】[Claims] 1 表面に段差、溝などの凹凸部を有する基板上
に結晶層の形成された半導体装置の製造方法にお
いて、前記基板の表面が、100,110,11
1またはこれと同等の面指数に対し、前記凹凸部
の稜線方向に平行の面指数ずれが、前記稜線方向
に垂直方向の面指数ずれよりも大きいことを確認
したのち、前記凹凸部上に半導体膜を成長するこ
とを特徴とする半導体装置の製造方法。
1. In a method for manufacturing a semiconductor device in which a crystal layer is formed on a substrate having irregularities such as steps and grooves on the surface, the surface of the substrate is 100, 110, 11
1 or an equivalent surface index, after confirming that the surface index deviation parallel to the ridgeline direction of the uneven portion is larger than the surface index deviation in the direction perpendicular to the ridgeline direction, a semiconductor is placed on the uneven portion. A method for manufacturing a semiconductor device characterized by growing a film.
JP57038471A 1982-03-10 1982-03-10 Semicondutor device Granted JPS58155720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57038471A JPS58155720A (en) 1982-03-10 1982-03-10 Semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57038471A JPS58155720A (en) 1982-03-10 1982-03-10 Semicondutor device

Publications (2)

Publication Number Publication Date
JPS58155720A JPS58155720A (en) 1983-09-16
JPH0467334B2 true JPH0467334B2 (en) 1992-10-28

Family

ID=12526153

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57038471A Granted JPS58155720A (en) 1982-03-10 1982-03-10 Semicondutor device

Country Status (1)

Country Link
JP (1) JPS58155720A (en)

Also Published As

Publication number Publication date
JPS58155720A (en) 1983-09-16

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