JPH0467683A - Velocity modulated field effect transistor - Google Patents

Abstract

PURPOSE:To enable a velocity modulated field effect transistor to operate at a high speed by a method wherein a channel section is composed of channel layers, and the channel layers are laminated interposing an electron barrier layer of insulator or semiconductor between them. CONSTITUTION:A channel section 5 is provided with channel layers 61 and 62, and the channel layers 61 and 62 are laminated interposing an electron barrier layer 12 identical to electron barrier layers 4 and 8 between them. A load is provided between a source electrode 10 and a drain electrode 11, a required power supply is connected, and when a control voltage of 0(V) is applied to gate electrodes 3 and 9 on the basis of a source electrode 10, electrons are distributed in channel layers 61 and 62 composed of a high speed electron channel layer 7H and a low speed electron channel layer 7L and travel between the source electrode 10 and the drain electrode 11.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a velocity modulated field effect transistor.

[Prior Art 1] Conventionally, a velocity modulation type field effect transistor has been proposed which will be described below with reference to FIG. That is, a semi-insulating semiconductor substrate 1 made of GaAS, for example.
A buffer layer 2 made of, for example, QaAs in which neither an n-type impurity nor an n-type impurity is intentionally introduced is formed on the semi-insulating semiconductor substrate 1. Further, within the buffer layer 2, a gate electrode 3 made of metal such as n+-GaAs or AI has an upper surface extending on the same surface as the upper surface of the buffer layer 2. It is arranged. Further, on the buffer layer 21, an electron barrier layer 4 of, for example, n+-A I QaAs, which extends continuously over the upper surface of the gate electrode 3, is formed to have a thickness of, for example, 300 Å. Further, on the electron barrier layer 4, a low-speed electron channel layer part 7 made of a semiconductor layer capable of obtaining a low electron velocity and a fast electron channel layer part 7 made of a semiconductor layer capable of obtaining a high electron velocity are placed on the former. A channel portion 5 is formed to the right of one of the channel layers 6 made of a laminate in which the latter is laminated. In this case, the semiconductor layer constituting the slow electron channel layer portion 7L is made of GaAs, for example, and has impurities of, for example, Sl and Be introduced at a high concentration of, for example, 2 x 1018 cm-3, and has a thickness of, for example, 300A. . Further, the semiconductor layer constituting the high speed electron channel layer section 7H is made of, for example, the same GaAS as the semiconductor layer constituting the low speed electron channel layer section 7L, but the semiconductor layer constituting the low speed electron channel layer section 7L is Impurities such as the impurities introduced in the present invention are not substantially introduced, or even if they are introduced, they are only at a much lower concentration than in the case of the semiconductor layer constituting the slow electron channel layer portion 4L. It has not been introduced. Further, on the channel portion 5, an n''
- A I Through the electron barrier layer 8 made of GaAs and having the same thickness, for example, the n''
- A gate electrode 9 made of metal such as GaAS or A1 is locally arranged. Further, a source electrode 10 and a drain electrode 11 are connected to the channel portion 5 at both positions with the gate electrode 9 interposed therebetween. In addition, in the figure, the source electrode 10 and the drain electrode 1
1 forms a metal electrode material layer on both sides of the gate electrode 9 on the electron barrier layer 8, and then heats the metal constituting the metal electrode material layer to form the electron barrier layer 8.
, is formed by diffusing into the channel layer 5 and the electron barrier layer 4 and alloying with them. The above is the configuration of the speed modulation type field effect transistor that has been proposed in the past. According to the conventional velocity modulation field effect transistor having such a configuration, the source electrode 10 and the drain electrode 1
1, with the required power supply connected through the load, the control voltages g3 and V, 9 are applied to the gate electrodes 3 and 9, respectively, with the source electrode 10 as a reference, and both are set to 0 (
V), electrons are distributed in both the low-speed electron channel layer 7L and the high-speed electron channel layer 7H constituting the channel layer 6, as shown by the band structure in FIG. 5A. As a result, a state is obtained in which the electrode runs between the source electrode 10 and the drain electrode 11. However, from such a state, the gate electrodes 3 and 9 are subjected to a controlled mHz pressure. 3 and vg. , the source electrode 10
By applying the required negative and positive values to the base, the high-speed electron channel layer portion 7H is formed on the low-speed electron channel local portion 7L, and the gate electrode 9 is disposed on the channel portion 5. Therefore, as shown in the band structure in Figure 5B, the number of electrons is the same as when the control voltages V, 3 and vg9 are applied to the gate electrodes 3 and 9 at a value of 0 (V). Then, an equilibrium state is reached in which the high-speed electrons are distributed only in the channel layer portion 7H constituting the channel layer 6 and run between the source electrode 10 and the drain electrode 11, and the control ! I
If the voltages 1, 3 and vg9 are applied at the required positive and negative values, respectively, contrary to the above case, the electrons will form the gate electrodes 3 and 3, as shown in the band structure of FIG. 5C. With the same number of electrons as when the control voltages g3, g3, and 9 are both applied to 9 at a value of 0 (V), the high-speed electron channel layer 7
The source electrode 10 and the drain electrode 1 are distributed only in L.
It is in an equilibrium state where it is running for 1 hour. In this case, the speed of the electrons traveling between the source m$410 and the drain electrode 11 is different between when the electrons are distributed and traveling only in the fast electron channel layer section 7H and when the electrons are traveling only in the slow electron channel layer section 7L. In the case where only
The former case is faster than the latter, and they are different from each other. From the above, according to the conventional speed modulation field effect transistor shown in FIG. 4, the mutual conductance of the channel portion 5 is as shown in FIG.
The control voltages applied to the gate electrodes 3 and 9 respectively vary depending on the polarities and values of V and g9, and therefore the control voltages applied to the gate electrodes 3 and 9 respectively change the gain depending on the polarities and values of g3 and Vg9. do. In addition, FIG. 6 shows the control voltage V
is shown as O when V=Vg3−■g9teal. Problem to be Solved by the Invention 1 However, in the case of the conventional velocity modulation field effect transistor shown in FIG. ,
A mode in which electrons increase in the high-speed electron channel layer section 7H (or the low-speed electron channel layer section 7L) constituting the channel layer 6 when changed to the required negative and positive (or positive and negative) values, respectively. Therefore, the frequency of the control I lightning voltages g3 and Vg9 applied to the gate electrodes 3 and 9 can only be increased to a value that changes when the electrons reach the above-mentioned equilibrium state. For this reason, in the case of the conventional fast modulation type field effect transistor shown in Fig. 4, the cutoff frequency f1 is relatively low, and therefore, the operation as a speed modulation type field effect transistor can only be obtained at a relatively low speed. It had the disadvantage that it could not be done. Therefore, the present invention seeks to propose a novel speed modulating field effect transistor that does not have the above-mentioned drawbacks. [Means for Solving the Problems] The speed modulating field effect transistor according to the present invention has a fourth
As in the case of the conventional velocity-modulated field effect transistor described above in the figure, there are two parts: (1) a low-speed electron channel layer made of a semiconductor layer that provides a low electron velocity; and a high-speed electron channel layer made of a semiconductor layer that provides a high electron velocity. a channel portion having a channel layer made of a laminate of; and (1) a gate disposed on the channel layer with an electron barrier layer made of an insulator or semiconductor interposed therebetween, so as to face the main surface of the channel layer. and (2) a source electrode and a drain 'lff1 connected to the channel portion at both positions sandwiching the gate electrode. However, in the speed modulation field effect transistor according to the present invention, in the speed modulation field effect transistor having such a configuration, (1) the channel portion has a plurality of the channel layers, and (2) the channel portion has a plurality of the channel layers. are stacked with another electron barrier layer made of an insulator or semiconductor interposed therebetween. [Operation/Effect] According to the speed modulation type field effect transistor according to the present invention, when a required power source is connected between the source electrode and the drain electrode through the load, the Ill I
If the 11 voltage is applied at a value of 0 (V) with the source electrode as a reference, electrons will move across multiple channel layers, as in the case of the conventional velocity modulation field effect transistor described above in FIG. For each of them, there are 47 states in which the electrons are distributed in both the fast electron channel layer portion and the slow electron channel layer portion constituting the layer, and run between the source electrode and the drain electrode. However, from such a state, for each of the plurality of channel layers, if the high-speed electron channel layer part is formed on the low-speed electron channel layer part (the same applies hereinafter), then in the case where the high-speed electron channel layer part is formed above the channel part, and vice versa, When a control voltage is applied at a required positive value with respect to the source electrode to the gate electrode disposed under the channel part, electrons are transferred to the high-speed electron channel layer for each of the plurality of channel layers. The electrons are distributed only between the source electrode and the drain electrode, and then the electrons are applied at the required value of the III control voltage in the plurality of channel layers. The high-speed electrons are distributed only in the channel region constituting the channel layer closest to the gate electrode and run between the source and drain electrodes, and the control voltage is applied to the gate electrode as described above. If a required negative value is applied with the source electrode as a reference, electrons will be distributed only in the slow electron channel layer portion of each of the plurality of channel layers and travel between the source electrode and the drain electrode. state, and then electrons are transferred only to the slow electron channel layer portion of the plurality of channel layers, which constitutes the channel layer farthest from the above-mentioned gate electrode to which the control voltage is applied with the required negative value. It is distributed and reaches an equilibrium state running between the source electrode and the drain N pole. In this case, as described in the conventional velocity modulation field effect transistor shown in FIG. The difference is that the former case is faster than the latter case, and the former case is faster than the latter case. From the above, in the case of the speed modulation type field effect transistor according to the present invention, the mutual conductance of the channel portion is applied to the gate electrode as in the case of the conventional speed modulation type field effect transistor described above in FIG. The Ha lightning voltage changes depending on the polarity and value, and therefore exhibits a gain depending on the polarity and value of the control voltage applied to the gate electrode. However, when the velocity modulation according to the present invention is applied to a field effect transistor, the above-mentioned equilibrium state of electrons in the channel region can be obtained from the time when the control voltage is applied to the above-mentioned gate electrode at a required positive (or negative) value. Up to this point, electrons are transferred to each of the plurality of channel layers in the high electron velocity semiconductor layer portion (
However, at time points g and R at which the above-mentioned equilibrium state of electrons is obtained, the electrons increase in the positive control voltage ( For the channel layer closest to (or farthest from) the gate electrode, which is applied with the required value (or negative), the above-mentioned Even if the first mode is maintained or changes slightly from that state, the high electron velocity semiconductor layer portion (or the low electron velocity semiconductor layer portion) constituting the channel layer remains The conventional velocity variation m, which is described above in FIG. Therefore, the frequency of the control voltage applied to the gate electrode is
It can be a value higher than the value of the frequency that the electrons change to when they reach the equilibrium state described above. Therefore, in the case of the speed modulation type field effect transistor according to the present invention, the cutoff frequency is higher than that of the conventional speed modulation type field effect transistor described above in FIG. The operation can be made faster than that of the conventional speed modulation type field effect transistor described above with reference to FIG.

【Example】

Next, referring to FIG. 1, an embodiment of the speed modulation type field effect transistor according to the present invention will be described. In FIG. 1, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. The speed modulating field effect transistor according to the present invention shown in FIG. 1 differs from the conventional speed modulating field effect transistor described above in FIG. Instead, a plurality of channel layers similar to the channel layer 6, two in the figure, are used.
In FIG. It has the same configuration as the conventional velocity modulation type field effect transistor described above. The above is the configuration of the embodiment of the speed modulation type field effect transistor according to the present invention. According to the speed-modulated field effect transistor of the present invention having such a configuration, when a required power source is connected between the source electrode 10 and the drain electrode 11 through a load, the gate electrodes 3 and 9 are The electric control voltage and 93g9 are both 0 (with the source electrode 10 as a reference).
If the voltage is applied at a value of For each of 61 and 62, the source voltage V7A10 is distributed between the high speed electron channel body 7 and the low speed electron channel layer 7 constituting it.
A state is obtained in which the conductor is running between the drain electrode 11 and the drain electrode 11. However, from this state, if control voltages g3 and g9 are applied to the gate electrodes 3 and 9 at required negative and positive values with respect to the source electrode 10, the plurality of channel layers 61 and 62, the high-speed electron channel layer section 7H is formed on the low-speed electron channel partition section 7L, and the gate electrode 9 is arranged on the channel section 5, so that electrons are
As shown in the band structure, the high-speed electrons are distributed only in the channel layer portion 7H of each of the plurality of channel layers 61 and 62 and run between the source electrode 10 and the drain electrode 11, and the next As shown in the band structure of FIG. The high-speed electron channel layer 7H forming the channel layer 62 closest to the gate electrode 9 to which 9 is applied at a required value with a positive value is distributed and runs between the source electrode 10 and the drain electrode 11. Also, the gate electrodes 3 and 9 are in an equilibrium state.
If control voltages V, 3 and V, 9 are respectively applied at the required positive and negative values with respect to the source electrode 10, the electrons will move in the opposite direction to the case in FIG. 2B, although not shown. To,
For each of the plurality of channel layers 61 and 62,
The electrons are distributed only in the low-speed electron channel layer portion 7L and travel between the source electrode 10 and the drain electrode 11, and then, although not shown, the electrons are similarly distributed in the case shown in FIG. 2C. On the contrary, a plurality of channel layers 61 and 6
Out of 2, control! a The channel Fi6 farthest from the gate electrode 9 where the voltage V,9 is applied at the required value with a negative value.
A second equilibrium state is reached in which the electrons are distributed only in the low-speed electron channel layer portion 7L constituting the electron beam 1 and run between the source electrode 10 and the drain electrode 11. In this case, as described in the conventional velocity modulation field effect transistor shown in FIG. There is a difference between the case where the electrons travel as a whole and the case where the electrons travel distributed over the low-speed electron channel layer portion 7L in that the former case is faster than the latter case. From the above, in the case of the speed modulation type field effect transistor according to the present invention shown in FIG. 1, the mutual conductance of the channel portion 5 is the same as in the case of the conventional speed modulation type field effect transistor described above in FIG. , changes depending on the polarity and value of the control voltages V 1 and Vg9 applied to the gate electrodes 3 and 9, respectively, and thus the control voltages g3 and ■ applied to the gate electrodes 3 and 9, respectively. It exhibits a gain depending on the polarity and value of 9. However, in the case of the velocity modulated field effect transistor according to the present invention shown in FIG.
Voltage ■, 3 and ■. Between the time when 9 is applied at the required negative and positive (or negative and positive) values, and the time when the above-mentioned equilibrium state of electrons in the channel section 5 is obtained, the electrons pass through the plurality of channel layers. Regarding each of 61 and 62, the high electron velocity semiconductor layer portion 7H (or the low electron velocity semiconductor layer portion 7L) constituting it
), but after the point at which the electrons reach the above-mentioned equilibrium state, the electrons become
Control voltage v,9 in the plurality of channel layers 61 and 62
For the channel layer 62 (or 61) closest (or farthest) to the gate electrode 9 (or 3) to which is applied with a required positive (or negative) value, the high electron velocity semiconductor layer portion constituting it Even if 7H (or low electron velocity semiconductor layer section 71) maintains the above-mentioned first mode state or slightly changes from that state, each of the other channel layers (in the case of the figure, the channel The layer 61 (or 62) takes a second mode in which it decreases in the high electron velocity semiconductor layer section 7H (or the low electron velocity semiconductor layer section 7L) that constitutes the layer 61 (or 62). For this reason, the frequencies of the control voltages VC+3 and V(+9 applied to the gate electrodes 3 and 9, respectively) are changed at the time when the electrons reach the above-mentioned equilibrium state, such that the frequencies of the control voltages VC+3 and V(+9) applied to the gate electrodes 3 and 9, respectively, are changed by the time when the electrons reach the above-mentioned equilibrium state. Therefore, in the case of the speed-modulated field effect transistor according to the present invention shown in FIG. It is several times higher (twice in the case of the figure) than the conventional speed modulating field effect transistor described above in Figure 4. It is possible to operate at a higher speed than in the case of a speed modulation type field effect transistor.The above description merely shows one embodiment of the present invention; In the structure of the modulation type field effect transistor, instead of the structure in which the gate electrode 3 is disposed in the buffer layer 2 on its upper surface side, a structure in which the gate electrode 3 is formed on the buffer layer 2 may also be adopted. The layer 2 is omitted, and the gate electrode 3 is arranged in the semi-insulating semiconductor substrate 1 on its upper surface side or on the semi-insulating semiconductor substrate 1 accordingly. Furthermore, it is also possible to omit one of the gate electrodes 3 and 9.Also, although the electron barrier layers 4, 12 and 8 are made of a semiconductor layer having n+, Alternatively, the source electrode 10 and the drain electrode 11 may be made of an insulator, and the gate electrode 9 may be sandwiched between the source electrode 10 and the drain electrode 11 within a stacked body of the electron barrier layer 4, the channel portion 5, and the electron barrier layers 8 and 12. It may also be formed of semiconductor regions having n+ type formed at both positions.Furthermore, for each of the plurality of channel layers 61 and 62, the high speed electron channel layer portion 7H is formed on the low speed electron channel peripheral portion 7L. Instead of having the structure shown in FIG. In addition, various modifications and changes may be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of a velocity modulated field effect transistor according to the present invention. FIG. 2 is a diagram showing the operation using a band structure. FIG. 3 is a diagram showing the frequency dependence of the gain of the speed modulated field effect transistor according to the present invention shown in FIG. 1 in comparison with that of the conventional speed modulated field effect transistor shown in FIG. FIG. 4 is a cross-sectional view showing a conventional speed modulation field effect transistor. FIG. 5 is a diagram showing the operation using a band structure. FIG. 6 is a diagram illustrating the relationship between the mutual conductance of the channel portion and the control II lightning voltage applied to the gate electrode, for use in explaining the velocity modulation type field effect transistor shown in FIGS. 1 and 4. FIG. 1...Semi-insulating semiconductor substrate 2...Buffer layer 3...
・・・・・・・・・・・・Gate electrode 4・・・・・・・
......Electron barrier layer 5...
...Channel part 6.61.62 ......Channel layer 7L...
......Low speed electron channel layer section 7H...
......High-speed electron channel layer section 8...
.........Electron barrier layer 9...
......Goo 1 ~ Electrode 10...
......Source electrode 11...
...Drain electrode 12...
...Electronic barrier layer applicant Nippon Telegraph and Telephone Corporation Figure 2 Figure 1 T Figure 4 Figure 5

Claims (1)

[Claims] 1. A channel section having a channel layer made of a laminate of a slow electron channel layer section made of a semiconductor layer capable of obtaining a low electron velocity and a fast electron channel layer section made of a semiconductor layer capable of obtaining a high electron velocity; a gate electrode disposed on the channel portion with an electron barrier layer made of an insulator or semiconductor interposed therebetween so as to face the main surface of the channel layer; In a velocity modulation field effect transistor having a source electrode and a drain electrode connected to each other in position, the channel portion has a plurality of the channel layers, and the plurality of channel layers are made of an insulator or a semiconductor. A velocity modulation field effect transistor characterized in that the transistor is laminated with another electron barrier layer interposed therebetween.