JPH0467754U

JPH0467754U -

Info

Publication number: JPH0467754U
Application number: JP11097190U
Authority: JP
Priority date: 1990-10-23
Filing date: 1990-10-23
Publication date: 1992-06-16

Description

[Brief explanation of drawings]

第１図ａ，ｂはそれぞれ本考案の一実施例を示
すブロツク図及びこの実施例のアドレス・コント
ロールレジスタのデータフオーマツト図、第２図
及び第３図は第１図ａ，ｂに示された実施例の動
作を説明するための転送元メモリ、転送先メモリ
間のＤＭＡ転送データの流れを示す模式図、第４
図及び第５図はそれぞれ第１図ａ，ｂに示された
実施例の第１及び第２の適用例を示す模式図であ
る。１……バス・コントロールユニツト、２……Ｄ
ＭＡ制御部、３……アドレスインクリメンタ・デ
イクリメンタ、４……アドレスレジスタ部、５…
…コントロールレジスタ部、６……カウントレジ
スタ部、７……カウントデイクリメンタ、８……
アドレスバス、９……データバス、４１……カレ
ント・レジスタ、４２……ベース・レジスタ、５
２……アドレス・コントロールレジスタ、８０…
…外部アドレスバス、９０……外部データバス、
３００……ＰＲＯＭライタ、３０１……１６ビツ
トＣＰＵ、３０２……偶数アドレスメモリ、３０
３……奇数アドレスメモリ、３０４……ＰＲＯＭ
、４１０……キヤラクタメモリ、４２０……ゲー
トアレイ、４３０……プリンタ・ヘツド、４３１
Ａ，４３１Ｂ……ヘツドピン。 Figures 1a and 3 are a block diagram showing an embodiment of the present invention and a data format diagram of the address control register of this embodiment, respectively, and Figures 2 and 3 are shown in Figure 1a and b. FIG. 4 is a schematic diagram showing the flow of DMA transfer data between a transfer source memory and a transfer destination memory for explaining the operation of the embodiment.
1 and 5 are schematic diagrams showing first and second application examples of the embodiment shown in FIGS. 1a and 1b, respectively. 1...Bus control unit, 2...D
MA control unit, 3...Address incrementer/decrementer, 4...Address register unit, 5...
...Control register section, 6...Count register section, 7...Count decrementer, 8...
Address bus, 9...Data bus, 41...Current register, 42...Base register, 5
2...Address control register, 80...
...External address bus, 90...External data bus,
300...PROM writer, 301...16-bit CPU, 302...Even number address memory, 30
3...odd address memory, 304...PROM
, 410...character memory, 420...gate array, 430...printer head, 431
A, 431B...Head pin.

Claims

[Scope of utility model registration request]

A base register that stores the first address of the address area to be accessed in the transfer source memory, and an address control that stores data indicating the data length of the data to be transferred, the update direction and update unit of sequentially updated addresses, and the update contents. an address incrementer/decrementer that sequentially updates the address stored in the base register as the first address according to the data stored in the address control register;
A DMA controller comprising a current register that temporarily holds and outputs an address updated by a decrementer.