JPH02105250A - Data transfer system - Google Patents

Abstract

PURPOSE:To improve data transfer efficiency by writing a telegram on a shared RAM by a processor when the quantity of a null area in the shared RAM exceeds that of a telegram to be written next. CONSTITUTION:A leading address (1) which changes at every readout of data from the shared RAM 3 by the processor 2 on a readout side is stored in a readout leading address storage means 5. The processor 1 on a write side stores the final address (2) written previously, and read out the leading address from the means 5 by a null area calculation write request sending means 6, and calculates the quantity of the null area in the RAM 3. When the quantity of the null area exceeds that of the data to be written next, a write request is outputted to a shared RAM arbitration circuit 4. The circuit 4 gives the dedicated right of the shared RAM to the request with high priority, however, when an interval for the delivery of the data to the next stage after changing to serial data is generated, the dedicated right is given to the processor 1, thereby, the next telegram can be written.

Description

[Detailed Description of the Invention] [Summary] A shared RAM is used, and data is transferred between a plurality of processors by bus exchange of the shared RAM in a shared RAM stop means that arbitrates the right to use the shared RAM. With regard to the data transfer method of a multiprocessor system that uses ordinary RAM, the present invention aims to provide a data transfer method with high data transfer efficiency, and a read start address storage means that updates and stores the read start address of a shared RAM every time it is read. And, from the last address written earlier and the start address read from the read start address storage means, the shared R
Calculate the amount of free space in AM, compare it with the amount of data to be written next, and if the amount of free space is less than the amount of data to be written next, send a write request to the shared RAM arbitration means Free space calculation write request sending The structure has a means.

[Industrial application field]

The present invention provides a multiprocessor system that uses a shared RAM and transfers data between a plurality of processors by exchanging buses of the shared RAM in a shared RAM arbitration means that arbitrates the right to use the shared RAM. Concerning improvements in data transfer methods.

[Conventional technology]

There are three methods of data transfer in conventional multiprocessor systems as shown below.

■Write byte by byte to the shared RAM, and after writing is completed,
A byte-by-byte transfer method in which the processor on the other side reads the data, and when the read is completed, writes the next one hide.

- A message unit transfer method in which a message is written to the shared RAM in units of messages, and after the writing is completed, the other party's processor reads it, and when the reading is completed, it writes the next message.

■Dual Port RAM transfer method that uses Dual Port RAM to freely read and write.

[Problems to be Solved by the Invention] However, in the byte unit transfer method, since writing and reading are repeated in byte units, there is a problem that it takes time to transfer a large amount of data and data transfer efficiency is poor.

In the message unit transfer method, the next message cannot be written unless all the messages written by the other party are read. Especially when it takes a long time to complete the read, writing the next message becomes slow, reducing data transfer efficiency. There is a bad problem.

The dual port RAM transfer method allows two processors to freely write and read data, but there is a problem in that the dual port RAM used is expensive.

The present invention aims to provide a data transfer method that uses a normal RAM and has high data transfer efficiency.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, the shared RAM 3 is used and the shared RA
In the shared RAM arbitration means 4 that arbitrates the right to use M3,
By exchanging the bus of the shared RAM 3, a plurality of processors 1.
In a multiprocessor system that transfers data between two processors, the read start address storage means 5 updates and stores the read start address of the shared RAM 3 every time it is read, and the read start address storage means stores the previously written last address and the read start address. The amount of free space in the shared RAM 3 is calculated from the first address read from step 5, and compared with the amount of data to be written next. If the amount of free space is greater than the amount of data to be written next, a write request is sent to the shared RAM 3. Stop means 4
Free space calculation write request sending means 6 is provided to send out a free space calculation write request.

[For production]

The operation of the present invention will be described with reference to FIG. 1 and FIG. 2, which is a diagram illustrating the start of writing to the shared RAM 3 in FIG. 1, for the case where a message is transferred.

In FIG. 1, the free space calculation write request sending means 6 is provided only on the processor 1 side, so this is an example where processor 1 writes and processor 2 reads, and the free space calculation write request sending means 6 is provided on the processor 1 side. If it is provided on the second side, it can be applied when one processor writes and another processor reads.

Every time the processor 2 on the reading side in FIG. 1 reads data from the shared RAM 3, the starting address (2) shown in FIG. I remember it at.

In addition, the processor 1 on the writing side stores the last address written earlier, and uses the free space calculation write request sending means 6 to store the read start address that changes as follows in the read start address storage means 5. Then, the amount of free space in the shared RAM 3, a+b+c in FIG. 2, is calculated.

The amount of this free space increases every time the processor 2 reads data, so when the amount of this free space becomes larger than the amount of data to be written next, a write request is output to the shared RAMI stop means 4.

The shared RAM arbitration means 4 gives exclusive rights to the shared RAM to those with a higher priority, but when there is an interval to serialize the read data and send it to the next stage, the shared RAM arbitration means 4 gives the exclusive rights to the processor 1. , now you can write the following message.

In other words, data transfer efficiency is improved because writing becomes possible when a free area for writing the next message occurs without waiting for all reading to be completed.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 3 is a block diagram when performing start-stop synchronization communication according to the embodiment of the present invention, in which a message is sent from processor 1 to processor 2.
An example is shown in which the asynchronous communication control unit 12 transmits serialized data to the partner station in an asynchronous manner.

First, the operation of the shared RAM arbitration unit 9 will be explained.
When there is a write/read request (REQ) from the processors 1 and 2 to the shared RAM 3, an acknowledgment (ACK) is output to the one with a higher priority, and the gate circuit 10 or 1
1 so that it can be used exclusively by the processor on the side that received the acknowledgment.

To explain the asynchronous communication control unit 12, it serializes, for example, 1 byte of data read from the shared RAM 3 by the processor 2, adds a start bit, a stop bit, etc., and sends it out in an asynchronous format. If it takes, for example, 1 μs for the processor 2 to read one byte of data, the time it takes to send it is several μs.

Next, a sequence in which data is transferred from the processor 1 to the processor 2 side in FIG. 3 and the data is sent out from the asynchronous communication control section 12 will be described.

First, when the processor 1 issues a write request to the shared RAM 3, the shared RAM arbitration unit 9 outputs an affirmative response to the processor 1 and opens the gate circuit 10.

With this positive response, processor 1 knows that writing is possible, and
Write the message to shared RAM3.

At this time, the processor 1 stores the last written address.

When there is a read request from processor 2, shared RAMm
The stop unit 9 waits for the processor 1 to complete writing, outputs an affirmative response to the processor 2, closes the gate circuit 10,
Open the gate circuit 11.

Then, the processor 2 reads the message, for example one byte at a time, from the shared RAM 3 and passes it to the asynchronous communication control unit 12 for transmission.

This read start address, which changes every time one byte is read, is stored in the read start address storage section 5.

On the other hand, in the processor l, the free space calculation write request sending program 6 stored in the memory 7 reads out the changing read start address from the read start address storage unit 5, and reads out the changing read start address from the read start address storage unit 5, and reads out the final address when the message is written first. The amount of free space in shared RAM3 is calculated by
If the amount exceeds the amount of the message to be written next, a write request is output to the shared RAM arbitration unit 9.

The shared RAM arbitration unit 9 outputs an affirmative response to the processor 1 during the several μs used by the asynchronous communication control unit 12 between when the processor 2 reads one byte and when the next byte is read, and closes the gate circuit 11. , the gate circuit 10 is opened.

In response to this affirmative response, the processor 1 uses the direct memory access unit 8 to write the next message to the shared RAM 3 (the writing time in this case is about 1 μs).

That is, even if the processor 2 does not have to wait until the entire message is read from the shared RAM 3, if the amount of free space in the shared RAM 3 becomes larger than the amount of the message to be written next, the shared RAM
Since data can be written to M3, data transfer efficiency is improved.

〔Effect of the invention〕

As explained in detail above, according to the present invention, when a normal RAM is used as the shared RAM, the amount of free space in the shared RAM 3 can be increased by If the amount of the message is larger than the amount written in the data, the processor 1 can write it to the shared RAM 3, which has the effect of improving data transfer efficiency.

head address memory section, Reference numeral 6 denotes free space calculation write request sending means.

calculation write request sending unit; 7 is memory, 8 is a direct memory access section; 9 is a shared RAM arbitration unit; 10.11 is a gate circuit, Reference numeral 12 indicates an asynchronous communication control section.

Free space

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is an explanatory diagram of the start of writing to the shared RAM in Figure 1, and Figure 3 is a diagram explaining the start of writing to the shared RAM in Figure 1.
The figure is a block diagram when performing start-stop synchronization communication according to an embodiment of the present invention. In the figure, 1.2 is a processor, and 3 is a shared RAM. 4 is a shared RAM arbitration means, 5 is a reading start address storage means, and the reading destination rod 1 is the same as the 7 disasters [2Al-'l's writing 1st woman's words, Yozuki diagram 2 θ

Claims (1)

[Claims] A shared RAM (3) is used, and a shared RAM arbitration means (4) arbitrates the right to use the shared RAM (3) by bus exchange of the shared RAM (3). Processor (1,
2) in a multiprocessor system that transfers data between: a read start address storage means (5) that updates and stores the read start address of the shared RAM (3) each time it is read; and a previously written final address; The amount of free space in the shared RAM (3) is calculated from the start address read from the read start address storage means (5), and compared with the amount of data to be written next, and the amount of free space is determined as the amount of data to be written next. 1. A data transfer system characterized in that a free space calculation write request sending means (6) is provided which sends a write request to the shared RAM arbitration means (4) if the amount is not larger than .