JPH0467809B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a photoelectric switch that can provide a long power-on delay time and a fast response speed.

(Prior art) For example, in a reflective photoelectric switch, the oscillation output of an oscillation circuit is frequency-divided by a frequency dividing circuit, and the frequency-divided output is applied to a light projecting circuit to project the light from the light emitting element toward the detected area. Further, the frequency-divided output is given to the digital integration circuit, and a light reception signal from a light reception circuit that receives reflected light from the object to be detected at the detection part is given to the digital integration circuit. An integrating circuit is provided that is configured to count the frequency-divided output only while the light reception signal is being applied, and output a detection signal when the count value reaches a predetermined value.

By the way, in this type of photoelectric switch,
When the power is turned on, the operation of the light receiving circuit is unstable until the capacitors such as couplings in the light receiving circuit are charged, and in such a state, a detection signal is output from the digital integration circuit based on the light receiving signal from the light receiving circuit. Doing so makes the detection operation uncertain. Therefore, it is necessary to prevent the detection signal from being output for a certain period of time after the power is turned on (power-on delay). For example, it may be possible to obtain the power-on delay time by counting the frequency-divided output with a digital integration counter, but in this case, the division ratio of the frequency divider circuit may be changed to obtain a long power-on delay time. If it is set to a high value, the subsequent response speed will be slow. Conversely, if the frequency division ratio of the frequency divider circuit is set to a small value in order to obtain a fast response speed, a long power-on delay time will be obtained until the light receiving circuit stabilizes. The problem is that there is no.

In order to solve these problems, conventional methods have been to provide a power-on delay circuit with a power-on delay capacitor to ensure a long power-on delay time, or to further divide the frequency-divided output of the frequency divider circuit. A configuration in which an on-delay frequency dividing circuit is provided to restrict the output from an output circuit subsequent to the digital integrating circuit has been considered.

(Problems to be Solved by the Invention) According to the conventional configuration, when making an IC chip, in the former case where a power-on delay circuit is provided, it is necessary to externally attach a power-on delay capacitor; In the latter case, where a frequency divider circuit for power-on delay is provided, it is necessary to secure a large space on the IC chip for the frequency divider circuit for power-on delay. There is a problem of damage.

The present invention has been made in view of the above circumstances, and its purpose is to provide a photoelectric switch that can obtain a long power-on delay time and fast response speed with a simple configuration, has excellent manufacturability, and can be made compact and lightweight. is to provide.

[Structure of the Invention] (Means for Solving the Problems) The photoelectric switch of the present invention includes an oscillation circuit whose oscillation period can be switched in two stages, and a frequency dividing circuit that divides the oscillation output of the oscillation circuit. , a digital integrator circuit is provided to count the frequency divided output of this frequency divider circuit, and when the power is turned on, the oscillation circuit is caused to oscillate at the greater period, and when the digital integrator circuit counts up to a predetermined value, the oscillation circuit is decreased. A power-on delay oscillation cycle adjustment circuit that causes oscillation to oscillate at the cycle of the smaller one is provided, and the light receiving operation or the light emitting operation is controlled by the frequency division output based on the oscillation output of the frequency division circuit that has the smaller cycle. has.

(Function) According to the photoelectric switch of the present invention, a long power-on delay time is obtained based on the oscillation output of the larger period of the oscillation circuit, and a fast response speed is obtained based on the oscillation output of the smaller period. This is what we do.

(Embodiment) An embodiment in which the present invention is applied to a reflective photoelectric switch will be described below with reference to the drawings.

First, the configuration of the oscillation circuit A will be described with reference to FIG. 1 and 2 are power supply terminals to which a DC voltage +V is applied. 3 and 4 are PNP type transistors, 5 is a double emitter type PNP type transistor, and each emitter is connected to power supply terminal 1, and each base is commonly connected so as to form a current mirror circuit. Further, the collector of the transistor 3 is connected to the base and is also connected to the power supply terminal 2 via a resistor 6. Reference numeral 7 denotes an NPN type transistor for state control, the collector of which is connected to the collector of the transistor 4, the emitter connected to the power supply terminal 2, and the base connected to the control terminal 8. 9 and 10 are NPN type transistors for forming a current mirror circuit, and the collector of transistor 9 is connected to transistor 7.
The emitter is connected to the power supply terminal 2, the base is connected to the collector and the base of the transistor 10, and in the transistor 10, the collector is connected to the collector of the transistor 5, The emitter is connected to power terminal 2. 11 and 12 are NPN transistors for forming a current mirror circuit; in the transistor 11, the collector is connected to the collector of the transistor 10, the emitter is connected to the power supply terminal 2, and the base is connected to the collector. The emitter of the transistor 12 is also connected to the power supply terminal 2. The transistors 3 to 5, the resistor 6, and the transistors 7 and 9 to 12 described above constitute a control circuit 13. 14 to 16 are
These are PNP type transistors, and each emitter is connected to the power supply terminal 1, each base is connected in common, and the collector of the transistor 14 is connected to the base so that they form a current mirror circuit. and is connected to the collector of transistor 12. Reference numeral 17 denotes an NPN type transistor for charge/discharge control, the collector of which is connected to the collector of the transistor 15, and the emitter connected to the power supply terminal 2. 18 is
The NPN type transistor 19 is a double emitter type NPN type transistor that forms a current mirror circuit with this transistor 18. In the transistor 18, the collector is connected to the collector of the transistor 17, and the emitter is connected to the power supply terminal 2. , the base is connected to the collector and to the base of the transistor 19, and in the transistor 19,
The collector is connected to the collector of the transistor 16, and the emitter is connected to the power supply terminal 2. The transistors 14 to 19 described above constitute an operating circuit 20. 21 is an oscillation capacitor, one terminal of which is connected to the collector of the transistor 19, and the other terminal connected to the power supply terminal 2. 22 is a waveform shaping circuit whose input terminal I is connected to the collector of the transistor 19, its output terminal Oa is connected to the base of the transistor 17, and its output terminal Ob is the oscillation output terminal 23.
It is connected to the.

Now, with reference to FIG. 1, the overall schematic configuration using this oscillation circuit A will be described. An oscillation pulse, which is an oscillation output signal, from the oscillation output terminal 23 (see FIG. 3) of the oscillation circuit A is applied to the input terminal I of the frequency dividing circuit B. This frequency dividing circuit B divides the oscillation pulse given to the input terminal I into 1/8, for example.
The frequency-divided pulse, which is the frequency-divided output signal, is outputted as a drive pulse from the output terminal Oa and given to the input terminal of the light projecting circuit C via the AND gate U, and the clock pulse is output from the output terminal Ob. output as digital integration circuit D
It is designed to be applied to the clock terminal CK. In this case, the light emitting circuit C causes the light emitting element to emit light every time a driving pulse is applied to the input terminal, and the light emitting element emits the pulse modulated light to the detected part. . E is a light receiving circuit, which has a light receiving element that receives reflected pulse modulated light reflected from the object to be detected at the detection site, and outputs a light receiving signal based on the received light from an output terminal. The signal is applied to an input terminal I of a digital integration circuit D via an OR gate J. In this case, the digital integration circuit D is composed of a counter or a shift register, and is designed to count the clock pulses applied to the clock terminal CK when the light reception signal is continuously applied to the input terminal I. When the count value reaches a predetermined value (for example, "5"), a detection signal is output from the output terminal. The detection signal from the digital integration circuit D is applied to the input terminal of the output circuit F via an AND gate K. This output circuit F is composed of, for example, a transistor, etc., and the detection signal from the digital integration circuit D is input to the input terminal of the AND gate K.
When the transistor is turned on, the ON output signal is output from the output terminal. G is an oscillation period adjustment circuit for power-on delay, which is composed of a flip-flop, the output from the digital integration circuit D is input to the set input terminal S, and the input to the reset input terminal R (initial reset) is set to low level. After the output of the digital integration circuit D becomes high level, the control signal S ₈ output from the output terminal Q is set to low level until the output of the digital integration circuit D becomes high level, and after the output of the digital integration circuit D becomes high level, the control signal S ₈ are now reaching a high level. The control signal _S8 from this oscillation cycle adjustment circuit G is applied to the control terminal 8 of the oscillation circuit A.

Next, the operation of this embodiment will be explained.

First, the oscillation operation of oscillation circuit A will be described with reference to FIGS. 3 to 7. Now, power terminal 1,
Let us consider a case where the control signal _S8 is at a low level when a DC voltage +V is applied between the terminals 2 and 2 (power is turned on). As mentioned above, when the power is turned on, a current i flows between the emitter and the collector of the transistor 3.
and transistor 4 forming a current mirror circuit.
A current i can flow between the emitter and collector of transistor 5, and a current 2i can also flow between the emitter and collector of transistor 5. At this time, the control signal _S8 is at a low level and the state control transistor 7 is off, so the current i flowing between the emitter and the collector of the transistor 4 flows between the collector of the transistor 9 and the collector, as shown in FIG.
Current i now flows between the collector and emitter of transistor 10 forming a current mirror circuit with transistor 9. Therefore, the current 2i between the emitter and collector of transistor 5 is
The current i is divided between each emitter and collector of 1. This allows current i to flow between the collector and emitter of transistor 12 forming a current mirror circuit with transistor 11.
is the current i flowing between the emitter and collector of .
When a current i flows between the emitter and the collector of the transistor 14, the transistor 1 forming a current mirror circuit with the transistor 14
The current i can also flow between the emitters 5 and 16 and the collector. However, waveform shaping circuit 2
The terminal voltage V ₂₁ of the oscillation capacitor 21 is applied to the input terminal I of 2, and the waveform shaping circuit 22 switches charging/discharging from the output terminal Oa when the terminal voltage V ₂₁ reaches the upper limit level. The signal _S22 is set to a low level "L", and when the terminal voltage _V21 reaches the lower limit level, the charge/discharge switching signal _S22 is set to a high level "H". Therefore, when the DC voltage +V is initially applied between the power supply terminals 1 and 2, the terminal voltage V ₂₁ of the oscillation capacitor 21 has not reached the upper limit level, so the waveform shaping circuit 22
As shown in the figure, the charge/discharge switching signal _S22 is set to a high level "H". As a result, the charge/discharge control transistor 17 is turned on, and the transistor 15
The current i flowing between the emitter and collector of transistor 17 now flows between the collector and emitter of transistor 17, and both transistors 18 and 19 are in an off state. As a result, transistor 16
The oscillation capacitor 21 is charged to the illustrated polarity by the current i flowing between the emitter and the collector, and its terminal voltage V ₂₁ rises. Thereafter, when the terminal voltage V ₂₁ of the oscillation capacitor 21 reaches the upper limit level, the charge/discharge switching signal S ₂₂ is switched to the low level "L" as shown in FIG. Turn off. As a result, the emitter of the transistor 15,
The current i flowing between the collectors comes to flow between the collector and emitter of the transistor 18, and a current 2i can flow between the collector and emitter of the transistor 19 forming a current mirror circuit with this transistor 18. Therefore, not only the current i between the emitter and collector of the transistor 16 but also the discharge current of the oscillation capacitor 21 flows between the collector and emitter of the transistor 19, and the oscillation capacitor 21 is discharged and the terminal voltage V ₂₁ will go down. After that, when the terminal voltage V ₂₁ of the oscillation capacitor 21 reaches the lower limit level, the waveform shaping circuit 22 sets the charge/discharge switching signal S ₂₂ to high level "H" and turns on the charge/discharge control transistor 17, so that the oscillation occurs. The capacitor 21 is charged again by the current i flowing between the emitter and collector of the transistor 16. Thereafter, by repeating the same operation, the waveform shaping circuit ₂₂ outputs an oscillation pulse P 23 a, which is an oscillation signal with an oscillation period of 2T, synchronized with the high level "H" and low level "L" of the charge/discharge switching signal S ₂₂ . It will now be output from Ob. Next, consider the case where the control signal _S8 is at a high level "H". In this case, since the state control transistor 7 is turned on, the current i flowing between the emitter and the collector of the transistor 4 flows between the collector and emitter of the state control transistor 7, as shown in FIG. Therefore, no current flows between the collector and emitter of transistor 9, and no current flows between the collector and emitter of transistor 10, which forms a current mirror circuit with transistor 9. As a result, as shown in FIG. 6, the current 2i flowing between the emitter and the collector of the transistor 5 all flows between the collector and the emitter of the transistor 11, and the current 2i flowing between the emitter and the collector of the transistor 14 is twice as large as that previously described. A current of 2i will flow. As a result, a current 2i can flow between the emitters and collectors of transistors 15 and 16 forming a current mirror circuit with transistor 14. As shown in FIG. 6, when the charge/discharge switching signal _S22 is at a high level "H", the current 2i between the emitter and collector of the transistor 15 flows between the collector and emitter of the charge/discharge control transistor 17. , the oscillation capacitor 21 is the transistor 16
will be charged by the current 2i flowing between the emitter and collector of , and its terminal voltage V ₂₁ will rise at twice the rate mentioned above. Thereafter, when the terminal voltage V ₂₁ of the oscillation capacitor 21 reaches the upper limit level, the waveform shaping circuit 22 sets the charge/discharge switching signal S ₂₂ to the low level "L" as shown in FIG. Transistor 17 is turned off, and the current 2i between the emitter and collector of transistor 15 begins to flow between the collector and emitter of transistor 18, and therefore the current 2i between the collector and emitter of transistor 19, which forms a current mirror circuit with transistor 18, flows between the collector and emitter of transistor 18. is in a state where current 4i can flow. As a result, transistor 1
A transistor 16 is installed between the collector and emitter of 9.
Not only the current 2i between the emitter and the collector of the oscillating capacitor 21 but also the discharging current of the oscillating capacitor 21 starts to flow, and the oscillating capacitor 21 is discharged and its terminal voltage V ₂₁ falls at twice the speed mentioned above. Become. As a result, the waveform shaping circuit 22 generates an oscillation pulse.
An oscillation pulse P ₂₃ b with an oscillation period T that is 1/2 of the oscillation period 2T of P ₂₃ a is output from the output terminal Ob.

Now, the overall operation will be described with reference to FIGS. 1 and 2. When the power is turned on, an initial reset is performed at this time, and the power-on delay oscillation cycle adjustment circuit G is also reset, so that the output of the output terminal Q, that is, the control signal _S8 , becomes a low level "L".
It is. As a result, the oscillation circuit A has an oscillation period of 2T.
The frequency dividing circuit B divides _{the frequency of this oscillation pulse P 23 a} . The frequency divided pulse from the output terminal Oa of this frequency dividing circuit B becomes one input of the AND gate U, and the other input of the AND gate U is the control signal _S8 , which is at the low level "L". Therefore, the light projection driving pulse does not enter the light projection circuit C. On the other hand, since the control signal _S8 is low level "L", the OR gate J
The output of is at a high level "H" by the inverter W, which is applied to the input terminal I of the digital integrator circuit D, so that the digital integrator circuit D counts the pulses from the output terminal Oh of the frequency divider circuit B.
After that, when the count value of the digital integration circuit D reaches a predetermined value (for example, "5"), the digital integration circuit D
The output becomes high level "H", and this output goes into the AND gate M and the oscillation period adjustment circuit G.
input to the set input terminal S of the . This output is further applied from the AND gate M to the reset input terminal R of the digital integration circuit D through the OR gate N, which is reset and the control signal _S8 becomes high level. The output pulse from the terminal Oa is output as is, and the light projection driving pulse is input to the light projection circuit C. Further, the OR gate J outputs the output of the light receiving circuit E as it is and inputs it to the input terminal I of the digital integration circuit D. In addition, the control signal _S8 enters the terminal 8 of the oscillation circuit A, and the oscillation circuit A generates an oscillation pulse.
Instead of P ₂₃ a, the oscillation period T is 1/2 of the oscillation period 2T.
The oscillation pulse P ₂₃ b is now output. Therefore, in frequency dividing circuit B, this oscillation pulse
_P23b is frequency-divided and the frequency-divided pulse is applied to the light projection circuit C as a drive pulse and to the digital integration circuit D as a clock pulse.

The reason for switching from the oscillation pulse P ₂₃ a to the oscillation pulse P ₂₃ b in the oscillation circuit A as described above is as follows.

The response speed of the photoelectric switch with the configuration shown in FIG.
It is determined by the count setting value (for example, "5") of the digital integration circuit D. For example, if the period of the oscillation pulse from the oscillation circuit A is T, the period of the output pulse from the divided output terminal Ob of the frequency dividing circuit B is 8T, and the count setting value of the digital integration circuit D is "5", the response time is It is 8T×5. On the other hand, when the power is turned on, the operation of the light receiving circuit E is unstable until the capacitors such as couplings in the light receiving circuit E are charged. If it is output, the detection operation becomes uncertain. Therefore, the detection signal is not output for a certain period of time after the power is turned on (power-on delay). In Figure 2, the power-on delay time is determined by the output terminal of frequency divider circuit B.
This is the product of the pulse period t from Ob and the count setting value "5" of the digital integration circuit D, that is, 5t. Here, assuming that the output pulse of oscillation circuit A is constant with a period of 2T, t = 8 × 2T, the power-on delay time is 8 × 5 × 2T, and the response speed is also 8 × 5 × 2T.
becomes.

By the way, if the oscillation period T is shortened in advance in order to obtain a fast response speed, the power-on delay time will also be shortened, making it impossible to take time for the light receiving circuit E to stabilize. Therefore, as in this embodiment, the oscillation circuit A is configured to output an oscillation pulse with a period of 2T when the control signal _S8 is at a low level, and output an oscillation pulse with a period of T when the control signal _S8 is at a high level. Then, the power-on delay time becomes 8 x 5 x 2T, and the response speed becomes 8 x 5T, so the response speed remains unchanged and the power-on delay time is doubled. That is, a long power-on delay time and a fast response speed can be obtained.

As described above, according to this embodiment, the oscillation output is divided into two oscillation pulses P ₂₃ a and P ₂₃ b having different oscillation periods by changing the state of the control signal S ₈ from low level “L” to high level “H”. An oscillation circuit A that switches between stages is provided, and an oscillation cycle adjustment circuit G for power-on delay that changes the state of the control signal _S8 given to the oscillation circuit A from low level "L" to high level "H". , it is possible to obtain a long power-on delay time and a fast response speed with a simple configuration. Therefore, even when integrated into an IC chip, the oscillation cycle adjustment circuit G for power-on delay consisting of a flip-flop on the IC chip can be used.
Unlike conventional power-on-delay circuits, there is no need to externally attach a power-on-delay capacitor, and unlike conventional power-on-delay frequency divider circuits, the oscillation cycle adjustment circuit G It is not necessary to secure a large space on the IC chip, which makes it easier to manufacture and allows for smaller size and lighter weight.

Moreover, according to this embodiment, the control signal
By changing the state of _S8 to low level "L" and high level "H", one oscillation capacitor 2
Since the oscillation circuit A is provided which can switch the oscillation period into two stages by simply using 1, the oscillation period is reduced compared to the case where, for example, two oscillation capacitors and a changeover switch to select between them are provided in order to switch the oscillation period into two stages. However, the oscillation circuit A itself has excellent manufacturability and can be made smaller and lighter, so the photoelectric switch as a whole can be made smaller and lighter.

In the above embodiment, a resistor or a variable resistor may be connected between the emitter of the transistor 9 and the power supply terminal 2 to control the power supply.

Further, although the above embodiment is a case in which the present invention is applied to a reflective photoelectric switch, the present invention may be applied to other photoelectric switches. It can also be applied to control only one side.

As a precaution, the reflective photoelectric switch itself can function satisfactorily not only with the oscillation circuit A, but also with any oscillation circuit whose oscillation period can be switched in two stages.

[Effects of the Invention] As explained above, the photoelectric switch of the present invention has the following effects:
An oscillation circuit whose oscillation cycle can be switched in two stages is provided, and an oscillation cycle adjustment circuit for power-on delay is provided which switches the oscillation cycle in response to power-on and the count value of the digital integration circuit. The power-on delay time and fast response speed can be obtained, and the device has excellent manufacturability and can be made smaller and lighter.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and Fig. 1 is a block diagram showing the overall configuration, Fig. 2 is a signal waveform diagram of each part, Fig. 3 is a wiring diagram of the oscillation circuit, and Figs. 4 to 7. The figure is a diagram corresponding to Figure 3 for explaining the operation. In the drawing, A is an oscillation circuit, B is a frequency dividing circuit, C is a light emitter circuit, D is a digital integration circuit, E is a light receiving circuit,
F indicates an output circuit, and G indicates an oscillation cycle adjustment circuit for power-on delay.

Claims (1)

[Claims] 1. An oscillation circuit whose oscillation period is switched in two stages, a frequency divider circuit that divides the oscillation output of this oscillation circuit, a digital integration circuit that counts the divided output of this frequency divider circuit, and an oscillation cycle adjustment circuit for power-on delay that causes the oscillation circuit to oscillate at the larger cycle and, when the digital integration circuit counts up to a predetermined value, causes the oscillation circuit to oscillate at the smaller cycle; A photoelectric switch configured to control a light receiving operation or a light emitting operation by a frequency-divided output based on the oscillation output of the smaller period.