JPH0467811U - - Google Patents
Info
- Publication number
- JPH0467811U JPH0467811U JP11049790U JP11049790U JPH0467811U JP H0467811 U JPH0467811 U JP H0467811U JP 11049790 U JP11049790 U JP 11049790U JP 11049790 U JP11049790 U JP 11049790U JP H0467811 U JPH0467811 U JP H0467811U
- Authority
- JP
- Japan
- Prior art keywords
- log
- amplifier
- output
- log amplifier
- hysteresis comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は本考案の一実施例の構成を示す説明図
、第２図は本考案の具体的実施例の動作を示す説
明図、第３図は従来の逐次加算形のログアンプの
一例の構成を示す説明図である。
１……信号入力端子、２……単一リミツタアン
プ、３……単一ログアンプ、４……出力合成回路
、５……ログ変換出力端子、６……抵抗、７……
リミツタアンプ出力端子、８……ヒステリシスコ
ンパレータ、９……電圧源、１０……減衰器、１
１……レベルシフト回路。なお図中同一符号は同
一または相当するものを示す。
Fig. 1 is an explanatory diagram showing the configuration of an embodiment of the present invention, Fig. 2 is an explanatory diagram showing the operation of a specific embodiment of the invention, and Fig. 3 is an example of a conventional successive addition type log amplifier. FIG. 2 is an explanatory diagram showing the configuration. 1... Signal input terminal, 2... Single limiter amplifier, 3... Single log amplifier, 4... Output synthesis circuit, 5... Log conversion output terminal, 6... Resistor, 7...
Limiter amplifier output terminal, 8... Hysteresis comparator, 9... Voltage source, 10... Attenuator, 1
1...Level shift circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
リーズ接続され、各単一ログアンプの出力電流が
出力合成回路によつて合成され、該出力合成回路
の出力が抵抗によつて電流電圧変換されて出力さ
れる構成の逐次加算形のログアンプにおいて、 該ログアンプのログ出力電圧の飽和領域への到
達を検出するヒステリシスコンパレータと、 該ログアンプのログ出力電圧が飽和領域に到達
すると、上記ヒステリシスコンパレータに連動し
て入力信号を減衰させる減衰器と、 上記減衰器が入力信号を減衰させると同時に、
上記ヒステリシスコンパレータに連動して該ログ
アンプのログ出力電圧に対して上記減衰器の減衰
量に相当するレベルシフトを行なうレベルシフト
回路とを備えたことを特徴とするログアンプ。 (2) 上記ヒステリシスコンパレータのヒステリ
シス電圧幅と上記減衰器の減衰量との和と同等な
ログアンプ出力電圧をヒステリシスコンパレータ
のコンパレートレベル以下に設定し、コンパレー
トレベルはログアンプのダイナミツクレンジ以下
に設定することを特徴とする上記請求項第１項記
載のログアンプ。[Claims for Utility Model Registration] (1) A single limiter amplifier and a single log amplifier are connected in series, the output currents of each single log amplifier are combined by an output combining circuit, and the output of the output combining circuit is connected to a resistor. In a successive addition type log amplifier configured to convert current to voltage and output it, the log amplifier includes a hysteresis comparator that detects when the log output voltage of the log amplifier reaches a saturation region, and a hysteresis comparator that detects when the log output voltage of the log amplifier reaches saturation. an attenuator that attenuates the input signal in conjunction with the hysteresis comparator when the region is reached; and at the same time, the attenuator attenuates the input signal.
A log amplifier comprising: a level shift circuit that performs a level shift corresponding to the attenuation amount of the attenuator with respect to the log output voltage of the log amplifier in conjunction with the hysteresis comparator. (2) Set the log amp output voltage, which is equivalent to the sum of the hysteresis voltage width of the hysteresis comparator and the attenuation amount of the attenuator, below the comparator level of the hysteresis comparator, and set the comparator level below the log amp's dynamic range. 2. The log amplifier according to claim 1, wherein the log amplifier is set to .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990110497U JP2520011Y2 (en) | 1990-10-24 | 1990-10-24 | Log amp |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990110497U JP2520011Y2 (en) | 1990-10-24 | 1990-10-24 | Log amp |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0467811U true JPH0467811U (en) | 1992-06-16 |
| JP2520011Y2 JP2520011Y2 (en) | 1996-12-11 |
Family
ID=31857834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990110497U Expired - Fee Related JP2520011Y2 (en) | 1990-10-24 | 1990-10-24 | Log amp |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2520011Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5732113A (en) * | 1980-08-04 | 1982-02-20 | Advantest Corp | Logarithmic amplifier |
| JPS62101109A (en) * | 1985-10-28 | 1987-05-11 | Mitsubishi Electric Corp | logarithmic amplifier |
-
1990
- 1990-10-24 JP JP1990110497U patent/JP2520011Y2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5732113A (en) * | 1980-08-04 | 1982-02-20 | Advantest Corp | Logarithmic amplifier |
| JPS62101109A (en) * | 1985-10-28 | 1987-05-11 | Mitsubishi Electric Corp | logarithmic amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2520011Y2 (en) | 1996-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |