JPS62201869U - - Google Patents
Info
- Publication number
- JPS62201869U JPS62201869U JP8852686U JP8852686U JPS62201869U JP S62201869 U JPS62201869 U JP S62201869U JP 8852686 U JP8852686 U JP 8852686U JP 8852686 U JP8852686 U JP 8852686U JP S62201869 U JPS62201869 U JP S62201869U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- inverting input
- operational amplifier
- voltage
- bias current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Networks Using Active Elements (AREA)
Description
第１図は本考案の一実施例の回路構成を示す回
路図、第２図は従来例の回路構成を示す回路図で
ある。
ＯＰ１……積分用演算増幅器、ＯＰ２……入力
電流補償用演算増幅器、Ｒ……入力抵抗、Ｃ……
積分コンデンサ、Ｒｂｆ……電流―電圧変換器を
構成する抵抗、ＲＬ……負荷抵抗。
FIG. 1 is a circuit diagram showing the circuit configuration of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the circuit configuration of a conventional example. OP1...Operational amplifier for integration, OP2...Operation amplifier for input current compensation, R...Input resistance, C...
Integrating capacitor, R bf ...Resistance that constitutes the current-voltage converter, RL...Load resistance.
Claims (1)
抵抗を介して接続された入力端子と、前記演算増
幅器の反転入力端子と出力端子との間に接続され
た積分コンデンサとを有する積分回路において、
前記演算増幅器の非反転入力端子に接続された入
力端子と、前記反転入力端子に負荷抵抗を介して
接続された出力端子とを有し、前記非反転入力端
子からのバイアス電流を検出して電圧に変換し、
その変換電圧に応じて、前記負荷抵抗を介して前
記反転入力端子のバイアス電流を減算する電流―
電圧変換器を具えたことを特徴とする積分回路。 An integrating circuit having an operational amplifier, an input terminal connected to an inverting input terminal of the operational amplifier via a resistor, and an integrating capacitor connected between the inverting input terminal and the output terminal of the operational amplifier,
The operational amplifier has an input terminal connected to a non-inverting input terminal, and an output terminal connected to the inverting input terminal via a load resistor, and detects a bias current from the non-inverting input terminal to generate a voltage. Convert to
A current that subtracts the bias current of the inverting input terminal through the load resistor according to the converted voltage.
An integrating circuit characterized by being equipped with a voltage converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8852686U JPH054049Y2 (en) | 1986-06-12 | 1986-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8852686U JPH054049Y2 (en) | 1986-06-12 | 1986-06-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62201869U true JPS62201869U (en) | 1987-12-23 |
| JPH054049Y2 JPH054049Y2 (en) | 1993-02-01 |
Family
ID=30946697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8852686U Expired - Lifetime JPH054049Y2 (en) | 1986-06-12 | 1986-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH054049Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081537A (en) * | 2007-09-25 | 2009-04-16 | New Japan Radio Co Ltd | Semiconductor device |
-
1986
- 1986-06-12 JP JP8852686U patent/JPH054049Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009081537A (en) * | 2007-09-25 | 2009-04-16 | New Japan Radio Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH054049Y2 (en) | 1993-02-01 |