JPH0467820U - - Google Patents

Info

Publication number
JPH0467820U
JPH0467820U JP1990110987U JP11098790U JPH0467820U JP H0467820 U JPH0467820 U JP H0467820U JP 1990110987 U JP1990110987 U JP 1990110987U JP 11098790 U JP11098790 U JP 11098790U JP H0467820 U JPH0467820 U JP H0467820U
Authority
JP
Japan
Prior art keywords
signal
output
delay
delay element
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990110987U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990110987U priority Critical patent/JPH0467820U/ja
Publication of JPH0467820U publication Critical patent/JPH0467820U/ja
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図で
ある。 1……入力端子、2……遅延回路、3……設定
端子、4……選択回路、5……出力端子。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Input terminal, 2...Delay circuit, 3...Setting terminal, 4...Selection circuit, 5...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 被遅延信号を入力する信号入力端子と、個々に
所定の遅延時間を有する遅延素子を複数直接に接
続し且つ遅延素子個々の出力タツプを備えた遅延
素子群と、この遅延素子群の出力タツプを選択し
その選択信号波形を整形する選択回路と、この選
択回路を制御する制御信号を入力する設定端子と
、出力端子とを有し、前記設定端子に入力する前
記制御信号の指示により前記遅延素子群の所定の
出力タツプを選択して、前記入力端子に入力する
入力信号を所定の時間遅延したのち波形整形して
前記出力端子に出力することを特徴とする遅延回
路。
A signal input terminal for inputting a delayed signal, a delay element group in which a plurality of delay elements each having a predetermined delay time are directly connected and each delay element has an output tap, and an output tap of this delay element group. It has a selection circuit that selects and shapes the selection signal waveform, a setting terminal that inputs a control signal to control the selection circuit, and an output terminal, and the delay element 1. A delay circuit characterized in that a predetermined output tap of a group is selected, an input signal input to the input terminal is delayed by a predetermined time, the waveform is shaped, and the signal is output to the output terminal.
JP1990110987U 1990-10-23 1990-10-23 Pending JPH0467820U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990110987U JPH0467820U (en) 1990-10-23 1990-10-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990110987U JPH0467820U (en) 1990-10-23 1990-10-23

Publications (1)

Publication Number Publication Date
JPH0467820U true JPH0467820U (en) 1992-06-16

Family

ID=31858398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990110987U Pending JPH0467820U (en) 1990-10-23 1990-10-23

Country Status (1)

Country Link
JP (1) JPH0467820U (en)

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