JPH0468532U - - Google Patents
Info
- Publication number
- JPH0468532U JPH0468532U JP11151690U JP11151690U JPH0468532U JP H0468532 U JPH0468532 U JP H0468532U JP 11151690 U JP11151690 U JP 11151690U JP 11151690 U JP11151690 U JP 11151690U JP H0468532 U JPH0468532 U JP H0468532U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit device
- socket
- jacks
- attached
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図ａ及びｂは本考案の一実施例を示す集積
回路装置測定用治具の上面図及び側面図、第２図
及び第３図は第１図の集積回路装置測定治具の分
解したときの斜視図及び平面図、第４図ａ及びｂ
は従来の集積回路装置測定用治具の一例を示す上
面図及び側面図である。
１……ソケツト、２……端子台、３，３ａ……
絶縁基板、４……測定用パツド、５……取付板、
６ａ〜６ｄ……スイツチ、７……コネクタ、７ａ
……接触部、８……ピラー、９……ジヤツク、９
ａ……導電部、１０……止めねじ、１１……位置
決め穴。
1A and 1B are top and side views of a jig for measuring an integrated circuit device showing an embodiment of the present invention, and FIGS. 2 and 3 are an exploded view of the jig for measuring an integrated circuit device shown in FIG. Perspective view and plan view, Figures 4a and b
1A and 1B are a top view and a side view showing an example of a conventional integrated circuit device measuring jig. 1...Socket, 2...Terminal block, 3, 3a...
Insulating board, 4... measurement pad, 5... mounting plate,
6a to 6d...Switch, 7...Connector, 7a
...Contact part, 8...Pillar, 9...Jack, 9
a... Conductive part, 10... Set screw, 11... Positioning hole.
Claims (1)
れているとともにこれらの測定用パツドのそれぞ
れにに配線を介して接続される導電接触部をもつ
複数のコネクタが取り付けられる絶縁基板と、前
記コネクタのそれぞれに挿入されるジヤツクと、
これらジヤツクをその裏面に取り付けるとともに
これらジヤツクに対応する集積回路装置装填用の
ソケツトがその表面に取り付けられる取付板と、
前記ソケツトと前記ジヤツクとの配線を断通させ
るスイツチとを有することを特徴とする集積回路
装置測定用治具。 an insulating substrate having a plurality of measurement pads formed at equal intervals on its periphery and a plurality of connectors each having a conductive contact portion connected to each of the measurement pads via wiring; a jack inserted into each of the
a mounting plate to which the jacks are attached to the back side thereof and a socket for loading the integrated circuit device corresponding to the jacks is attached to the front surface thereof;
A jig for measuring an integrated circuit device, comprising a switch that disconnects wiring between the socket and the jack.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11151690U JPH0468532U (en) | 1990-10-24 | 1990-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11151690U JPH0468532U (en) | 1990-10-24 | 1990-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0468532U true JPH0468532U (en) | 1992-06-17 |
Family
ID=31858979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11151690U Pending JPH0468532U (en) | 1990-10-24 | 1990-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0468532U (en) |
-
1990
- 1990-10-24 JP JP11151690U patent/JPH0468532U/ja active Pending
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