JPH0468705B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a circuit for controlling the position of a transducer head for reading and writing information in a disk storage device represented by a so-called fixed disk device, and more specifically, a circuit for controlling the position of a transducer head for reading and writing information in a disk storage device represented by a so-called fixed disk device. A plurality of areas are set in which reference information for detecting the position of the transducer head that reads and writes information is recorded, and as the reference information, a group of repetitive patterns that are shifted from each other between adjacent areas is set. The present invention relates to a head position control circuit for a disk storage device which detects and controls the position of a head based on a pair of reference information signals recorded and sequentially read out from a pair of adjacent areas via the head.

[Prior art and its problems]

As is well known, a disk storage device includes a plurality of disks or a single disk as an information storage medium, and this disk is rotated by a motor at a high speed of several thousand rpm in a fixed disk device. On both sides of the disk, dozens to hundreds of tracks for recording information are set concentrically. The head for writing information to or reading information from this track is one for each disk surface, and is positioned on one of the plurality of tracks each time reading or writing, and in principle, the head is is positioned so that it is in the center of the As technology advances, efforts are being made to reduce the diameter of disks and increase their storage density in order to make disk storage devices more compact and capable of storing a larger amount of information. Conventionally, when the storage density is relatively low, open loop control has been adopted for positioning the above-mentioned heads. In this control method, only a predetermined number of pulse commands are issued to the actuator, such as a pulse motor, that drives the head so that the head comes to the specified track number position, and the current position of the head is not detected at all. Therefore, no fine adjustment of the head position is performed. However, such an open loop control system is limited to 500 TPI (tracks per inch) for a fixed disk with a diameter of 5.25 inches. As track densities become even higher, exceeding 700 TPI, it becomes necessary to employ closed-loop control for head positioning. In order to carry out such control, it is of course necessary to accurately detect the position of the head, and various inventions and devices have been made for this purpose. Information, so-called servo information, is written in advance, this reference information is read out by the head itself whose position is to be detected, and the read signal is processed to determine the head position. The present case also relates to a head position control circuit for a disk storage device based on this principle. However, many of the conventional technologies, for example,
In the technology described in No. 99709 and others, the pattern of reference information written in advance on the disk is devised, and when detecting the position of the head, it is necessary to accurately process the read signal indicating this special pattern in an analog manner. Therefore, it is generally necessary to employ a complex and high-grade circuit for the signal processing circuit. Furthermore, since the pattern of reference information has a certain meaning, it is necessary to write it to the disk very accurately. Examples of such prior art will be briefly explained with reference to FIGS. 4 to 6. FIG. 4 is a side view of the main parts of the fixed disk device, and in the figure, two disks 1 are attached to the spindle shaft 1.
a, and is driven at high speed by a spindle motor 1b. On each surface of the disk 1, as shown in FIG. 5, a large number of concentric annular areas for the tracks 2 are set. A sector-shaped area is set in a part of the area. As seen in FIG. 4, each side of the disk 1 is provided with transducer heads 4 for reading and writing information, and these heads 4
are each carried on a movable carriage 5 via a head arm 4a. This carriage 5 is guided to a fixed part by guide elements 5a, and the actuator 6 is guided by a thin metal band 5b.
The carriage 5 and, therefore, the head 4 carried thereon are driven or position controlled through the drive so as to move forward or backward in the direction indicated by the arrow P in the figure. The reference information 3 in the prior art described above has a pattern as shown in FIG. is used. Both reference information 3a and 3b are magnetically recorded by repeating S and N from left to right in the figure, and when the disk 1 moves in the direction of arrow Q in the figure, at the center m between the starting end l and the ending end n. , both reference information 3a and 3b move from N to S at the same time, but
On both sides of the reference information, the points from S to N are shifted from each other. First, when the head 4 is at the normal position P0 with respect to the track 2b, the readout signal of the reference information 3 from the head 4 includes:
The read signals of both reference information 3a and reference information 3b are included. In this case, when the center m passes under the head 4, both reference information 3a and 3b move from N to S at the same time, so both reference information 3a and 3
The read signals b have the same direction, for example, negative polarity, and are added to each other. However, when both sides pass under the head 4, both reference information 3a, 3
Since b moves from S to N, its read signal has a positive polarity opposite to the previous one, and since the places where it moves from S to N are shifted from each other, the read signal of both reference information 3a and 3b has the positive polarity. occur at different times from each other. Therefore, from the readout signal from the reference information 3 from the head 4, the positive polarity readout signals from both the reference information 3a and 3b are temporally distinguished from each other and separated using the negative polarity signal at the center m as a reference. , the peak values of both the separated signals can be detected in an analog manner. As can be easily seen, when the head 4 is at the normal position P0, the separated read signals of both reference information 3a and 3b have equal peak values. However, if the head 4 deviates even slightly from this normal position P0, this balance will be disrupted. For example, if the head 4 is at a position P1 that is deviated above the normal position P0 by half the pitch between tracks, the reference information 3 The readout signal for the reference information 3 includes only the signal from the reference information 3a, and conversely, when the head 4 is located at the position P2 shifted downward in the figure by the same amount, the readout signal for the reference information 3 includes only the signal from the reference information 3b. It turns out. In this way,
The two pieces of reference information 3a and 3b contained in the readout signal of the reference information 3 are separated from each other, and the deviation from the normal position P0 of the head 4, that is, the off-track amount, is detected from the magnitude relationship of their peak values. It is possible to further correct the amount of deviation to zero, but this requires accurate analog evaluation of the peak value of the signal, which inevitably makes the circuit more complicated and expensive.
A circuit for mutually separating both reference information 3a and 3b is also required. Therefore, the inventor of the present invention proposed in a previous application a head position detection method that does not have such problems. Next, an overview of this method and its problems will be explained with reference to FIGS. 7 and 8. FIG. 7 shows reference information 3 of a different pattern from the previous one in FIG. 6, and parts that functionally correspond to those in FIG. 6 are given the same reference numerals. As in the case of Fig. 6, two pieces of reference information 3a and 3b are written to the track 2b shown in the center, but unlike before, each reference information 3a and 3b is written as shown by the striped pattern in the figure. The tracks are composed of simple repeating patterns and are written offset from each other in the longitudinal direction Q of the track. Therefore, both reference information 3a, 3 from the head 4
The readout signal b is a simple repetitive signal of positive and negative pulse-like signals as shown enlarged in the horizontal direction on the right side of FIG. 8a, and both reference information 3a and 3b
The readout signals RS occur in periods separated from each other in terms of time, as shown by periods Ta and Tb in FIG. However, in Figure 8a, head 4
is at the normal position P0 with respect to the track 2b. Therefore, the height of the repetitive pulse in the readout signal of both the reference information 3a and 3b is equal to the height of the repetitive pulse in both periods Ta and Tb.
shall have the same value for The reference signal RP shown in FIG. 8b is, for example, a so-called index pulse, and reference information 3 is normally written from its starting end l in synchronization with this reference signal RP. Threshold signal shown in figure c
TS is a triangular wave-like signal generated in synchronization with this reference signal RP, and its instantaneous value provides a threshold value that changes over time, and the peak value of each pulse signal in the readout signal RS mentioned above is is compared to this threshold. As a result of this comparison, as shown in Figure d, only the pulse signal whose peak value exceeds the threshold value in the readout signal RS is the count pulse CP.
is extracted as. As can be easily seen, when the head 4 is at the normal position P0, this count pulse corresponding to both the reference information 3a and 3b mentioned above is
The numbers na and nb of CPs are equal to each other. However, when the head 4 is located at a position P1 which is deviated from the normal position P0 in FIG.
As shown in Figure e, the peak value of the pulse in the read signal RSa from the reference information 3a becomes larger than the peak value of the pulse in the read signal RSb corresponding to the reference information 3b, and is compared with the threshold signal TS. The numbers na and nb of count pulses CPa and CPb corresponding to both the reference information 3a and 3b, respectively, are different from each other, and when the head 4 is at the position P1 shifted upward, na>nb. Similarly, when head 4 is at position P2, which is displaced downward, na<nb
becomes. In this way, both reference information 3a, 3b
The number na of count pulses CPa and CPb corresponding to
The amount and direction of deviation of the head 4 from the normal position P0 can be detected from the difference na-nb of nb. In this newly proposed head position detection method, the peak value of the pulse signal in the readout signal RS is handled in an analog manner, but the threshold value signal TS
The count pulse CP after being compared with
Since it can be processed by a digital circuit, the circuit configuration is simpler and its operation is more reliable than in the case of the method shown in FIG. 6 before signal processing. In addition, count pulses corresponding to both reference signals 3a and 3b
Since CPa and CPb occur clearly temporally separated from each other, a signal separation circuit is not required. Furthermore, since both signal information 3a and 3b may be simple repeating patterns, there is an advantage that writing is easy and there are few errors. As mentioned above, the new proposed method has excellent advantages in principle that are not found in the conventional technology, but when it is put into practical use, there are unexpected problems, which are based on the threshold signal TS. It was found that this was caused by the fact that the signal was generated in synchronization with the signal RP. As mentioned above, reference signal 3 is written in synchronization with reference signal RS, so threshold signal TS is also written in synchronization with reference signal RS.
In principle, it should be possible to synchronize with RP, but in reality, the reference signal RP itself may become out of synchronization with the starting edge l of the reference signal 3. That is,
While the reference information 3 is written on the disk 1, the reference signal RS such as the well-known index pulse is usually generated from the spindle motor 1b that rotates the disk 1, so it is not affected by changes in ambient temperature or aging. Therefore, the reference signal RP1 may actually be issued at a timing different from the timing of the reference signal RS when the reference information 3 is written, as shown in FIG. 8b. This reference signal RP
Although the temporal variation tv in the timing of occurrence of 1 is small, it affects the aforementioned count pulses CPa and CPb, causing their numbers na and nb to vary, thereby reducing the detection accuracy of the head position. FIG. 8g shows the threshold signal TS that is generated in synchronization with the reference signal RP1 when it is generated with a delay of time tv from the normal timing.
Figure h shows a comparison between the reference information read signals RSa, RSb and this delayed threshold signal TS when the head 4 is at the normal position P0. The count pulses CPa and CPb as a result of this comparison are shown in Figure i, and their numbers na and nb should originally be equal to each other, but in reality na > nb
I'm getting used to it. Of course, all of these problems are caused by the fact that the reference signal RP is generated from a place other than disk 1, so it is recommended to write other reference information for generating the reference signal RP on disk 1. This problem can be solved by writing the reference information to the reference information 3 or track 2 written on the same disk 1, which consumes the recording area on disk 1. It becomes necessary to distinguish this from other data information, etc., which goes against the simplification of the circuit configuration.

[Purpose of the invention]

An object of the present invention is to determine the head position of a disk storage device so that even if the timing of generation of a reference signal deviates from the timing when reference information is written, the detection accuracy of the head position will not be affected by this. The purpose is to obtain a control circuit.

[Key points of the invention]

According to the present invention, the above object is to record a plurality of information recording tracks on the storage medium disk mentioned at the beginning and a plurality of reference information for detecting the position of a transducer head for reading and writing information on the tracks. A group of repetitive patterns that are mutually shifted between adjacent areas is recorded as the reference information, and a pair of patterns are sequentially read out from the adjacent pair of areas via the head. a threshold signal generation circuit that generates a ramp-shaped threshold signal that changes over time to a head position control circuit of a disk storage device that detects and controls the position of the head based on a reference information signal; a synchronization circuit that generates a synchronization signal that starts the operation of the threshold signal generation circuit based on a reference signal that is generated in synchronization with the rotation of the disk; a comparator circuit that generates a count pulse for counting the number of repetitive pattern signals in the reference signal that cross the threshold by comparison; A position deviation detection circuit is provided which detects the amount of deviation from the normal position of the head with respect to the track from the difference in numerical values, and the synchronization circuit issues a synchronization signal at a timing later than the starting edge timing of the reference information signal, thereby detecting the synchronization. This is achieved by making the threshold generation circuit which receives the reference information signal generate a threshold signal having a time width shorter than the time from the start to the end of the reference information signal.

[Embodiments of the invention]

Hereinafter, in describing embodiments of the circuit of the present invention with reference to the drawings, first the outline of the configuration and its operation will be described with reference to FIGS. 1 and 2. FIG. 1 is a basic configuration diagram of the circuit of the present invention, in which parts common to the above-mentioned prior art illustration are given the same reference numerals. In the figure, the main parts of the disk 1 driven at a constant speed by the spindle motor 1b are shown in an expanded form. However, as is known, writing may be repeated over the entire circumference of a surface of the disk 1 that is different from the surface on which the track 2 is set. Reference information 3 is similar to that shown in FIG. 7, in which the areas for adjacent reference information are shifted from each other in the longitudinal direction of the track, and one area has a repeating pattern about 100 times. It is written and recorded repeatedly. This reference information 3 synchronizes its start end 1 with a reference signal RP such as a so-called index pulse generated in synchronization with the rotation of the spindle motor 1b by means such as a Hall element 1c that detects the position of the rotor. and is written by head 4. The head 4 for reading out the reference information 3 written in this manner is driven forward and backward in the radial direction of the disk by an actuator 6 as shown by an arrow P. As is well known, the actuator 6 is, for example, a two-phase or more multi-phase pulse motor, and is simply shown in the figure by a rotor 6a and two-phase stator coils 6b, 6c. When the drive circuit 6d receives the so-called seek signal SK, it operates as a pulse motor and outputs the seek signal SK.
The head 4 is driven to the approximate position of the track 2 designated by the control signal CS.
When received, it operates as a kind of torque motor and can finely adjust the position of the head 4 to a position determined by the ratio of the current values supplied to the two stator coils 6b and 6c. The control circuit 8 that supplies the seek signal SK or control signal CS to the drive circuit 6d of the actuator 6 is, for example, a microcomputer. In order to determine the amount and direction of fine adjustment of the position of the upper head 4, reference information 3 is read out via the head 4, and the read signal is sent to the amplifier 7.
The reference information RS is amplified by the reference information RS, which includes a large number of pulse signals as described above. In Figure 2a,
Reference signal when head 4 is at normal position P0
RS is shown separately as two pieces of reference information RSa and RSb corresponding to two pieces of reference information 3a and 3b, respectively. The threshold signal generating circuit 10 indicated by a block in FIG. The signal TS is generated in synchronization with the synchronization signal SS from the synchronization circuit 20 shown on the left. The synchronization circuit 20 receives the aforementioned reference signal.
In response to receiving RP, this synchronizing signal SS is emitted, but instead of immediately emitting this synchronizing signal SS based on the reference signal RP shown in Fig. 2b, it is shown in Fig. 2c.
As shown in the figure, the synchronization signal SS is generated so that it rises a short time td later than the reference signal RP. Therefore, the threshold signal generation circuit 10 generates the small delay time td from the reference signal RP as shown in FIG.
After that, a threshold signal TS is generated, and a comparison circuit 30 shown on the right side compares the pulse signal in the reference signal RS mentioned above with this threshold signal TS, so that the peak value of the former is equal to the peak value of the latter. A count pulse CP is generated when the value is exceeded. In FIG. 2f, the count pulse CP resulting from this comparison is shown divided into two parts CPa and CPb corresponding to the reference information 3a and 3b, respectively. At this time, the time width Tt of the threshold signal TS generated by the threshold signal generation circuit 10 is
As can be seen from Figure 2, the starting point l of the reference signal RS
The time Tr from n to terminal n is selected to be shorter than the time Tr.
More precisely, as can be seen from FIG.
The time width of the threshold signal TS is set to be sufficiently short so that there is no delay beyond the terminal n of the threshold signal TS. If this is done, the respective numbers na and nb of count pulses CPa and CPb shown in Fig. 2f will be:
When the head 4 is at the normal position P0 as shown in FIG.
The number of pulses of count pulses CPa and CPb shown in
na and nb are equal to each other. Next, considering the case where the reference pulse RP is shifted from the starting edge l of the reference information 3 by a variation time tv, as shown in Fig. 2g, and is generated with a delay in the figure, the threshold signal TS is As shown in , the threshold signal TS is generated after a delay time td, but in this case as well, the threshold signal is The time width Tt of TS is selected. As can be easily seen from the figure, this condition can be expressed as Tt≦Tr−tv−td. As long as this condition is satisfied, the count pulses CPa and CPb shown in Figure i
The respective pulse numbers na and nb are equal to each other.
Furthermore, in FIG. 2k, the position of the head 4 deviates from its normal position P0 and is at the position P2 in FIG. reference signal RSa,
Waveforms of RSb and threshold signal TS are shown.
As can be seen in the figure, the threshold signal
TS is generated with a delay time Td behind the reference signal RP, but if it is selected so that td≧tv,
The starting edge of the threshold signal TS is never earlier than the starting edge l of the reference signal RS, and therefore the number of pulses of the count pulses CPa and CPb shown in FIG. It won't affect you. As can be seen from the above explanation, even if the generation timing of the reference signal RP fluctuates by the time tv before and after the starting edge l of the reference signal RS, the threshold signal TS
The time that satisfies the relationship td≧tv than the reference signal RP
Delay by td and time width of threshold signal TS
If Tt is selected to satisfy the relationship Tt≦Tr−tv−td, the number of pulses of count pulses CPa and CPb
Since na and nb are not affected, the difference na-nb between them, that is, the deviation of the head 4 from the position P0, can be accurately detected. Returning to FIG. 1, the positional deviation detection circuit 40 detects the difference na-nb between the pulses na and nb of the count pulses CPa and CPb described above. The circuit 40 generates both count pulses CPa, which are generated separately from each other over time.
It is sufficient that the circuit can detect the difference na-nb in the number of pulses from CPb, but the simplest circuit can be configured with one up-down counter circuit as shown in the figure. In this case, the positional deviation detection circuit 40 receives a count pulse CP at its count input terminal C, and its count mode is switched by signals applied to two mode designation inputs U and D. In this example, the count-up mode designation input U is connected to the synchronization circuit 20 described above.
The synchronization signal SS from
Simultaneously with the rise of TS, that is, the generation of the threshold signal TS, the positional deviation detection circuit 40 is put into the count-up mode. The signal applied to the other count-up mode designation input D may be a complementary signal SS1 of the synchronizing signal SS as shown in FIG. 2d. It rises at the center of the threshold signal TS and switches the positional deviation detection circuit 40 to countdown mode. By switching the count mode of the positional deviation detection circuit 40 for the count pulses CPa and CPb in this manner, the difference na−nb in the number of pulses described above is stored in the circuit 40 at the end of the threshold signal TS. Since the stored count value is stored, at this point, the stored count value can be read into the circuit 8 via the input port 8a of the control circuit 8, for example, bit-parallel as shown. Also, the difference in the number of pulses above is na−nb
When the value of becomes negative, the carry signal output from the final stage of the counter may be stored, and the carry signal may be read at the same time as reading the count value described above. The control circuit 8 calculates the value of the control signal CS for the drive circuit 6d of the actuator 6 based on the positional deviation signal read in this way, and outputs the control signal CS through its output port 8b.
Output CS. Next, a specific embodiment of the circuit of the present invention will be described with reference to FIG. The parallel circuit 7 which receives the read signal of the reference signal 3 from the head 4 includes a differential input differential output high precision operational amplifier 71 and an associated circuit at its output side. Capacitors 72a and 72b receiving the two differential outputs cut off the DC component in the output signal and provide only the AC component to the right resistance circuit. A pair of resistors 73a and 73b are load resistors for differential output, and substantially both resistors 73a and 73b are load resistors for differential output.
A reference signal RS is taken from the interconnection point of 3a and 73b, and a pair of resistors 74a and 74b are added to maintain symmetry for the differential amplification difference of the operational amplifier 71. The center of the threshold signal generation circuit 10 is an operational amplifier 11 that performs an integral operation, and a known feedback capacitor 12 is connected between its input and output.
The signal integrated by this amplifier 11 is the potential of a connection point V shown on the difference side, and a synchronization signal SS from a synchronization circuit 20 is applied to this connection point V via a resistor 15. . Therefore, the potential at the connection point V is "1" from the rising edge l1 of the synchronizing signal SS to the center m1, and is "0" from the center m1 to the terminal n1. On the other hand, the integral speed, that is, the slope of the threshold signal TS, is set by a time constant determined by the aforementioned capacitor 12 and the resistance values of the resistor 13 and adjustment resistor 14 connected in series thereto. In response to the potential change at the connection point V as described above, this integrating circuit first integrates the "1" value of the potential in the positive direction at such an integration speed, and then integrates it in the negative direction at the same integration speed. Therefore, the threshold signal TS, which is the output of the operational amplifier 11, has a symmetrical triangular waveform with medium and high pitches. The operating reference potential of the upper input in the diagram of the operational amplifier 11 on the time constant circuit side is set by a pair of resistors 16a and 16b, and the operating reference potential of the lower input is set by another pair of resistors 17.
a and 17b, and is applied to the lower input via the resistor 18. Further, the two diodes 11a and 11b and the resistor 11c attached to the operational amplifier 11 are a kind of limiter circuit for ensuring the above-described operation of the amplifier. The synchronization circuit 20 may be a counter 21 which receives and is started by the reference signal RP, as shown, the counter 21 having its counter value reset by the reference signal RP and subsequently clocked by the clock circuit 22. It receives the count input C and counts up the clock pulses. The flip-flop 23 is first reset by the reference signal RP;
Since the counter 21 is counted up for a short time td and is set when the count output is output from the count stage B1, the synchronization signal SS is output from the Q output after this short delay time td after receiving the reference signal RS. emits. This set state of the flip-flop 23 continues until the counter 21 counts up and a count output is output from the subsequent counting stage B2 and is reset, and thereafter the reset state is maintained for the same amount of time as before. The aforementioned complementary synchronization signal SS1 is obtained from the output of flip-flop 23. Of course, it is not limited to this simple example.
A more accurate synchronization circuit 20 can also be easily constructed by combining known techniques. The main body of the comparison circuit 30 is a comparison operational amplifier 31, but in this example, a low-pass filter circuit is added for removing unnecessary high frequency components that may be included in the reference signal RS. This filter circuit is an LC filter consisting of a reactor 32, a capacitor 33 on the ground side, and a capacitor 34 on the B power supply side.
This is combined with a pair of resistors 35a and 35b for setting the operating reference potential of the input on the side receiving the reference signal RS of the comparison operational amplifier 31, and this DC reference potential is applied to the input via the resistor 36. given to. The comparison operational amplifier 31 compares the reference signal RS applied to the upper input in this diagram with the threshold signal TS applied to the lower input, and generates a count pulse.
A CP is generated and applied to the positional deviation detection circuit 40 configured as the up-down counter 41 described above. The head position control circuit for a disk storage device according to the present invention described above can be implemented in various forms other than the specific configurations mentioned in the embodiments. In particular, the circuit configurations of the synchronization circuit 20, the comparison circuit 30, and the positional deviation detection circuit 40 can be freely selected according to the purpose by combining known techniques within the scope of the present invention. As for the threshold signal generation circuit 10, not only the circuit configuration but also the waveform of the generated threshold signal can be selected from waveforms such as a repetitive sawtooth wave in addition to those described in the embodiment. The triangular wave having a peak value at the center described in 1. has the following unique effect. That is, referring to FIG. 2 h or k above, the threshold signal TS is generated with a time difference of Td±Tv with respect to the starting edge l of the reference signal RS, so its central peak position is the same as that of the reference signal. R.S.
A slight deviation occurs with respect to the center m. Therefore, if the center peak value of the threshold signal TS is lower than the highest peak value of the reference signal RS, there is a risk of an error in counting the number of pulses of the count pulse CP. As long as the value is selected to be slightly higher than the highest peak value of the reference signal RS, it is possible to prevent errors in counting the number of pulses of the count pulse CP under all conditions. That is, since a medium-high triangular wave naturally has a peak value at its center, it is advantageous in eliminating the above-mentioned counting error. The peak value of the triangular wave should of course be selected to be higher than the highest peak value of the reference signal RS, and more precisely, the maximum fluctuation width of the generation timing of the reference signal RP is set as tvm, and the delay time td of the threshold signal is selected. Assuming that this is the same, it is practically desirable to set it to about 1+2·Td/Tt times the highest peak value, or slightly higher than this.

【Effect of the invention】

As can be seen from the above description, according to the present invention, a plurality of information recording tracks and a plurality of reference information for detecting the position of a transducer head for reading and writing information are recorded on the storage medium disk. A group of repetitive patterns that are mutually shifted between adjacent areas is recorded as the reference information, and a pair of patterns are sequentially read out from the adjacent pair of areas via the head. In a head position control circuit of a disk storage device that detects and controls the position of the head based on a reference information signal of No matter how much deviation occurs, the current position of the head can always be accurately detected, and based on this, the deviation from the normal position of the head can be correctly corrected. According to the present invention, the head position control circuit of the above-mentioned type of disk storage device can fully exhibit advantages over the conventional technology, and the circuit configuration for detecting the head position can be simplified. operation can be ensured. In contrast to the proposal of the earlier application of the present invention, in order to implement the present invention, it is only necessary to slightly delay the synchronization signal from the synchronization circuit, so there is no need to add a substantial circuit configuration, and the new proposed method Problems encountered during implementation can be completely resolved. Note that when implementing the present invention, it is necessary to make the time width of the reference signal longer than the generation time width of the threshold signal, and therefore it is theoretically necessary to have a wide writing area for the reference information. , the fluctuation width of the reference signal generation timing is usually 1/20 of the total time width of the reference signal.
Due to the following trivial amount, in practice there is no need to expand the area for reference information for the embodiments of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the basic configuration of a head position control circuit for a disk storage device according to the present invention together with related parts, and FIG. 2 shows waveforms of main signals in the circuit to explain the circuit operation. Waveform diagram, Figure 3 is a circuit diagram of a specific embodiment of the present invention, Figure 4 is a circuit diagram of a specific embodiment of the present invention.
The figure is a side view of a main part of an example of a disk storage device to which the present invention is implemented, FIG. 5 is a plan view of the main part,
FIG. 6 is a write area allocation diagram showing an example of a state in which reference information is written in the prior art; FIG. 7 is a write area allocation diagram showing an example of how reference information for head position detection is written to which the present invention is applied; FIG. 8 is a waveform diagram showing waveforms of main signals in a circuit for explaining circuit operation in a conventional technique using the reference information. In the figure, 1: disk, 2: track, 3, 3a, 3
b: Reference information or servo information, 4: Head,
6: Head actuator, 6d: Actuator drive circuit, 7: Reference signal amplification circuit, 8:
Control circuit or microcomputer, 10: Threshold signal generation circuit, 20: Synchronization circuit, 30:
Comparison circuit, 40: Positional deviation detection circuit, 41: Up-down counter, CP, CPa, CPb: Count pulse, CS: Control signal, l: Start end of reference information,
m: center of reference information, n: end of reference information, P
0: Normal head position, P1, P2: Head position deviated from normal position, RP: Reference signal or index pulse, RS, RSa, RSb: Reference signal,
SS: Synchronization signal, SS1: Complementary signal of synchronization signal, TS:
Threshold signal, td: delay time of threshold signal,
tv: fluctuation time of the reference signal.

Claims (1)

[Claims] 1 A plurality of information recording tracks and a plurality of areas in which reference information for detecting the position of the transducer head that reads and writes information on the tracks are set on the storage medium disk, and as the reference information. A group of repetitive patterns that are shifted from each other are recorded between adjacent areas, and the position of the head is detected based on a pair of reference information signals that are sequentially read out from the pair of adjacent areas via the head. and a threshold signal generating circuit that generates a ramp-shaped threshold signal that changes over time, and a threshold signal generating circuit that generates the threshold signal based on a reference signal that is generated in synchronization with the rotation of the disk. a synchronization circuit that emits a synchronization signal that starts the operation of the generation circuit; and a synchronization circuit that compares each of the pair of reference information signals with the threshold signal to determine the number of repetitive pattern signals in the reference signal that cross the threshold. A comparator circuit that emits a count pulse for counting, and a position that counts the count pulse for each of a pair of reference information signals and detects the amount of deviation from the normal position of the head with respect to the track from the difference between the two counts. a shift detection circuit, the synchronization circuit emits a synchronization signal at a timing delayed from the starting edge timing of the reference information signal, and the threshold generation circuit receiving the synchronization signal detects the synchronization signal from the starting edge to the ending edge of the reference information signal. 1. A head position control circuit for a disk storage device, characterized in that the circuit emits a threshold signal having a time width shorter than that of the head position control circuit.