JPH0468706A - Broad band fet amplifier - Google Patents
Broad band fet amplifierInfo
- Publication number
- JPH0468706A JPH0468706A JP17827290A JP17827290A JPH0468706A JP H0468706 A JPH0468706 A JP H0468706A JP 17827290 A JP17827290 A JP 17827290A JP 17827290 A JP17827290 A JP 17827290A JP H0468706 A JPH0468706 A JP H0468706A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- fet
- constant line
- circuit means
- distributed constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- Microwave Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は広帯域ＦＥＴ （電界効果トランジスタ）増
幅装置に係り、特にマイクロ波帯で用いるに当たり１オ
クタ一ブ以上にわたって高利得を得るに好適な広帯域Ｆ
ＥＴ増幅装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a wideband FET (field effect transistor) amplification device, and particularly to a wideband FET (field effect transistor) amplification device suitable for obtaining high gain over one octave or more when used in the microwave band. F
It relates to an ET amplifier.
［従来の技術］
第４図は、例えばｒＧａＡｓ ＦＥＴ Ｕｌ−ｔｒ
ａｂｒｏａｄ−Ｂａｎｄ Ａｍｐｌｉｆｉ −ｅｒｓ
ｆｏｒ Ｇｂｉｔｓ／ｓ ＤａｔａＲａｔｅ
ＳｙｓｔｅｍｓＪ （Ｋ、ＨＯＮＪＯ他著、ＩＥＥ
Ｅ、１９８１．Ｊｕｌｙ Ｔｒａ−ｎｓ、ｏｎ
ＭＴＴ）に示された広帯域ＦＥＴ増幅装置の１段分を抜
き出して示す回路構成図である。図において、（１）は
ソース接地されたＦＥＴで、ゲート端子Ｇ１ソース端子
Ｓ１ ドレイン端子りを有する。（２）は分布定数線路
であり、抵抗（３）に直列に接続され、ＦＥＴ （１）
のゲート端子Ｇと接地間に接続される。一方、（４）は
分布定数線路であり、抵抗（５）に直列に接続され、Ｆ
ＥＴ （１）のドレイン端子りと接地間に接続される。[Prior art] FIG. 4 shows, for example, an rGaAs FET Ul-tr
abroad-Band Amplifiers
for Gbits/s DataRate
SystemsJ (K, HONJO et al., IEE
E., 1981. July Tran-ns, on
FIG. 2 is a circuit configuration diagram showing one stage of the wideband FET amplifier shown in FIG. In the figure, (1) is a FET whose source is grounded, and has a gate terminal G, a source terminal S1, and a drain terminal. (2) is a distributed constant line, which is connected in series with the resistor (3), and is connected to the FET (1)
is connected between the gate terminal G and ground. On the other hand, (4) is a distributed constant line, which is connected in series with the resistor (5) and F
Connected between the drain terminal of ET (1) and ground.
（６）は整合回路で、一端はＦＥＴ（１）のゲート端子
Ｇに接続され他端は入力端子（８）に接続されている。(6) is a matching circuit, one end of which is connected to the gate terminal G of FET (1), and the other end connected to the input terminal (8).
（７）は整合回路で、一端はＦＥＴ （１）のドレイン
端子り接続され他端は出力端子（９）に接続されている
。(7) is a matching circuit, one end of which is connected to the drain terminal of FET (1), and the other end connected to the output terminal (9).
以上のような構成において、次にその動作を説明する。The operation of the above configuration will now be described.
第４図の構成において、高周波数域においては分布定数
線路（２）、（４）に比べて抵抗（３）。In the configuration shown in FIG. 4, in the high frequency range, the resistance (3) is higher than the distributed constant lines (2) and (4).
（５）の影響がそれぞれ小さくなるように各素子の値が
選択されている。従って、入力側も出力側も共に高周波
数域においては分布定数線路（２）と整合回路（６）及
び分布定数線路（４）と整合回路（７）とでそれぞれイ
ンピーダンス整合を行なっている。一方、低周波数域に
おいては、逆に分布定数線路（２）、（４）に比べて抵
抗（３）。The values of each element are selected so that the influence of (5) is reduced. Therefore, impedance matching is performed by the distributed constant line (2) and the matching circuit (6) and by the distributed constant line (4) and the matching circuit (7) in the high frequency range on both the input side and the output side. On the other hand, in the low frequency range, the resistance (3) is lower than that of the distributed constant lines (2) and (4).
（５）の影響を大きくすることによって不必要な利得の
増加を抑制することができる。その結果、入力端子（８
）からの入力信号に対する出力端子（９）からの出力信
号の利得としては低周波数域から高周波数域まで広帯域
に平坦な特性を得ることができる。By increasing the influence of (5), unnecessary increases in gain can be suppressed. As a result, the input terminal (8
As for the gain of the output signal from the output terminal (9) with respect to the input signal from ), it is possible to obtain flat characteristics over a wide band from a low frequency range to a high frequency range.
［発明が解決しようとする課題］
従来の広帯域ＦＥＴ増幅装置は以上のように構成されて
いるので、広帯域にわたって平坦な周波数特性を得るた
めに、低周波数域での利得を抑制しており、そのために
ＦＥＴ （１）のゲート端子Ｇと接地間に分布定数線路
（２）と抵抗（３）を接続している。ところが、高周波
数域でこの抵抗（３）の影響を全く無視することはでき
ず、高周波数域での利得の減少が避けられなかった。こ
のため、利得の周波数特性を平坦にしようとすると利得
が抑制され、逆に利得を上げようとすると周波数特性の
平坦性を犠牲にする必要がでてくるという問題があり、
広帯域わたって平坦で高い利得を得ることが大きな課題
となっていた。[Problem to be solved by the invention] Since the conventional wideband FET amplifier device is configured as described above, the gain in the low frequency range is suppressed in order to obtain flat frequency characteristics over a wideband. A distributed constant line (2) and a resistor (3) are connected between the gate terminal G of the FET (1) and ground. However, the influence of this resistor (3) cannot be completely ignored in the high frequency range, and a decrease in gain in the high frequency range is unavoidable. Therefore, if you try to flatten the frequency characteristics of the gain, the gain will be suppressed, and conversely, if you try to increase the gain, you will have to sacrifice the flatness of the frequency characteristics.
Obtaining a flat and high gain over a wide band has been a major challenge.
この発明は、上記のような課題を解決するためになされ
たもので、１オクタ一ブ以上の広帯域にわたって高利得
を得ることを可能とした広帯域ＦＥＴ増幅装置を得るこ
とを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a wideband FET amplifier device that can obtain high gain over a wideband of one octave or more.
［課題を解決するための手段］
上記目的を達成するために、この発明は、ソース端子を
接地されるＦＥＴと、前記ＦＥＴのゲート端子にインピ
ーダンス整合用の入力整合手段を接続して構成される入
力側回路手段と、前記ＦＥＴのドレイン端子にインピー
ダンス整合用の出力整合手段を接続して構成される出力
側回路手段と、前記入力側回路手段及び出力側回路手段
の少なくとも一方と接地間に接続されるインダクタと抵
抗の直列回路手段と、前記直列回路手段の抵抗に並列に
接続され所望の電気長を有する分布定数線路手段を備え
る広帯域ＦＥＴ増幅装置を提供するものである。[Means for Solving the Problems] In order to achieve the above object, the present invention comprises an FET whose source terminal is grounded, and an input matching means for impedance matching connected to the gate terminal of the FET. An input side circuit means, an output side circuit means configured by connecting an output matching means for impedance matching to the drain terminal of the FET, and a connection between at least one of the input side circuit means and the output side circuit means and ground. The present invention provides a broadband FET amplifier device comprising a series circuit means of an inductor and a resistor, and a distributed constant line means connected in parallel to the resistor of the series circuit means and having a desired electrical length.
［作用］
上記手段において、この発明の広帯域ＦＥＴ増幅装置は
、直列回路手段の抵抗に並列接続される分布定数線路手
段の電気長を、１オクタ一ブ程度の帯域幅を有する所望
の帯域の帯域側周波数に対して１７４波長とすることに
より、この帯域で分布定数線路手段のインピーダンスを
開放とし、これより２倍の周波数で分布定数線路手段の
インピーダンスを短絡にし、これにより入力側回路手段
からＦＥＴ、出力側回路手段を経て得られる利得を高め
ると共に１オクタ一ブ程度の帯域内での利得特性を平坦
にしている。[Operation] In the above means, the broadband FET amplifier device of the present invention allows the electrical length of the distributed constant line means connected in parallel to the resistor of the series circuit means to be a desired band having a bandwidth of about one octave. By setting 174 wavelengths for the side frequency, the impedance of the distributed constant line means is opened in this band, and the impedance of the distributed constant line means is short-circuited at twice the frequency, thereby causing the FET to be disconnected from the input side circuit means. , the gain obtained through the output side circuit means is increased, and the gain characteristics are flattened within a band of about one octave.
［実施例］ 以下、図面を参照しながらこの発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図はこの発明の一実施例に係る広帯域ＦＥＴ増幅装
置の回路構成図である。図において、（１０）はＦＥＴ
（１）のゲート端子Ｇに接続されるインダクタ、（１
１）はその一端をインダクタ（１０）に接続され他端を
接地される抵抗、（１２）は抵抗（１１）に並列に接続
される所望の電気長を有す°る分布定数線路である。一
方、入力端子（８）は整合回路（６）を介してＦＥＴ（
１）のゲート端子Ｇに接続され、ＦＥＴ （１）のドレ
イン端子りは整合回路（７）を介して出力端子（９）に
接続される。FIG. 1 is a circuit diagram of a broadband FET amplifier according to an embodiment of the present invention. In the figure, (10) is an FET
An inductor connected to the gate terminal G of (1),
1) is a resistor whose one end is connected to the inductor (10) and the other end is grounded; and (12) is a distributed constant line having a desired electrical length and connected in parallel to the resistor (11). On the other hand, the input terminal (8) is connected to the FET (
1), and the drain terminal of the FET (1) is connected to the output terminal (9) via a matching circuit (7).
以上のような構成において、−次にその動作を説明する
。In the above configuration, the operation thereof will be explained next.
抵抗（１１）に並列に接続される分布定数線路（１２）
の電気長を１オクタ一ブ程度の帯域幅を有する所望の帯
域の低域側周波数ｆｏに対して、１／４波長に選んでお
く。その結果、低域側周波数ｆＯに対して分布定数線路
（１２）のインピーダンスは開放となり、分布定数線路
（１２）の影響がなくなり、相対的に抵抗（１１）の効
果が大きくなる。一方、低域側周波数ｆＯの２倍の周波
数２ｆＯに対しては分布定数線路（１２）のインピーダ
ンスは短絡となり、相対的に抵抗（１１）の影響が無視
できるようになる。従って、低域側周波数ｆＯの２倍の
周波数２ｆＯにおいてインダクタ（１０）のインダクタ
ンスと整合回路（６）とでインピーダンス整合を行なえ
るように各素子の値を選ぶことによって、この増幅装置
は周波数２ｆＯでは抵抗（１１）の影響をほとんど受け
ることなく高利得を得ることができる。また、抵抗（１
１）の値を調整することによって周波数ｆＯの近傍から
その２倍の周波数２ｆＯまでの所望の帯域で平坦な利得
特性と高利得を得ることができる。Distributed constant line (12) connected in parallel to resistor (11)
The electrical length is selected to be 1/4 wavelength with respect to the lower frequency fo of a desired band having a bandwidth of about one octave. As a result, the impedance of the distributed constant line (12) becomes open to the lower frequency fO, the influence of the distributed constant line (12) disappears, and the effect of the resistor (11) becomes relatively large. On the other hand, at a frequency 2fO that is twice the lower frequency fO, the impedance of the distributed constant line (12) becomes a short circuit, and the influence of the resistance (11) becomes relatively negligible. Therefore, by selecting the values of each element so that impedance matching can be performed between the inductance of the inductor (10) and the matching circuit (6) at the frequency 2fO, which is twice the lower frequency fO, this amplifier device can be operated at a frequency of 2fO. In this case, high gain can be obtained almost without being affected by the resistor (11). Also, the resistance (1
By adjusting the value of 1), it is possible to obtain flat gain characteristics and high gain in a desired band from the vicinity of the frequency fO to twice the frequency 2fO.
第２図はこの発明の他の実施例に係る広帯域ＦＥＴ増幅
装置の回ｉ構成図である。同図の構成の第１図の構成と
異なる点は、抵抗（１１）と分布定数回路（１２）の並
列回路と接地間にキャパシタ（１３）を接続し、抵抗（
１１）、分布定数線路（１２）の並列回路とキャパシタ
（１３）の接続点にバイアス端子（１４）を接続した二
と、並びにインダクタ（１０）の代わりに分布定数線路
（１５）を接続したことである。FIG. 2 is a block diagram of a broadband FET amplifier according to another embodiment of the present invention. The difference between the configuration in the figure and the configuration in Figure 1 is that a capacitor (13) is connected between the parallel circuit of the resistor (11) and the distributed constant circuit (12) and the ground,
11) A bias terminal (14) is connected to the connection point between the parallel circuit of the distributed constant line (12) and the capacitor (13), and a distributed constant line (15) is connected in place of the inductor (10). It is.
以上述べたような構成において、キャパシタ（１３）は
低域側周波数ｆＯからその２倍の周波数２ｆＯにわたる
帯域で、その影響を無視できる容量値に設定されている
。その結果、バイアス端子（１４）からＦＥＴ （１）
のゲートバイアスを印加することができるようになる。In the configuration described above, the capacitor (13) is set to a capacitance value that allows its influence to be ignored in a band extending from the lower frequency fO to twice the frequency 2fO. As a result, from the bias terminal (14) to the FET (1)
It becomes possible to apply a gate bias of .
その他の動作については第１図の構成の場合と全く同様
であり、低域側周波数ｆＯからその２倍の周波数２ｆＯ
まで平坦で高い利得特性を得ることができる。The other operations are exactly the same as in the case of the configuration shown in Fig. 1, starting from the lower frequency fO to twice the frequency 2fO.
It is possible to obtain flat and high gain characteristics up to
第３図はこの発明の更に他の実施例に係る広帯域ＦＥＴ
増幅装置の回路構成図であり、第１図の構成と異なる点
は、抵抗（１１）と分布定数線路（１２）の並列回路と
接地間にキャパシタ（１３）を接続したことと、整合回
路（６）とインダクタ（１０）の接続点とＦＥＴ （１
）のゲート端子Ｇの間に整合回路（１６）を介在させた
ことである。FIG. 3 shows a broadband FET according to still another embodiment of the present invention.
This is a circuit configuration diagram of an amplifier device, and the difference from the configuration in FIG. 1 is that a capacitor (13) is connected between the parallel circuit of a resistor (11) and a distributed constant line (12) and the ground, and a matching circuit ( 6) and the connection point of inductor (10) and FET (1
) is provided with a matching circuit (16) between the gate terminals G of the two.
以上述べたような構成によれば、低周波数域の周波数ｆ
Ｏから１オクタ一ブ以上の周波数にわたって整合回路（
１６）の作用に基づく広い帯域での整合を取りやすくし
、広帯域における利得特性の平坦化と高利得を実現して
いる。According to the configuration described above, the frequency f in the low frequency range
A matching circuit (
Based on the effect of 16), matching in a wide band is facilitated, and flat gain characteristics and high gain in a wide band are realized.
なお、上記各実施例ではＦＥＴ （１）のゲート端子Ｇ
に至る入力側回路に抵抗（１１）に並列に所望の電気長
を有する分布定数線路（１２）を接続した構成を例示し
たが、同様の回路を出力側に設けた構成、入力／出力側
の両方に設けた構成でも同様効果を得ることができる。In each of the above embodiments, the gate terminal G of FET (1)
Although the configuration in which a distributed constant line (12) having a desired electrical length is connected in parallel to the resistor (11) to the input side circuit leading to A similar effect can be obtained even with a configuration provided on both sides.
［発明の効果コ
以上のように、この発明によれば、ＦＥＴのゲート端子
と接地間に接続するインダクタと抵抗との直列回路に加
えて抵抗と並列に所望の電気長を有する分布定数線路を
設けたので、１オクタ一ブ以上の広帯域にわたり平坦な
利得特性で高利得の増幅器が得られる効果がある。[Effects of the Invention] As described above, according to the present invention, in addition to a series circuit of an inductor and a resistor connected between the gate terminal of an FET and the ground, a distributed constant line having a desired electrical length is connected in parallel with the resistor. This arrangement has the effect of providing a high-gain amplifier with flat gain characteristics over a wide band of one octave or more.
第１図はこの発明の一実施例に係る広帯域ＦＥＴ増幅装
置の回路構成図、第２図はこの発明の他の実施例に係る
広帯域ＦＥＴ増幅装置の回路構成図、第３図はこの発明
の更に他の実施例に係る広帯域ＦＥＴ増幅装置の回路構
成図、第４図は従来の広帯域ＦＥＴ増幅装置の回路構成
図である。
図において、（１）はＦＥＴ、（２）は分布定数線路、
（３）は抵抗、（４）は分布定数線路、（５）は抵抗、
（６）は整合回路、（７）は整合回路、（８）は入力端
子、（９）は出力端子、（１０）はインダクタ、（１１
）は抵抗、（１２）は分布定数線路、（１３）はキャパ
シタ、（１４）はバイアス端子、（１５）は分布定数線
路、（１６）は整合回路である。
なお、図中、同一符号は同一、又は相当部分を示す。
代理人 弁理士 吉 １）研 二
（外２名）
１、 ＦＥＴ（（ｘ：ケート旬姑子。
６．整合回路
７ 整合回路
８、入力Ｓ＋
９、出力ｆｌＩ］＋
１０、 イ〉り”フタ
１１、ｊ耐ル
Ｃ）：）ニレイン立端ド）。
５；ソーλ蔚魁子）
１６、ｇ合口路
第
図
１４゜
キャへ〇シク
ノマイ７ス舅虻ｔト
１５、分￥一定数稗路
２、分子定数碌路
３、砥面
４、分浄定数竹路
５、抵抗
第
手
続
補
正
書（自発）
５、補正の対象
平成 ２年
９月２７日
明細書の特許請求の範囲及び発明の詳細な説明の欄。
６、補正の内容
発明の名称
広帯域ＦＥＴ増幅装置
補正をする者
理
人
特許請求の範囲
ソース端子を接地されるＦＥＴと、前記ＦＥＴのゲート
端子に入力整合手段を接続して構成される入力側回路手
段と、前記ＦＥＴのドレイン端子に出力整合手段を接続
して構成される出力側回路手段と、前記入力側回路手段
および出力側回路手段の少なくとも一方と接地間に接続
されるインダクタと抵抗の直列回路手段と、前記直列回
路手段の抵抗に並列に接続され所望の電気長を有する伝
送線路手段を備えることを特徴とする広帯域ＦＥＴ増幅
装置。FIG. 1 is a circuit diagram of a broadband FET amplifier according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a broadband FET amplifier according to another embodiment of the invention, and FIG. 3 is a circuit diagram of a broadband FET amplifier according to another embodiment of the invention. FIG. 4 is a circuit diagram of a wideband FET amplifier according to another embodiment. FIG. 4 is a circuit diagram of a conventional wideband FET amplifier. In the figure, (1) is an FET, (2) is a distributed constant line,
(3) is a resistance, (4) is a distributed constant line, (5) is a resistance,
(6) is a matching circuit, (7) is a matching circuit, (8) is an input terminal, (9) is an output terminal, (10) is an inductor, and (11) is a matching circuit.
) is a resistor, (12) is a distributed constant line, (13) is a capacitor, (14) is a bias terminal, (15) is a distributed constant line, and (16) is a matching circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Patent Attorney Yoshi 1) Kenji (2 others) 1. FET ((x: Kate Shunkako. 6. Matching circuit 7 Matching circuit 8, input S+ 9, output flI]+ 10, I〉li" lid 11 , j resistance C):) Nirain standing end de). , molecular constant Rokuji 3, abrasive surface 4, separation constant Takeji 5, resistance No. procedural amendment (voluntary) 5, subject of amendment Claims and details of invention in September 27, 1990 specification Explanation column. 6. Contents of the correction Name of the invention Broadband FET amplifier device Comprising a FET whose source terminal is grounded and an input matching means connected to the gate terminal of the FET an output circuit means configured by connecting an output matching means to the drain terminal of the FET, and an inductor connected between at least one of the input circuit means and the output circuit means and ground. 1. A broadband FET amplifier comprising: a series circuit means of a resistor; and a transmission line means connected in parallel to the resistor of the series circuit means and having a desired electrical length.
Claims (1)
端子に入力整合手段を接続して構成される入力側回路手
段と、前記ＦＥＴのドレイン端子に出力整合手段を接続
して構成される出力側回路手段と、前記入力側回路手段
および出力側回路手段の少なくとも一方と接地間に接続
されるインダクタと抵抗の直列回路手段と、前記直列回
路手段の抵抗に並列に接続され所望の電気長を有する分
布定数線路手段を備えることを特徴とする広帯域ＦＥＴ
増幅装置。An input side circuit means comprising an FET whose source terminal is grounded, an input matching means connected to the gate terminal of the FET, and an output side circuit comprising an output matching means connected to the drain terminal of the FET. means, a series circuit means of an inductor and a resistor connected between at least one of the input side circuit means and the output side circuit means and ground, and a distribution connected in parallel to the resistor of the series circuit means and having a desired electrical length. Broadband FET characterized by comprising constant line means
Amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2178272A JPH0834394B2 (en) | 1990-07-04 | 1990-07-04 | Broadband FET amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2178272A JPH0834394B2 (en) | 1990-07-04 | 1990-07-04 | Broadband FET amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0468706A true JPH0468706A (en) | 1992-03-04 |
| JPH0834394B2 JPH0834394B2 (en) | 1996-03-29 |
Family
ID=16045577
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2178272A Expired - Lifetime JPH0834394B2 (en) | 1990-07-04 | 1990-07-04 | Broadband FET amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0834394B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0585101U (en) * | 1992-04-22 | 1993-11-16 | 三菱電機株式会社 | Bias circuit for microwave semiconductor device |
| US5363060A (en) * | 1992-08-12 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Microwave amplifier |
| US6144529A (en) * | 1997-03-25 | 2000-11-07 | Tdk Corporation | Slider with negative and positive pressure generating portions and head including the same |
| US6904683B2 (en) | 2000-11-16 | 2005-06-14 | Kai R&D Center Co., Ltd. | Nail clippers |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62209909A (en) * | 1986-03-11 | 1987-09-16 | Mitsubishi Electric Corp | Ultra high frequency semiconductor circuit |
-
1990
- 1990-07-04 JP JP2178272A patent/JPH0834394B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62209909A (en) * | 1986-03-11 | 1987-09-16 | Mitsubishi Electric Corp | Ultra high frequency semiconductor circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0585101U (en) * | 1992-04-22 | 1993-11-16 | 三菱電機株式会社 | Bias circuit for microwave semiconductor device |
| US5363060A (en) * | 1992-08-12 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Microwave amplifier |
| US6144529A (en) * | 1997-03-25 | 2000-11-07 | Tdk Corporation | Slider with negative and positive pressure generating portions and head including the same |
| US6317294B1 (en) | 1997-03-25 | 2001-11-13 | Tdk Corporation | Slider with negative and multiple positive pressure generation portions and head including the same |
| US6904683B2 (en) | 2000-11-16 | 2005-06-14 | Kai R&D Center Co., Ltd. | Nail clippers |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0834394B2 (en) | 1996-03-29 |
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