JPH0468716A - information processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and particularly to an information processing device that detects errors in information that occur during reading of recorded information or on a communication path using codes, and corrects and decodes the information. .

[Prior Art] Conventionally, as one of this type of decoding method, USP 4,4
In 97,058, an RS called super strategy (
A method for decoding a Reed Solomon code is disclosed.

Here, by elements on the Galois field GF (2'), the code amount minimum distance cL, , = 5, that is, Cr and Cz codes with 2 correction capabilities are converted to CI RC (Cross Inter
leaved Read-3olomon Codes
) is configured in this format. In addition, GF (2
” ), the operation is performed in 8-bit units.

Then, based on the decoding result of the C1 code prior to the decoding of the C2 code, ■ If there are 0.1 errors, correction processing is performed and the CI flag = OFF ■ If there are 2 errors, correction processing is performed, and C, flag = ON
(1) If there are three or more errors, no correction processing is performed, and a 01 flag is added such that the C1 flag is set to ON, and the information of the C1 flag is used to increase the reliability of decoding the C2 code.

There is also a method of erasure correction based only on the error position without using the erroneous result pattern, but in the past, for the purpose of increasing the reliability of decoding, erasure correction was not used and processing was performed only within the range of error correction capability. was doing. Furthermore, conventionally, when erasure correction is used, switching is not performed, such as using erasure correction under certain conditions and not using erasure correction under other conditions.

[Problem to be solved by the invention] However, when reading recorded information or receiving communication information, synchronization (Resync) errors often occur, bit shifts occur, and long blocks of data such as all the data in one block are incorrect. A burst error occurs. Even in such a case, the above CIRC method can only recognize that an error larger than the correction ability of C1 has occurred.
A method that performs only correction within the error correction capability of conventional codes cannot cope with long burst errors.

The present invention eliminates the drawbacks of the prior art described above, and its purpose is to provide an information processing device with higher reliability and correction ability.

[Means and operations for solving the problem] In order to achieve the above object, the information processing apparatus of the present invention includes an input means for inputting encoded information, and a position and function of an error in the inputted information. a decoding means for detecting the size and correcting the decoding;
an erasure correction means for detecting and correcting the position of an error in the input information; a detection means for detecting a burst error in the input information; and when a burst error is detected by the detection means, the The erasure correcting means performs correction, and the decoding means performs decoding when the erasure correction means is not detected.

Preferably, the detection means detects a burst error by detecting a synchronization shift of input code information.

As a result, the presence and location of burst errors can be reliably grasped, and decoding can be performed with increased reliability and correction ability.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a block configuration diagram showing an example in which the information processing device of the embodiment is applied to reading recorded data on an optical disk. In FIG. 0, 1 is a signal detector (optical pickup); Read recorded data. A preamplifier 2 amplifies the read information signal.

3 is a binarization circuit which binarizes the amplified information signal. 4 is a decoding means, which decodes the binarized information data and controls error detection and correction; FIG. 4(A);
(B) or Figure 5 (A).

(B)) Outputs the decoded read data and clock signal.

The error correction code used in this example is ReedSol.
This is called the omon code, and is currently used on CDs (Com
This is the same as the one widely used in discs such as pact disks. For methods of encoding and decoding Reed Solomon codes, see USP 4,497,05.
8, and has been published in various other publications.

5 is a sector synchronization circuit, which synchronizes with sectors, which are information recording units on the optical disk. A phase-locked loop circuit (PLL) 6 generates a clock signal synchronized with sector data. 7 is Re5sync
) This is a detection circuit that performs resynchronization based on resync signals at predetermined intervals in a sector, detects the presence or absence of a resync error, and notifies the decoding means 4 when a resync error is detected.

FIG. 2 is a diagram schematically showing the sector recording structure of the embodiment. In the figure, Re5ync is sync data for resynchronization, and each 36-byte recording data C,
It is written in the front part of (1) to C and (36). As a result, even if, for example, a bit shift occurs while reading the recorded data c s (1), it is possible to resynchronize with the next sync data, and furthermore, the next recorded data c s (2
) can be read correctly. Therefore, in the case of this embodiment, burst errors can be stopped at a maximum of 36 bytes.

Although not shown, address information for specifying the sector, sync data for sector synchronization, etc. are written at the beginning of the sector.

FIG. 3 is a conceptual diagram showing the configuration of one sector data in the embodiment in a two-dimensional view. In FIG.
(=1024) bytes. Then, a parity C2 of 4 bytes is applied to each vertical direction of this information data.
is added, resulting in a total of 32 sets of codes C2(1) to C2(32)
is generated.

Furthermore, these 32 sets of codes C2(1) to C, (32)
Add 4 bytes of parity C1 to each horizontal direction,
A total of 36 sets of codes C+ (1) to C, (36) are generated. Therefore, one sector data has a product code structure of 1296 bytes in total.

Furthermore, the parameters in this configuration are the same for the Ct code and the interleaved C2 code that constitute code words in the data recording direction, and the code length n is n c
1= n cz= 36 bytes, information length k cI=
k cz = 32 bytes, code amount minimum distance d is d c
s” d C2 = 5, correction ability t is t c, = t
cz=2 bytes. Also, 8 bits (1 byte)
It is composed of a system on GF (2') that performs calculations in units, and its 256 elements are ro,
1. C1, C2, . . . , α214".

The basic concept of this coding system is explained in W.

Wesley Peterson and E.J.
Weldon, Jr., “Error-Correct
ing Codes 2nd Edition, M
Please refer to IT PRESS.

When encoding this one sector information, first the code C2
(1), C2(2), ..., C2(32) in the order
3 encoding (addition of 4 parities). Next, the code C+(
1), C+(2), ..., C1 in the order of C, (36)
When encoding (adding 4 parities) or decoding one sector information, contrary to encoding, first the code CI (1),
Perform C1 decoding in the order of CI (2), -..., C, (36), then C* (1) +' C* (2) ,,
..., 02 group number in the order of Cm (32).

Here, the two-error correction capability in this embodiment will be described.

2 error correction capability means that two pairs of error position (byte position) and error size (error byte pattern) are determined.

That is, it has four independent linear equations, from which the above two sets of information can be obtained.

On the other hand, if the location of the error is known by some method, it is possible to perform erasure correction based on information only about the location and correct more error patterns.

Table 1 shows the relationship between the maximum combination of the number of erasure corrections and the number of error corrections in the case of 2 error correction capability (code amount minimum distance is 5).

Margin Table 1 Below: Regarding the decryption algorithm in this case, Y, S
Ugiyama et al, An Erasure-
and-ErrorsDecoding Algori
thm for Goppa Codes, IE
EE Trans, II Mar, 1976 is helpful.

Next, the reliable decoding process of this embodiment using the relationships shown in Table 1 will be explained.

FIG. 4(A) is a flowchart of C3 decoding processing according to the embodiment. In step S1, C1 decoding processing is performed. That is,
0.1 or 2 error correction is performed according to the correction ability of the C1 code. Also, if the error exceeds the correction ability, a C flag is set. In step S2, it is determined whether there is a beam sync error.

When there is no resync error, the process proceeds to step S3, and the corresponding code CI(1), CI(2), or C,(36) is turned OFF. If there is a resync error, the process advances to step S4, and the code CI(1),
Cs (2) or C, (36) Turn on the glue sync error flag.

FIG. 4 CB) is a flowchart of the C3 decoding process of the embodiment. The beam sink error flag is O in step Sll.
Check whether it is N or not. If the resync error flag is not ON, the process advances to step S12 and C3 decoding processing is performed. Here, when there is a 0.1 or 2 error, if the CI flag and error position match, pattern correction processing is performed, and if the C1 flag and error position do not match, uncorrectable processing is performed. Uncorrectable processing is also performed for errors that exceed the correction ability in C3 decoding.

Also, the resync error flag is set to O in step Sll determination.
If N, the process advances to step S13 and the number of resync error flags is checked.

If the number of resync error flags is 1 or 2, the process advances to step S14 to perform erasure and error processing.

That is, a symbol with a resync error flag set is treated as an erasure, and as mentioned in the previous IEEE document, it is checked whether there is another 1 error due to 02, and if the number of errors is O, it is determined as an O error. If the number of errors caused by C2 is 1 and the CI flag at a position other than erasure matches the error position caused by 02, l error processing is performed.

Also, the number of errors due to C2 is 1, and C at a position other than erasure,
If the error position caused by the flag and 02 do not match, uncorrectable processing is performed, and furthermore, if the number of errors caused by C2 is 2 or more, uncorrectable processing is performed.

Further, if the number of resync error flags is three in the check at step 313, the process advances to step S14, where erasure correction processing is performed. In other words, the flagged symbol is treated as an erasure, and the pattern is corrected. However, if other CI errors are included, the error correction capability is exceeded, so uncorrectable processing is performed. If the number of resync error flags is 4 or more, the process advances to step S16 and uncorrectable processing is performed.

In this way, by incorporating erasure correction using the resync error flag, up to three error corrections are possible in C2 decoding. That is, the maximum correction length for burst errors can be extended from 72 bytes to 108 bytes.

[Other Examples] A slightly simpler method is also possible.

FIG. 5(A) is a flowchart of C1 decoding processing in another embodiment. In step S21, it is determined whether or not there is a sync error, and if there is no, C8 decoding is performed in step S22, and in step S23, the C3 code sync error flag is turned OFF. Further, if it is determined in step S21 that there is a resync error, the resync error flag is turned on in step S24.

FIG. 5(B) is a flowchart of C2 decoding processing in another embodiment. In step S31, it is checked whether the beam sync error flag is ON.

If it is not ON, the process advances to step S32 and C2 decoding is performed. If it is ON, the process advances to step S33, and it is checked whether the number of resync error flags is four or more. If there are not four or more, erasure correction processing is performed in step S34. If there are four or more, uncorrectable processing is performed in step S35.

[Effects of the Invention] As described above, according to the present invention, when there is no burst error, processing can be performed within the correction capacity, and when there is a burst error, all CI codes are regarded as errors, and the sync error flag is set. By turning ON, burst errors can be reliably known, and this symbol can be treated as an erasure in C2 decoding to improve correction ability without deteriorating reliability.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an example in which the information processing device of the embodiment is applied to reading recorded data on an optical disk. FIG. 2 is a diagram showing an outline of the sector recording structure of the embodiment. A conceptual diagram showing the configuration of one sector data in the embodiment in plan view; FIG. 4(A) is a flowchart of CI decoding processing in the embodiment; FIG. 4(B) is a flowchart of C2 decoding processing in the embodiment; FIG. 5(A) is a flowchart of C1 decoding processing in another embodiment, and FIG. 5(B) is a flowchart of C2 decoding processing in another embodiment. In the figure, 1... signal detector, 2... preamplifier, 3...
...Binarization circuit, 4...Decoding means, 5...Sector synchronization circuit, 6...Phase locked loop circuit (PLL)
), 7... Resync (Re5sync) detection circuit. Figure 5 (A) 5th v! J (B)

Claims (2)

[Claims] (1) An input means for inputting encoded information, a decoding means for detecting the position and size of an error in the inputted information, and correcting and decoding the position of the error in the inputted information. an erasure correction means for detecting and correcting; a detection means for detecting a burst error in the inputted information; and when a burst error is detected by the detection means, the erasure correction means performs correction and corrects the undetected burst error. An information processing apparatus comprising: a control means for controlling the decoding means to perform decoding. (2) The information processing apparatus according to claim 1, wherein the detection means detects a burst error by detecting a synchronization shift of input code information.