JPH0468805B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sense amplifier circuit, and more particularly to a sense amplifier circuit that detects a phase difference between signals having different phases.

2. Description of the Related Art Conventionally, a circuit configuration is known in which a plurality of detection amplification circuits are used to detect a phase difference between signals having different phases, and each signal is individually detected and amplified by the detection amplification circuit one by one.

However, such a conventional circuit configuration has a drawback in that a phase error occurs in the detection output pulse due to the offset voltage of each detection amplifier circuit.

For example, two with a 90° phase difference as shown in Figure 1a.
When detecting two sine wave signals S1 and S2, even if the reference voltage is set to 0V, each detection amplifier circuit has a
If there is an offset voltage indicated by a broken line in the figure, the detection output pulses P1 and P2 are detected shifted by Δt ₁ and Δt ₂ from the time when they should be detected, as shown in FIG. 1b, resulting in a phase error. The signal voltage to be detected is several tens of mV, and the phase error tolerance is within ±10%.
In other words, when detecting the phase difference between two pulses with a duty of 50%, the offset voltage tolerance range of the detection amplifier circuit must be several meters in order for the high portions of the pulses to overlap with a certain margin on the time axis.
V or less, and it has been difficult to realize this in a sense amplifier circuit composed of field effect transistors because the offset voltage generally exists in the order of tens of mV.

SUMMARY OF THE INVENTION An object of the present invention is to provide a novel sense amplifier circuit that cancels phase errors by equalizing phase shifts between a plurality of pairs of input signals even when there is an offset voltage.

According to the present invention, one comparator circuit having one pair of inputs and one pair of outputs, and the same number of input signals as the plurality of input signals inputting a plurality of input signals and their reference voltages or a signal complementary to the input signals. A pair of input terminals and a group of output holding circuits of the same number as the pair of input terminals, one end of each of which is connected to the terminal side into which the plurality of signals are inputted, the other end of which is connected in common, and the other end of the commonly connected The same number of first input transfer gate groups of the input terminal pair are connected to the first input of the comparison circuit, and one end is connected to the terminal of the input terminal pair, respectively, to which the reference voltage or the complementary signal is input. , a second input transfer gate group of the same number as the input terminal pairs, the other end of which is commonly connected, and the other end of which is commonly connected to the second input of the comparison circuit, and one end of which is connected to the output holding circuit group, respectively. a first output transfer gate group, the other end of which is connected to the first input of the comparator circuit, and the other end of which is connected in common to the first output of the comparison circuit; a second output transfer gate group connected to a second input of the group, having other ends commonly connected and the commonly connected other ends connected to a second output of the comparator circuit;
One period of circuit operation is divided into the same number of input terminal pairs, and within each divided period, the plurality of input signals applied to the input terminal pair and their reference voltages or the complementary signal are By applying an input clock signal to the gates of a pair of input transfer gates, the comparison result outputted through the comparison circuit is inputted by applying an output clock signal to the gates of the pair of output transfer gates. There is obtained a detection amplifier circuit characterized in that it includes means for outputting to the corresponding output holding circuit.

A feature of the detection amplifier circuit of the present invention is that one comparison circuit is used in a time-division manner to detect a phase difference between a plurality of input signals. Then, all the output signals output from the comparator circuit will have the same offset voltage, equivalently eliminating phase errors between the output signals. Therefore, even a circuit with a large offset voltage using field effect transistors can be used as a detection amplifier circuit.

The present invention will be described below with reference to drawings showing embodiments.

FIG. 2 is a circuit diagram showing one embodiment of the present invention, in which there are two pairs of input terminals. Comparison circuit 1 has inputs 2, 3 and outputs 4, 5. Input 2 of the comparison circuit is commonly connected to one end of input transfer gates 6 and 8, and input 3 of the comparison circuit is commonly connected to one end of input transfer gates 7 and 9.
The gates of input transfer gates 6 and 7 are connected to clock φ1, the other end of input transfer gate 6 is connected to input terminal A, and the other end of input transfer gate 7 receives a reference voltage source or a signal complementary to A. It is connected to the terminal. The gates of the input transfer gates 8 and 9 are connected to the clock φ3, the other end of the input transfer gate 8 is connected to the input terminal B which inputs the second signal, and the other end of the input transfer gate 9 is connected to the reference voltage source or B. It is connected to the terminal that inputs the complementary signal. The output 4 of the comparator circuit 1 is the output transfer gate 10,1
The output 5 is commonly connected to one end of the output transfer gates 11 and 13.
The gates of the transfer gates 10 and 11 are connected to the clock φ2, the other end of the output transfer gate 10 is connected to the input 15 of the first output holding circuit 14, and the other end of the output transfer gate 11 is connected to the first output holding circuit 14. It is connected to input 16 of circuit 14. The gates of the output transfer gates 12 and 13 are connected to the clock φ4, the other end of the output transfer gate 12 is connected to the input 18 of the second output holding circuit 17, and the other end of the output transfer gate 13 is connected to the second output. It is connected to the input 19 of the holding circuit 17. Q1 and Q2 are each output holding circuit 1
This is the output of 4,17.

Here, the comparison circuit 1 may be a differential amplifier circuit or a dynamic flip-flop type amplifier circuit. In addition, the output holding circuits 14 and 17 are flip-flops.
Any device like a flop that has the function of holding data until the next input comes in may be used.

Next, the circuit operation will be explained with reference to the timing diagram of the clock signal shown in FIG. First, clock φ
1 makes input transfer gates 6 and 7 conductive, and inputs signals from input terminal A to comparison circuit inputs 2 and 3.

The comparator circuit 1 amplifies a minute signal to a value necessary for driving the output holding circuit. Comparison circuit output 4, 5
complementary signals are obtained. Next, clock φ2
conducts the output transfer gates 10 and 11 at
The comparison results are input from the comparison circuit outputs 4 and 5 to the inputs 15 and 16 of the output holding circuit 14. At this time, the clock φ1 is cut off, but since the comparator circuit 1 has a data holding function, the input signal may be cut off. Furthermore, in the same way, the input transfer gates 8 and 9 are made conductive with the clock φ3, the second signal is inputted to the comparator circuit inputs 2 and 3 from the input terminal B, and the output transfer gates 12 and 13 are made conductive with the clock φ4, and the comparison result is The input 18,1 of the output holding circuit 17
Enter 9.

When detecting two or more signals, provide the same number of input transfer gate pairs, output transfer gate pairs, and output holding circuits as the signal pairs, and perform sequential input, comparison, and output as in the case of two signals. The comparison result of the pair of input terminals is obtained in the corresponding output holding circuit.

Furthermore, since the detection amplifier circuit of the present invention uses only one comparison circuit, the area occupied by the circuit is obviously smaller than the conventional case where a plurality of comparison circuits are used.

Although the above description has been made using an n-channel MOS transistor, the input/output transfer gate is not limited to this, and it goes without saying that a p-channel MOS or a complementary MOS may be used.

As is clear from the above explanation, since the same comparison circuit is used to compare the two signals, the phase shift of the output pulse due to the offset voltage is equal and there is no relative phase error.

According to the present invention, it is possible to obtain a detection amplifier circuit in which a phase error between signals does not occur even if an offset voltage exists in the comparator circuit.

[Brief explanation of drawings]

FIG. 1a is an input signal waveform diagram, and FIG. 1b is an output waveform diagram of the detection amplifier circuit. FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a clock signal timing diagram. The numbers in the figure indicate the following. 1... Comparison circuit, 2, 3... Comparison circuit input,
4, 5... Comparison circuit output, 6, 7, 8, 9... Input transfer gate, 10, 11, 12, 13
...Output transfer gate, 14, 17... Output holding circuit, 15, 16, 18, 19... Input of output holding circuit, Q1, Q2... Output of output holding circuit.

Claims (1)

[Claims] 1 one comparator circuit having one pair of inputs and one pair of outputs, and the same number of input terminal pairs as the plurality of input signals to which a plurality of input signals and their reference voltages or signals complementary to the input signals are input; A group of output holding circuits having the same number as the input terminal pairs, one end of which is connected to the terminal side to which the plurality of input signals are respectively input, and the other end of which is connected in common, and the other end of the commonly connected terminal is connected to the terminal side of the comparison circuit. a first input transfer gate group of the same number as the input terminal pair connected to one input; one end connected to the terminal to which the reference voltage or the complementary signal of the input terminal pair is input, and the other end common. a second input transfer gate group of the same number as the input terminal pairs, the other end of which is connected and commonly connected to the second input of the comparison circuit; and one end of which is connected to the first input of the output holding circuit group. a first output transfer gate group whose other end is connected to the first output of the comparator circuit, and whose other end is connected to the first output of the comparator circuit; a second output transfer gate group, the other end of which is connected to the input, the other end of which is connected in common, and the other end of which is commonly connected is connected to the second output of the comparison circuit;
A period is divided into the same number of input terminal pairs, and within each divided period, the plurality of input signals and their reference voltages or the complementary signals applied to the input terminal pair are applied to a pair of input transfer gates. The output holding circuit receives a comparison result by applying an input clock signal to the gate and outputting it through the comparison circuit by applying an output clock signal to the gates of the pair of output transfer gates. A detection amplification circuit characterized in that it is equipped with means for outputting.