JPH0468879A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a clear still picture with high vertical resolution by supplying the suitable number of timing signals corresponding to the number of gate electrodes to the gate electrode corresponding to a driving signal from a driving circuit, executing vertical charge transfer and executing full frame scan reading. CONSTITUTION:In a photodetecting area 7, photodiode P corresponding to picture elements/while being arranged in the shape of a matrix, and vertical charge transfer paths L1-Lm are provided. In the vertical charge transfer paths L1-Lm, the gate electrodes are arranged as prescribed and further at the terminal part of these paths, a horizontal charge transfer path 8 is formed. Signals for executing charge transfer operations synchronously to the vertical charge transfer paths L1-Lm at prescribed timing are supplied from first - third driving circuits 10-12 to the gate electrodes. A synchronizing control circuit 6 generates timing signals phiH, VL, phiG, phiFS, VS, phi1, phi2, phi3 and phi4 and a start pulse signal. Thus, full frame scan reading is enabled and the clear still picture can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a charge-coupled solid-state imaging device (CCD).
In particular, the present invention relates to a solid-state imaging device suitable for high integration and high pixel density.

[Conventional technology]

Heretofore, such solid-state imaging devices of the interline transfer type have been known, and are applied to electronic cameras, copying machines, and other video equipment.

This type of solid-state imaging device has a plurality of photodiodes corresponding to pixels arranged in a matrix in the row and column directions, and a vertical charge transfer path is formed adjacent to each photodiode group arranged in the column direction. Furthermore, a structure is developed in which a horizontal charge transfer path is provided at the end of each vertical charge transfer path. The area where the photodiode group and the vertical charge transfer path are formed is called a light receiving area, and the surfaces of the vertical charge transfer path and the horizontal charge transfer path are laminated with a light shielding layer for blocking incident light.

FIG. 13 is a schematic plan view of the main part of the light-receiving area when viewed from the light-receiving surface side, and the structure will be further explained according to the figure.
n+ in the P well layer formed on the surface of the semiconductor substrate.
By embedding the type impurity layer in a matrix, a plurality of photodiodes Pd, Pd2...- are formed, and each photodiode Pd+, Pdz
, . . . , there are vertical charge transfer paths L1L-, Ls . . . for transferring signal charges in the column direction Y.
The area excluding these photodiodes and vertical charge transfer paths (diagonal JI! area surrounded by dotted lines in the figure)
is the channel stop area.

Vertical charge transfer path, L2. A plurality of gate electrodes G, , G, , G, , G made of a polysilicon layer are provided on the upper surface of Lff ·-m- along the column direction Y.

Clock signals φφ2 φ, φ4 based on a four-phase drive system using four gate electrodes as one set.
or is applied.

That is, two gate electrodes G3. G2 is formed correspondingly, and two gate electrodes G3. Other photodiodes and vertical charge transfer paths, which are formed corresponding to G4 and are not shown, have similar structures. In addition, photodiode t" P d
, , P d2-- and the vertical charge transfer path, , L,
, L3- are transferage-hTg, ,'r
g2-..., and by setting the clock signal φ2 or φ4 to a predetermined high voltage, the signal charge of the photodiode is transferred to the vertical charge transfer path.

Then, a timing signal φ1 φ according to the four-phase drive method
2 φ3. By sequentially generating potential wells and Botenl barriers in synchronization with predetermined timings t0 to t4 as shown in FIG. 14 in response to voltage changes in φ4,
Vertical charge transfer path LL2. By transferring the signal charge L3, ---1 in the direction Y of the horizontal charge transfer path, and horizontally transferring the signal charge transferred from the horizontal charge transfer path to each row in synchronization with a predetermined timing, Read out chronologically.

[Invention or problem to be solved]

In such conventional charge-coupled solid-state imaging devices,
The odd-numbered photodiode groups in the row direction were defined as odd fields, and the even-numbered photodiodes were defined as even fields. First, the signal charges generated in the photodiode groups corresponding to the odd fields were read out. After that, the so-called interlaced 2 signal charges generated in the photodiodes corresponding to even fields are read out.
All signal charges corresponding to one frame image were read out by field scanning readout.

Therefore, when attempting to obtain a frame image in the case of still image capturing, there is a problem in that the time lag between each field or the quality of the reproduced image deteriorates.

The present invention has been made in view of these problems,
Instead of performing interlaced 2-field scanning readout as in the conventional technology, so-called non-interlaced full-frame readout, that is, all pixel signals corresponding to 1 frame image are read out in 1 frame.
An object of the present invention is to provide a charge-coupled solid-state imaging device that can provide a clear reproduced image by reading out multiple frames.

In addition, when providing an electronic shutter function to the charge-coupled solid-state imaging device itself without using a mechanical shutter, the so-called non-interlaced full-frame An object of the present invention is to provide a charge-coupled solid-state imaging device that can provide a clear reproduced image by reading out all pixel signals corresponding to one frame image in one frame scanning readout.

[Means to solve the problem]

To achieve this goal, the present invention forms a plurality of photoelectric conversion elements corresponding to pixels arranged in a matrix in the row and column directions, and performs vertical charge transfer adjacent to each group of photoelectric conversion elements arranged in the column direction. After forming a pixel signal and transferring the pixel signal generated in the pixel to the vertical charge transfer path, a gate signal at a predetermined timing is supplied to the gate electrode of the vertical charge transfer path to vertically transfer the pixel signal for each row. , the subject is a charge-coupled solid-state imaging device that scans and reads out pixel signals for each row using a horizontal charge transfer path.

In the present invention, which is directed to such a charge-coupled solid-state image pickup device, each transfer gate electrode is provided between each vertical transfer gate electrode and drive signal electrode, which are provided in pairs adjacent to each of the photoelectric conversion elements. A switch element is provided in the horizontal charge transfer path, and each set includes a predetermined number of gate electrodes in order from the gate electrode on the side of the horizontal charge transfer path, and the switch element is turned on to transfer pixel signals to the horizontal charge transfer path for each row. A drive circuit that sequentially generates drive signals corresponding to each set in each cycle is provided, and timing signals of a number of phases corresponding to a predetermined number of gate electrodes are supplied to gate electrodes corresponding to the drive signals from the drive circuit. By performing vertical charge transfer by
We decided to perform continuous full frame scanning.

[Effect]

According to the solid-state imaging device of the present invention having such a structure, all pixel signals corresponding to a frame image can be read out by one frame scanning readout, and furthermore, all pixel signals can be read out by exposure by an electronic shutter. can be carried out under the same conditions. Therefore, it is possible to obtain clear still images with high vertical resolution.

[Embodiment] Hereinafter, an embodiment of a charge-coupled solid-state imaging device according to the present invention will be described with reference to the drawings. A case will be described in which the present invention is applied to an electronic still camera for capturing still images.

First, the overall structure of an electronic still camera will be explained with reference to FIG. 1. In FIG. A solid-state imaging device, each with an imaging optical system 1
They are arranged in order along the optical axis of the image pickup bag a3, and are configured to make an optical image of the object incident on the light receiving area of the charge-coupled solid-state imaging bag a3.

Furthermore, 4 is a signal processing circuit, and 5 is a recording mechanism. The signal processing circuit 4 performs color separation, γ correction, white balance adjustment, etc. on the pixel signal output from the charge-coupled solid-state imaging bag f13, and converts it into a luminance signal. Color difference signals are formed, and the recording mechanism 5 performs recordable modulation processing on these luminance signals and color difference signals, and then records them on a magnetic recording medium or the like.

A series of operations from imaging to recording is processed by synchronously controlling the synchronous control circuit 6, the aperture mechanism 2, the readout timing of the charge-coupled solid-state imaging device 3, and the operation of the signal processing circuit 4 and recording mechanism 5. do.

The charge-coupled solid-state imaging device 3 has a configuration shown in FIG.

That is, the light-receiving area 7 for receiving the optical image of the object is formed by a plurality of front-ends (P in the figure) corresponding to pixels arranged in a matrix along the column direction Y and the row direction
), vertical charge transfer paths L1 to L formed adjacent to each photodiode group arranged in the column direction Y,
Or is provided.

A horizontal charge transfer path 8 is formed at the end of each of these vertical charge transfer paths .about.L, and an output amplifier 9 is formed at the end of the horizontal charge transfer path 8.

Furthermore, the vertical charge transfer paths L1 to L are provided with gate electrodes arranged in a predetermined manner, as will be described later, and furthermore, a light shielding layer for blocking the incidence of light is laminated on the upper surface of these gate electrodes.

These gate electrodes are supplied with a signal for causing the vertical charge transfer paths L to L to perform a charge transfer operation in synchronization with a predetermined timing. Second. It is supplied from the third drive circuit 10, 11.12. Note that the timing signals φH and VL φ are supplied to the respective drive circuits 10, 11, and 12. φFI
1. V8φ.

The synchronous control circuit 6 generates φ, φ2, φ4 and the start pulse signal.

Further, the horizontal charge transfer path 8 is provided with a gate electrode for receiving signal charges transferred from the vertical charge transfer paths L to L and further horizontally transferring them to the output amplifier 8 side, and these operations are performed. Gate signals α1 G2 α, applied to the gate electrodes to perform the following.

G4 is supplied from the synchronous control circuit 6.

Next, the structure of the light receiving area 7 and the circuit configuration of the drive circuits 10, 11, and 12 connected thereto are shown in FIGS. 3, 4, and 5.
This will be explained in detail with figures. In addition, FIG. 3 shows the structure of the main part of the light-receiving area 7 when viewed from the light-receiving surface side, and FIG.
FIG. 5 is a vertical cross-sectional view taken along the line y--y of FIG. 3.

In these figures, on the surface side of the n-type semiconductor substrate 13,
A p-well layer 14 for forming the light receiving region 7, a p-well layer 15 for forming the first drive circuit IO, and a second . A p-well layer 16 for forming the third drive circuit 11°I2 is buried, and these p-well layers 14, 15 .
Predetermined circuits are formed in each of the 16.

First, the light receiving region 7 is formed by arranging a plurality of impurity layers I7 made of n+ type impurities in a matrix along the column direction Y and the row direction X in the p well layer 14. A photodiode shown in FIG. A vertical charge transfer path, -L, is formed. Then, there is a p
By forming the type 1 impurity layer 19, a channel stopper region (the shaded area surrounded by the dotted line in FIG. 3) is formed.

In FIG. 3, the photodiodes P in FIG. 2 are indicated by P, , P, , P, , P, -... for each row.

Furthermore, in FIG. 3, photodiodes P1 . P
In the regions adjacent to t, Ps, P4, .

, 612-G 42. G12-G42.・---・- are stacked with G Is to G 4 a, and furthermore, the gate electrode G
Assuming that I + is the first gate electrode, as shown in FIGS. 3 and 4, the odd-numbered gate electrode G + I
+ 0211 G +□.

G22. Gn+ 023. --- Narrow the radius Wl of the even-numbered gate electrode G 21+ 04++ 0
221 G42゜G21+G41'-・-・-radius W2
It is widely formed.

Then, a gate signal φ3. φ2. φ31 φ4φ12
φ22 φ2 φ4. By applying , potential wells (hereinafter referred to as transfer pixels) and potential barriers for charge transfer are generated in the vertical charge transfer path under each gate electrode. In addition, even-numbered gate electrodes G
21+ G411 Gtt+ G4! IG! 2104
3. When a predetermined high voltage signal is applied to . th gate electrode G! I+G41+G
121041.0!21 G42. . . . The structure is such that the transfer vixel generated below becomes conductive and the signal charge can be transferred from the foot diode to the transfer pixel.

Furthermore, as shown in FIG. 3, vertical charge transfer paths L1 to L1
A horizontal charge transfer path 8 is formed at the terminal end of the gate electrode, and a gate electrode is provided for horizontally transferring signal charges at a timing similar to the four-phase drive force type or the two-phase drive force type.

Next, the circuit configuration of the first drive circuit IO is shown in FIGS. 3 and 5.
This will be explained with figures. If the gate electrode C11 closest to the horizontal charge transfer path 8 is the first gate electrode, then the odd-numbered gate electrodes G 11+ G 211G 121 G
3m, each tip of G 13 + G 31 ... or NMOS transistor M, 1. Mu□+ M121
Mn2. M+3+M22. −・−, the signal V
Connected to the L signal line, even numbered gate electrode G 11
+ G 41 + G 22 * G 42G 22
+ G 42- - Each tip of NMO3h transistor M 21+ M411 Mzt+ M42. Mn
2. It is connected to the signal line of the drive signal φ□ via M42.

Further, a drive signal φ is applied to the gate contacts of these transistors. or supplied.

Furthermore, even-numbered gate electrodes G 11+ 0411 G
221G 4m+ 022. An npn transistor Q 211 Qa is installed at each tip of the G 42--'-'-"
l+ Q221 Q42. Q2*.

Q42. The emitter contacts of '---- are connected, and the drive signals φ, 3,
A voltage V8 is applied to the collector contact.

These NMO3) transistors are connected to P in FIG.
As shown in the structure in the well layer 15, it consists of a pair of n3 type impurity layers 20 and 21 and a gate electrode laminated on the surface portion, and a drive signal φ8 is applied to the n+ type impurity layer 20, which serves as a drain contact. , the n-type impurity layer 21 serving as a source contact is connected to the gate electrode on the vertical charge transfer path. Further, the signal VL is applied to the p-type impurity layer 22 buried in the p-well layer I5. Further, the npn transistor has a p+ type impurity layer 23 buried in the p well layer 15 and an npn transistor.
Consisting of a type 1 impurity layer 24 and an n type semiconductor substrate 13, an n° type impurity layer 24 serving as an emitter contact is connected to each gate electrode, and a p well layer 15 and a p well layer 15 serving as a base contact are connected to each gate electrode.
A timing signal φ1 is applied to the 11-type impurity 23, and a bias voltage V of the substrate 13 is applied to the n-type semiconductor substrate 13 serving as a collector contact.

Next, the second drive circuit 11 transfers the timing signals φ1 to φ4 supplied from the synchronous control circuit 6 to the third drive circuit 12.
Drive signals s, , s2 . s3. s.

NMOS transistor f that switches in synchronization with S
f1z , m2+ , m3+ , m4+ -1 -, a set of four NMO3) transistors is connected to their gate contacts in order with drive signals s, , s2 . s,, s4 are applied, and the first of each set
NMOS transistor mz, m+2. m+s
, rrlz ・""'-, the timing signal φ1 is applied to the train contact, and the second NMOS transistor mz+ , m
t2. mxs, m2<--・--10 Timing signal φ2 at drain contact, third NMO8) transistor m3+, m32, m3:l, m
The timing signal φ2, the fourth
th NMOS transistor m<+, m<□, rni
Timing signal φ4 is supplied to the train contact of 3m44...-. In addition, in FIG. 3, NMOS transistors m + + , m 21 , m 31 ,
The signal φ1 on each source contact side of m 41 . φ21
φ31 φ4 or timing signal φ1φ2φ3φ4
This is a signal corresponding to

As shown in the figure, the source contacts of each N0M5 transistor are connected in order from the gate electrode G l l closest to the horizontal charge transfer path 8 .

The third drive circuit 12 receives drive signals S, S2, S3, . It is formed of a shift register that outputs S4-, -, , S4.

In addition, these second. The third drive circuit 11.12 includes a fifth drive circuit 11.12.
It is formed of an NMO3 structure transistor and an electronic element formed in the p-well layer 16 shown in the figure. In the p-well layer 16 of FIG. 5, for example, an n-type impurity layer 25, 26 and a gate contact forming an NMO3 transistor are shown.

Next, a case will be described in which the operation of the charge-coupled solid-state imaging device having such a structure is applied to an electronic still camera that takes still images.

First, the general operation for photographing a still image will be explained with reference to FIG. 6. Assuming that the period T vi in the figure corresponds to the vertical blanking period of a standard television system such as NTSC, a so-called field shift operation is performed to transfer the charge from the pixel to the vertical charge transfer path at a predetermined time during the period T v s. According to the electronic shutter function, the exposure completion point corresponds to the point of this field shift operation or the point of closing of the shutter. Therefore, the exposure operation starts from this point forward, and the exposure period continues until the field shift operation starts. Further, unnecessary charges such as smear components and dark current components in the vertical charge transfer paths L1 to L and the horizontal charge transfer path 8 are swept out by the charge transfer operation before the start of the field shift operation. Further, just before the start of exposure, unnecessary charges in the photodiode are completely disposed of on the substrate side -2 using the vertical overflow drain structure.

Next, during a period Tve corresponding to the vertical blanking period of a standard telephony system such as NTSC, the pixel signals of all photodiodes are simultaneously transferred to the vertical charge transfer paths L1 to L.
1 transfer pixel, and during periods T, l, l corresponding to the next horizontal blanking period, transfer the pixel signal of the transfer pixel closest to the horizontal charge transfer path 8 to the horizontal charge transfer path 8, Next, the horizontal scanning period (so-called IH period)
During the period T I H corresponding to , the horizontal charge transfer path 8
The pixel signals of the first row are read out by horizontally transferring the pixel signals of one row.

Then, in a period Ti corresponding to the next horizontal blanking period, the pixel signals of the next row from the vertical charge transfer paths L1 to L are transferred to the horizontal charge transfer path 8, and then in the next horizontal scanning period. During the corresponding periods T and A, pixel signals in the second row are read out by performing horizontal transfer through the horizontal charge transfer path 8.

Furthermore, the pixel signals of the third row are read out during each period THB and TIN corresponding to the next horizontal blanking period and horizontal scanning period. Then, the pixel signals of the remaining rows are read out in order by repeating the same process, and finally all the pixel signals corresponding to one picture of one frame are read out.

Next, the scanning readout operation will be described in detail based on the timing chart for each drive signal and timing signal shown in FIG. Note that the period T1 in FIG. , corresponds to a vertical blanking period, period T He corresponds to a horizontal blanking period, and period T IN corresponds to a horizontal scanning period. In addition, the symbol "H" in the figure is 12 ports, "M" is O ports, and "L" is -
8 volts, "HH" equals the board voltage approximately 15-25
Indicates the voltage level of Porto.

First, the period T v a corresponding to the vertical blanking period
In this case, the timing signal φ□ goes to the “H” level at a predetermined time t2, and otherwise goes to the “M” level.
. is always at the "M" level, and the timing signal φ,3 is at the "H" level in synchronization with the timing signal φ□ being at the "H" level. All the drive signals 81 to So outputted from are always at "L" level.

Therefore, during this period T, the timing signal φ is at the "M" level. Accordingly, all N of the first drive circuit IO
MO3) transistor becomes conductive, and on the other hand, all the drive signals s, s, , s, -s of the third drive circuit 12 become "L" level, so all of the transistors in the second drive circuit 11 become conductive. The NMOS transistors become non-conductive, and all gate electrodes G, , G2 . ．． G, ,G, ,-G, ,
G2°G 3 nG 4 n is controlled by the first drive circuit IO.

That is, when the timing signals φ□ and φF8 are not at the "H" level, the odd-numbered gate electrodes GG, , G, .
, 03□~G Is , gate signal φ applied to G 2c, I φ21 φi, φ, 2~φ1a φ
3 is equal to the "L" level signal VL (this signal is always set to 18 volts), and a potential barrier is generated in the vertical charge transfer paths L1 to L under these gate electrodes. .

On the other hand, even-numbered gate electrodes G 21 , G41 ,
Gate signals φ21φ41. applied to G22G42 to G2m and G4m. φ, 2 φ42~φ, φ4.
．． becomes equal to the "M" level signal φ□, and transfer pixels are generated in the vertical charge transfer paths L1 to L under these gate electrodes.

Therefore, all of the transfer gate 'rgi::adjacent portions (see FIG. 3) become transfer pixels, and these transfer pixels are separated by a potential barrier.

In this state, when timing signals φ8 and φF5 go to “H” level at a predetermined time t2, all np
n) Runstar Q2. ．． Q, , Q6 become conductive, and even-numbered gate electrodes G2G 41 , G22
, G42 to G2n, and G4n, an "H" level voltage of about 12 volts is applied, so all the transfer gates Tg become conductive, and the pixel signals of all the photodiodes are transferred to the adjacent transfer pixels.

Incidentally, as explained with reference to the timing of FIG. 6, the exposed surface is completed just before time t2, and the process of discarding unnecessary charges is also completed.

In this way, during the period T vn, a so-called field shift operation is performed, and as shown at time t2 in FIG. be transferred. Note that FIG. 11 shows the charge transfer operation of one vertical charge transfer path.

Next, period III corresponds to the first horizontal blanking period.
In IT, , the timing signal φ. All NMO3t in the first drive circuit 10 is always at "L" level.
- The transistor becomes non-conducting and is isolated from all gate electrodes.

On the other hand, the drive signal S at the first output terminal of the third drive circuit I2 is at "M" level, and the other drive signals 82 to S are "
By reaching the L'' level, only the first coarse NMOS transistors m ++ , m 21 , m 3m4I related to the drive signal S1 in the second drive circuit 11 become conductive.

During the period when the drive signal S is at the "M" level, a four-phase timing signal φ for performing vertical charge transfer is generated.
1 φ2 φ3 φ4 are input to the second drive circuit 11, so that the first to fourth gate signals φ13.
φ21 φ31 Only φ41 or timing signal φ1
φ2 φ3. is equal to φ4, and the first to
Fourth gate electrode Gz, G21. Gff
1, G<+, a charge transfer operation is performed. still,
Each signal waveform during this period T88 (time = period M from ts to t4) is shown in an enlarged manner in FIG.

As a result, the signal charges are equal to the gate signals φ1 and φ in FIG.
21 φ31 φ4, timing (sign 12,
3. 4. 5. 6. 7))
As in the first transfer shown in FIG. 1, the pixel signal q1 of the first row closest to the horizontal charge transfer path 8 is transferred to the horizontal charge transfer path 8, and The pixel signal q2 of the second row moves to the position of the first row.

Next, the first horizontal scanning period T, (times t4 to t5
(period), the signal to the gate electrode stops changing, and on the other hand, the horizontal charge transfer path 8 changes in synchronization with the gate signals α1 to α4 at a predetermined timing according to the four-phase drive force type or the two-phase drive force type. By performing horizontal transfer, pixel signals for the first row are read out.

Next, in the period from time t5 to t7, time t, ~t5
By repeating the same operation as above, pixel signals of the next row are read out. However, during the horizontal blanking period THB from time t to t4, the drive signal S of the third drive circuit I2
1 and 82 "M" at the same time and the remaining drive signals 83~
S6 or "L" level. Incidentally, the waveforms of each gate signal during this period THB are shown in an enlarged manner in FIG.

As a result, the first to fourth gate electrodes G l
1' = 041 and the fifth to eighth data l-electrodes 012 to G4□ or the timing signals φ1 to φ4
The pixel signals under these gate electrodes are vertically transferred.

That is, according to the timing shown in the ninth factor, as shown in the second vertical scan in FIG.
, are transferred to the horizontal charge transfer path 8, and the third row q3 or two rows and the fourth row q4 or one row are transferred to the horizontal charge transfer path 8 side.

Then, during the horizontal scanning period TIN from time t to t7, the horizontal charge transfer path 8 reads out the pixel signal q2 of the second row.

Next, when the third scanning readout is started from time t7, the drive signals S1, S2 and S of the third drive circuit I2 are
M'' becomes a bell, and the remaining drive signals 84~So or “L”
level, so the 1st to 12th gate electrodes of the 1st to 3rd sets G to G 41.012 to G4□, G I
Vertical charge transfer is performed by ff~G43. Therefore, like the third transfer in FIG. 11, the pixel signal q of the third row is transferred to the horizontal charge transfer path 8, and the pixel signal Q4 of the fourth to seventh rows are transferred. One row of each of qs, qs, and q- is transferred to the horizontal charge transfer path 8 side.

Then, the pixel signal q of the third row is read out by the horizontal charge transfer path 8.

Thereafter, each time the pixel signals of each row are read out, the drive signals 84 to So of the third drive circuit I2 are inverted to "M" in order, and the gate electrodes to be driven are inverted four by four. As shown in FIG. 10, all gate signals φ1. .about..phi.4o has a waveform equal to the timing signal .phi..about..phi.4, and the pixel signals of the last row can be read out in the final scanning readout.

FIG. 12 shows potential profiles of vertical charge transfer operations in arbitrary order, that is, the 1st and +1st vertical charge transfer operations. As the interval between empty transfer pixels increases, pixel signals are read out in order from the side closest to the horizontal charge transfer path 8.

As described above, according to this embodiment, pixel signals corresponding to a frame image can be read out by one frame scanning readout.

Furthermore, in this embodiment, since the width of the even-numbered gate electrodes is made wider than the width of the odd-numbered gate electrodes, it is possible to increase the charge retention capacity of the transfer pixel adjacent to the transfer gate, and also to increase the charge retention capacity during vertical charge transfer. Since charge is always transferred in the transfer pixel under the even-numbered gate electrode, the transfer efficiency is improved.

In this embodiment, during the period THa corresponding to each horizontal blanking period, the four-phase timing signals φ, ~φ4
The charge transfer may be performed in synchronization with the number of phases, or the gate electrodes may be driven in accordance with the number of phases using an appropriate number of timing signals of four or more phases.

〔Effect of the invention〕

As explained above, according to the charge-coupled solid-state imaging device of the present invention, exposure is performed using a group of photoelectric conversion elements corresponding to pixels, and pixel signals generated in these photoelectric conversion elements are transferred to a vertical charge transfer path and a horizontal charge transfer path. Since it can be read out by full frame scanning readout via the transfer path, a clear or still image can be provided.

In addition, charge coupling has a so-called electronic shutter function that applies an appropriate voltage to the semiconductor substrate, discards unnecessary charges to the semiconductor substrate side, and performs exposure from the point of discarding the charge, and can perform full-frame scanning readout. It is possible to provide a type solid-state imaging device.

In addition, the most efficient transfer is achieved by generating transfer vixels and potential barriers between a pair of gate electrodes that are adjacent to each other to avoid charge mixing, resulting in the highest vertical resolution. It provides an effective means to improve one's performance.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an electronic still camera to which a charge-coupled solid-state imaging device according to an embodiment of the present invention is applied, FIG. 2 is a schematic configuration diagram of a charge-coupled solid-state imaging device according to an embodiment, and FIG. An explanatory diagram showing the main part structure and peripheral circuit configuration of the light receiving area in the example, FIG. 4 is a longitudinal cross-sectional view taken along the line X-X in FIG. 3, and FIG. 6 is an explanatory diagram schematically showing the scanning readout operation of the embodiment; FIG. 7 is a timing chart showing the scanning readout operation of the embodiment in detail; FIGS. 8, 9, and Fig. 10 is a timing chart showing an enlarged view of the main timing in Fig. 7, Fig. 11 is a diagram conceptually showing the charge transfer operation during scanning readout, and Fig. 12 is a diagram showing charge transfer during scanning readout. Figure 13 is a structural diagram showing the main structure of a conventional charge-coupled solid-state imaging device. Figure 14 is an explanatory diagram showing the operation of conventional scanning readout using a potential profile. It is. Symbols in the figure: 1: Imaging optical system 2, mechanical aperture mechanism 3, charge-coupled solid-state imaging device 4, signal processing circuit 5: recording mechanism 6, synchronization control circuit 7, light receiving area 8: horizontal charge transfer path 9 , output amplifiers 10, 11, 12; drive circuits L1 to L, , vertical charge transfer path M, 1. M2□, M2I, M4I ~; NMOS transistor m2 mff+ ~; NMO3h transistor G. 041~ Gate Electrode Procedure Amendment August 9, 1990 Patent Character Chomiya 1, Case Indication 1990 Patent 1! J No. 1'', No. 8654 2, Name of the invention Solid-state imaging device 3 Relationship with the case by the person making the amendment Name of the person issuing the license (520) Fuji Photo Film Co., Ltd. 4, Agent 5, Date of amendment order = ( 6. Subject of amendment Description and drawings

Claims (1)

[Claims] A plurality of photoelectric conversion elements corresponding to pixels are arranged in a matrix in the row and column directions, and a vertical charge transfer path is formed adjacent to each group of photoelectric conversion elements arranged in the column direction. After the signal is transferred to the vertical charge transfer path, the pixel signal is vertically transferred for each row by supplying a gate signal at a predetermined timing to the gate electrode of the vertical charge transfer path, and the pixel signal for each row is transferred by the horizontal charge transfer path. In a charge-coupled solid-state imaging device that scans and outputs signals, a switch element is provided for each transfer gate electrode between each vertical transfer gate electrode and a drive signal electrode provided in pairs adjacent to each of the photoelectric conversion elements. a set of a predetermined number of gate electrodes in order from the gate electrode on the horizontal charge transfer path side, turn on the switch element, and sequentially at every cycle of transferring the pixel signal to the horizontal charge transfer path for each row. A drive circuit that generates a drive signal corresponding to each set is provided in A charge-coupled solid-state imaging device that performs full-frame scanning readout by performing charge transfer.