JPH0469426B2 - - Google Patents
Info
- Publication number
- JPH0469426B2 JPH0469426B2 JP58109531A JP10953183A JPH0469426B2 JP H0469426 B2 JPH0469426 B2 JP H0469426B2 JP 58109531 A JP58109531 A JP 58109531A JP 10953183 A JP10953183 A JP 10953183A JP H0469426 B2 JPH0469426 B2 JP H0469426B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive lead
- protruding electrode
- protruding
- semiconductor element
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Collation Of Sheets And Webs (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は可撓性フイルムとそれに固着した多数
の導電リードから成るフイルムキヤリアと、多数
の突起電極を有する半導体素子を熱圧着によつて
接続するいわゆるギヤングボンデイング方式の半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a film carrier consisting of a flexible film and a large number of conductive leads fixed thereto, and a semiconductor element having a large number of protruding electrodes, which are connected by thermocompression bonding. The present invention relates to a semiconductor device using a gigantic bonding method.
従来例の構成とその問題点
通常、半導体素子内の配線は信号ラインと電源
ラインに大別されるが、大電流を必要とする半導
体素子の場合、配線抵抗による電圧降下が問題と
なる。通常、半導体素子内の配線はスパツタリン
グや真空蒸着で形成するため、その配線を厚くす
ることは工業的に不可能であり、したがつてその
電圧降下を許容限度内に抑えるために半導体素子
で電源ラインの配線幅を広くしたり、多層配線を
採用するといつた対策がとられているが、前者の
対策は素子面積の増大を招き、後者の対策は製造
工程数が増加するばかりでなく配線構造が複雑に
なり、歩留りを下げるという欠陥がある。Conventional Structures and Their Problems Usually, wiring within a semiconductor device is broadly divided into signal lines and power supply lines, but in the case of semiconductor devices that require a large current, voltage drop due to wiring resistance becomes a problem. Normally, wiring within a semiconductor device is formed by sputtering or vacuum evaporation, so it is industrially impossible to make the wiring thick. Countermeasures have been taken such as widening the line wiring width and adopting multilayer wiring, but the former method increases the device area, while the latter method not only increases the number of manufacturing steps but also increases the wiring structure. The disadvantage is that it becomes complicated and reduces yield.
そこで、大電流を必要とする半導体素子におい
て前記のコストアツプを招く対策を取ることな
く、しかも電源ラインの電圧降下を小さくするこ
とが可能なギヤングボンデイング方式の半導体装
置が提案されている。 Therefore, a semiconductor device using a giant bonding method has been proposed, which is capable of reducing the voltage drop in the power supply line without taking the above-mentioned cost-increasing measures for semiconductor elements that require a large current.
このようなギヤングボンデイング方式の半導体
装置の従来例を第1図a及びbに示す。第1図b
は第1図aのA−A′断面図である。 A conventional example of such a gigantic bonding type semiconductor device is shown in FIGS. 1a and 1b. Figure 1b
is a sectional view taken along line A-A' in FIG. 1a.
半導体素子1の周辺部に設けられた突起電極2
にベースフイルム4から伸延したそれとでフイル
ムキヤリアを構成する導電リード3が接続され
る。また、電源ライン用の突起電極6,6a及び
6bを半導体素子1の内部及び周辺部に設け、ベ
ースフイルム4から伸延した導電リード5及び5
aをこの突起電極6,6a及び6bに接続する。
この一連の接続は第1図bに示すボンデイングツ
ール7でもつて突起電極2,6,6a及び6bと
導電リード3,5及び5aを同時に熱圧着するこ
とでなされる。 Protruding electrodes 2 provided on the periphery of the semiconductor element 1
A conductive lead 3 extending from the base film 4 and forming a film carrier is connected to the base film 4. Further, protruding electrodes 6, 6a and 6b for power supply lines are provided inside and around the semiconductor element 1, and conductive leads 5 and 5 extending from the base film 4 are provided.
A is connected to the protruding electrodes 6, 6a and 6b.
This series of connections is made by simultaneously thermocompressing the protruding electrodes 2, 6, 6a and 6b and the conductive leads 3, 5 and 5a using the bonding tool 7 shown in FIG. 1b.
尚、突起電極6bは半導体素子1の内部へ伸延
した導電リード5と半導体素子1の端面部分の電
気的短絡(以下エツジタツチと称す)の発生を防
止する役割を持つ。 Incidentally, the protruding electrode 6b has the role of preventing the occurrence of an electrical short circuit (hereinafter referred to as an edge touch) between the conductive lead 5 extending into the interior of the semiconductor element 1 and the end face portion of the semiconductor element 1.
この第1図の従来例により、電源ラインの取出
しを半導体素子1の内部及び周辺部で、かつ任意
の複数の場所で行える。また、導電リード5,5
aは通常18μm,35μmの銅箔を用いるため、コ
ストアツプを招かずに電圧降下を無視できる効果
がある。 According to the conventional example shown in FIG. 1, the power supply line can be taken out inside and around the semiconductor element 1 at any number of locations. In addition, the conductive leads 5, 5
Since copper foil of 18 .mu.m or 35 .mu.m is normally used for a, the voltage drop can be ignored without increasing costs.
しかし、突起電極6と突起電極6b間に導電リ
ード5が、また突起電極6と突起電極6a間に導
電リード5aが接続されることにより、半導体素
子1の主材料(通常Si)と導電リード5及び5a
の主材料(通常Cu)の熱膨張係数の違いによる
熱ストレスが発生し、突起電極6,6a及び6b
の剥離や、導電リード5及び5aが剥離または断
線するといつた問題がある。 However, by connecting the conductive lead 5 between the protruding electrode 6 and the protruding electrode 6b and the conductive lead 5a between the protruding electrode 6 and the protruding electrode 6a, the main material of the semiconductor element 1 (usually Si) and the conductive lead 5 are connected. and 5a
Thermal stress occurs due to the difference in the coefficient of thermal expansion of the main material (usually Cu) of the protruding electrodes 6, 6a and 6b.
There are problems such as peeling of the conductive leads 5 and 5a, and peeling or disconnection of the conductive leads 5 and 5a.
発明の目的
本発明はこのような従来例の欠点を除去すべく
なされたものであり、コストアツプを招くことな
く、各材料の熱膨張係数の違いによる熱ストレス
の問題を完全に解決できる半導体装置を提供しよ
うとするものである。Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional examples, and provides a semiconductor device that can completely solve the problem of thermal stress caused by the difference in coefficient of thermal expansion of each material without increasing costs. This is what we are trying to provide.
発明の構成
この目的を達成するために本発明における半導
体装置は、周辺部及び内部それぞれに複数個の突
起電極を形成した半導体素子と、前記周辺部の突
起電極にそれぞれ接続される複数本の第1の導電
リード及び前記内部の突起電極に接続される第2
の導電リードを可撓性のベースフイルムに形成し
たフイルムキヤリアとを具備し、前記半導体素子
の周辺部の突起電極に並設されるように、第2の
導電リードをこの第2の導電リードに接続するこ
となく支持するダミーの突起電極を設け、前記第
2の導電リードの先端部を前記内部の突起電極に
対応して複数に分岐させてそれぞれ突起電極に接
続したものである。この構成によれば、第2の導
電リードと半導体素子端面との電気的短絡を前記
のダミーの突起電極によつて防止し、かつ第2の
導電リードとダミーの突起電極が接続されないこ
とにより、熱ストレスによる第2の導電リードの
切断や、第2の導電リードに接続される突起電極
の剥離といつた問題の発生を防止することができ
る。Structure of the Invention In order to achieve this object, a semiconductor device according to the present invention includes a semiconductor element in which a plurality of protruding electrodes are formed in each of the peripheral part and the inside thereof, and a plurality of protruding electrodes each connected to the protruding electrodes in the peripheral part. a second conductive lead connected to the first conductive lead and the internal protruding electrode;
a film carrier in which a conductive lead is formed on a flexible base film, and a second conductive lead is attached to the second conductive lead so as to be arranged in parallel with the protruding electrode on the periphery of the semiconductor element. A dummy protruding electrode is provided to support without being connected, and the tip of the second conductive lead is branched into a plurality of parts corresponding to the internal protruding electrodes, each of which is connected to the protruding electrode. According to this configuration, an electrical short circuit between the second conductive lead and the end face of the semiconductor element is prevented by the dummy protruding electrode, and the second conductive lead and the dummy protruding electrode are not connected. It is possible to prevent problems such as breakage of the second conductive lead and peeling of the protruding electrode connected to the second conductive lead due to thermal stress.
実施例の説明
以下、本発明の一実施例を第2図a及び第2図
bで説明する。第2図bは第2図aのA−A′断
面図である。また、従来例と同一箇所には同一番
号を付してある。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 2a and 2b. FIG. 2b is a sectional view taken along line A-A' in FIG. 2a. Also, the same numbers are given to the same parts as in the conventional example.
半導体素子1の周辺部に設けられた突起電極2
にベースフイルム4から伸延したそれとでフイル
ムキヤリアを構成する導電リード3が接続され
る。また、電源ライン用の導電リード8はベース
フイルムから半導体素子1の内部へと伸延し、先
端部を突起電極6に対応して分岐させ、そのそれ
ぞれの先端部を半導体素子1の内部に設けられた
突起電極6及び6aに接続する。ここで、導電リ
ード8の下部で、かつ半導体素子1の周辺部の位
置にダミーの突起電極6bを設ける。このダミー
の突起電極6bは突起電極2,6及び6aと同じ
製造工程で形成される突起電極であり、エツジタ
ツチ防止に有効である。 Protruding electrodes 2 provided on the periphery of the semiconductor element 1
A conductive lead 3 extending from the base film 4 and forming a film carrier is connected to the base film 4. Further, the conductive lead 8 for the power supply line extends from the base film into the inside of the semiconductor element 1, has a tip end branched corresponding to the protruding electrode 6, and has each tip end provided inside the semiconductor element 1. It is connected to the protruding electrodes 6 and 6a. Here, a dummy protruding electrode 6b is provided below the conductive lead 8 and at a position around the semiconductor element 1. This dummy protruding electrode 6b is a protruding electrode formed in the same manufacturing process as the protruding electrodes 2, 6, and 6a, and is effective in preventing edge touching.
以上の突起電極2と導電リード3、突起電極6
及び6aと導電リード8は第3図bに示すボンデ
ングツール10によつて同時に熱圧着される。 The above protruding electrode 2, conductive lead 3, and protruding electrode 6
6a and the conductive lead 8 are simultaneously bonded by thermocompression using a bonding tool 10 shown in FIG. 3b.
しかし、導電リード8とダミーの突起電極6b
は第3図に示すように先端部に凹み部分10を設
けたボンデイングツール9を用いることによつ
て、熱圧着されない。 However, the conductive lead 8 and the dummy protruding electrode 6b
is not thermocompression bonded by using a bonding tool 9 having a concave portion 10 at its tip as shown in FIG.
以上説明した本具体例の構造にすることによ
り、エツジタツチを防止できる以外に、突起電極
6と突起電極6a間は湾曲した導電リード8によ
つて接続され、突起電極6とダミーの突起電極6
b間は機械的に接続されないため、半導体素子1
と導電リード8の熱膨張係数の違いによる熱スト
レスが湾曲部とダミーの突起電極6bで吸収さ
れ、突起電極6及び6aの剥離、または導電リー
ド8の断線は発生しない。 By adopting the structure of this specific example as described above, in addition to being able to prevent edge touching, the protruding electrode 6 and the protruding electrode 6a are connected by the curved conductive lead 8, and the protruding electrode 6 and the dummy protruding electrode 6 are connected by the curved conductive lead 8.
Since there is no mechanical connection between
Thermal stress due to the difference in coefficient of thermal expansion between the conductive lead 8 and the curved portion is absorbed by the curved portion and the dummy protruding electrode 6b, so that peeling of the protruding electrodes 6 and 6a or disconnection of the conductive lead 8 does not occur.
発明の効果
以上説明した本発明の具体例を実施することに
より、フイルムキヤリアの製造工程及び熱圧着に
おける工数を従来のままで、消費電力が大なる半
導体装置でも半導体素子の面積を大とすることな
く、配線による電圧降下を抑えることが可能な半
導体装置を提供することができる。そして、従来
問題であつたエツジタツチや、各材料の熱膨張係
数の違いによる熱ストレスの問題を完全に解決で
きるという大きな利点が得られる。Effects of the Invention By implementing the specific example of the present invention described above, it is possible to increase the area of a semiconductor element even in a semiconductor device with high power consumption while keeping the number of man-hours in the film carrier manufacturing process and thermocompression bonding the same as before. Therefore, it is possible to provide a semiconductor device that can suppress voltage drop due to wiring. Furthermore, a great advantage can be obtained in that the conventional problem of edge contact and thermal stress caused by differences in the coefficient of thermal expansion of each material can be completely solved.
尚、実施例の説明では電源用配線について記述
したが、本発明は信号用配線についても適用でき
ることは明らかである。 Although the embodiments have been described with respect to power supply wiring, it is clear that the present invention can also be applied to signal wiring.
第1図aは従来の半導体素子内へ導電リードを
伸延したギヤングボンデイング方式の半導体装置
を示す平面図、第1図bは第1図aのA−A′断
面図、第2図aは本発明の半導体装置の一実施例
を示す平面図、第2図bは第2図aのA−A′断
面図、第3図は本発明の半導体装置に用いるボン
デイングツールの先端形状を示す図である。
1……半導体素子、2……周辺部の突起電極、
3……第1の導電リード、4……ベースフイル
ム、6,6a……内部の突起電極、6b……ダミ
ーの突起電極、8……第2の導電リード。
FIG. 1a is a plan view showing a conventional semiconductor device using a guy-young bonding method in which conductive leads are extended into a semiconductor element, FIG. 1b is a sectional view taken along line A-A' in FIG. 1a, and FIG. 2a is a A plan view showing an embodiment of the semiconductor device of the present invention, FIG. 2b is a sectional view taken along the line A-A' in FIG. 2a, and FIG. 3 is a diagram showing the tip shape of a bonding tool used in the semiconductor device of the present invention It is. 1...Semiconductor element, 2...Protruding electrode in the peripheral area,
3...First conductive lead, 4...Base film, 6, 6a...Internal protruding electrode, 6b...Dummy protruding electrode, 8...Second conductive lead.
Claims (1)
を形成した半導体素子と、前記周辺部の突起電極
にそれぞれ接続される複数本の第1の導電リード
及び前記内部の突起電極に接続される第2の導電
リードを可撓性のベースフイルムに形成したフイ
ルムキヤリアとを具備し、前記半導体素子の周辺
部の突起電極に並設されるように、第2の導電リ
ードをこの第2の導電リードに接続することなく
支持するダミーの突起電極を設け、前記第2の導
電リードの先端部を前記内部の突起電極に対応し
て複数に分岐させてそれぞれ突起電極に接続した
半導体装置。1. A semiconductor element in which a plurality of protruding electrodes are formed on each of the peripheral part and the inside, a plurality of first conductive leads respectively connected to the protruding electrodes in the peripheral part, and a second conductive lead connected to the protruding electrodes in the inside. a film carrier in which a conductive lead is formed on a flexible base film, and a second conductive lead is attached to the second conductive lead so as to be arranged in parallel with the protruding electrode on the periphery of the semiconductor element. A semiconductor device, wherein a dummy protruding electrode is provided to support without being connected, and the tip of the second conductive lead is branched into a plurality of parts corresponding to the internal protruding electrodes, each of which is connected to the protruding electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58109531A JPS601968A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58109531A JPS601968A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS601968A JPS601968A (en) | 1985-01-08 |
| JPH0469426B2 true JPH0469426B2 (en) | 1992-11-06 |
Family
ID=14512610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58109531A Granted JPS601968A (en) | 1983-06-17 | 1983-06-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS601968A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3269171B2 (en) * | 1993-04-08 | 2002-03-25 | セイコーエプソン株式会社 | Semiconductor device and clock having the same |
| JP3577913B2 (en) | 1997-02-27 | 2004-10-20 | セイコーエプソン株式会社 | Semiconductor device and electronic equipment including the same |
| US7157790B2 (en) * | 2002-07-31 | 2007-01-02 | Microchip Technology Inc. | Single die stitch bonding |
| US7326594B2 (en) | 2002-07-31 | 2008-02-05 | Microchip Technology Incorporated | Connecting a plurality of bond pads and/or inner leads with a single bond wire |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53123074A (en) * | 1977-04-01 | 1978-10-27 | Nec Corp | Semiconductor device |
-
1983
- 1983-06-17 JP JP58109531A patent/JPS601968A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS601968A (en) | 1985-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3232965B2 (en) | Method for manufacturing flexible photoelectric conversion device and flexible photoelectric conversion device | |
| JPH0513967A (en) | Semiconductor memory control device and high-density mounting method thereof | |
| JP3033227B2 (en) | Semiconductor device | |
| WO1998010625A1 (en) | An integrated circuit package | |
| JP2828056B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100488324B1 (en) | an integrated circuit package | |
| JPH0469425B2 (en) | ||
| JPS61278160A (en) | Connector for semiconductor integrated circuit | |
| JPS601968A (en) | Semiconductor device | |
| JPH01298731A (en) | Semiconductor device | |
| JP2819825B2 (en) | Semiconductor device with built-in TAB | |
| JPH05107551A (en) | LCD display panel wiring structure | |
| JP2000183216A (en) | Semiconductor device | |
| JP3450590B2 (en) | Terminal connection structure of integrated circuit | |
| JPH04199563A (en) | Package for semiconductor integrated circuit | |
| JP3337781B2 (en) | Lead frame and TAB tape | |
| JP3925280B2 (en) | Manufacturing method of semiconductor device | |
| JPS63221380A (en) | Construction of terminal section | |
| JP2766361B2 (en) | Semiconductor device | |
| JPS63104435A (en) | Semiconductor device | |
| JP2768336B2 (en) | Semiconductor device | |
| JP2568822B2 (en) | Semiconductor device | |
| JP2002131772A (en) | Structure of liquid crystal display device | |
| JP2634942B2 (en) | Semiconductor device | |
| JPH0312527Y2 (en) |