JPH0469452B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse generator, and particularly to a pulse generator suitable for generating pulses synchronized with a control signal of a reference frequency.

[Background of the invention]

In a digital circuit, a circuit output pulse is generated in synchronization with the pulse timing of an input clock pulse (hereinafter abbreviated as clock), and the operation and stop of the pulse generation operation is controlled by input to the circuit. Circuit blocks that can be controlled in synchronization with signal pulses are often used.

FIG. 1 shows an example of the circuit block T
This shows a flip-flop (hereinafter abbreviated as TFF).
CK is a clock input terminal, and the circle on the terminal is TFF.
is the falling edge of input clock 1 (transient part where the logic level changes from “1” level to “0” level)
This shows that it works.

In FIG. 2, the operation of the TFF shown in FIG. 1 and its problems will be explained. Figure 2 1 is the clock, 2 is Figure 1
The reset pulse 3 input to the reset terminal R of the TFF is the waveform of the output pulse from the output terminal Q of the TFF. When reset pulse 2 is at “1” level, TFF stops operating and output 3 is at “0” level.
maintained at the level. When the reset pulse 2 is at the "0" level, the TFF is activated and generates an output whose logic level is inverted every falling edge of the clock 1.

Here, if reset pulse 2 has a falling phase as shown by the solid line in FIG. 2, the Q output will have the waveform shown in FIG. In the case of such a falling phase, the Q output has the waveform shown in FIG. 2, 3'.

In general, in digital circuits, clock 1 and reset pulse 2 are often generated separately from a common high-frequency reference clock, but even in such cases, the difference in the number of logic gate stages in the process of generating each pulse Or, due to differences in the characteristics of the logic circuit elements used, it is difficult to design and manufacture the phase relationship between clock 1 and reset pulse 2 as desired, or to ensure stability against fluctuations in temperature, power supply voltage, etc. It is often difficult to maintain

Therefore, if the falling edge of reset pulse 2 and the falling edge of clock 1 coincide, the operation of the TFF becomes unstable and the Q output becomes
3 and 3' are repeated alternately every time reset pulse 2 is repeated. Alternatively, even if the falling phase of reset pulse 2 slightly oscillates around the falling phase of clock 1 due to the influence of ripples in the power supply voltage, etc., the falling phase of reset pulse 2 On the other hand, a fluctuation occurs in the generated phase of the Q output such that the generated phase jumps by a time corresponding to one cycle of the clock.

In other words, depending on the phase relationship between reset pulse 2 and clock 1, TFF reset pulse 2 and Q
There is a possibility that the phase relationship with output 3 may become unstable.

Here, for example, the reset pulse 2 is the horizontal synchronizing signal of the television signal (or a pulse having a constant phase relationship with the horizontal synchronizing signal), and the reset pulse 3 is the operating clock of the digital memory or the horizontal scanning operating clock of the solid-state image sensor. In such a case, the phase (time) relationship between the video signal read from the memory or image sensor and the horizontal synchronization signal varies with each horizontal scanning period, and the output of the memory device or solid-state image sensor may This causes a jitter phenomenon in which the image reproduced on the cathode ray tube surface of the monitor device shifts left and right for each scanning line.

As a means for preventing the above-described unstable phenomenon, there is a conventional example described in Japanese Patent Laid-Open No. 57-42236.
The operating principle of this conventional example will be explained with reference to FIG. In the conventional example, it is detected that the fall of the reset pulse 2 with respect to the clock 1 enters the phase range shown in FIG. 3r, and the clock is automatically switched from the clock 1 to the clock 1'. After the clock is switched, the output 3 remains stable as shown in FIG. 3 even with slight phase fluctuations of the reset pulse 2.

In the conventional example, after the clock 1' is selected by the above switching, the falling position of the reset pulse 2 changes greatly, and the r shown in the waveform of 1' changes.
When the clock enters the phase phase of , clock switching is performed again and the clock is switched from 1' to 1.

By the way, in the conventional example, it is necessary to provide the above-mentioned phase detection resistor r, but the value of r (time value) must be set to a sufficiently small value with respect to the clock period T in FIG. 3. This is because, if r has a time value greater than T/2, for example, r for clock 1 and r for clock 1' will overlap in FIG. This is because, as a result, clocks 1 and 1' are constantly switched, and the phase of output 3 becomes unstable. Even if r is less than T/2, r for clock 1 and clock 2
If there is not a sufficient interval between r and r, a slight phase vibration of the reset pulse 2 will cause output phase instability as described above.

In order to set r, a pulse delay circuit having a delay time of r is provided in the conventional example. As a pulse delay circuit with a minute delay time, a circuit in which logic gates (inverters, etc.) are connected in series in multiple stages is generally used.

However, in such delay circuits, the delay time varies widely due to manufacturing variations, or due to variations in temperature, power supply voltage, etc., so the smaller the required value of r, the more difficult it is to design. , manufacturing becomes difficult.

For the above reasons, the repetition frequency of the clock 1 becomes high, and therefore, when T in FIG. 3 is small, it becomes difficult to implement the conventional method. Therefore, a method is desired that does not require generation of a minute and highly accurate pulse delay time r.

[Purpose of the invention]

The present invention provides a pulse generator that can always maintain a desired constant phase relationship between a clock and a control signal pulse, and can therefore prevent the phenomenon of unstable phase of output pulses of flip-flops and the like that operate using these pulses. It is on offer.

[Summary of the invention]

The gist of the present invention is to provide a pulse phase delay means for a control signal pulse or a clock, the delay means having a structure in which the delay time can be varied by external control,
The delay time of the delay means is automatically controlled so that the phase of the control signal pulse relative to the clock is maintained at a certain constant phase.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 401 in FIG. 4 is a TFF, and clock 1 is input to the clock terminal CK. On the other hand, TFF401
A pulse 2' obtained by phase-delaying the input reset pulse 2 by a phase delay circuit 402 is input to the reset terminal R of the circuit. At the same time, pulse 2' is applied to the reset terminal R of the TFF 403, and pulse 40, whose polarity is inverted by the inverter 44, is applied to the clock terminal CK of the clock 1.
Enter 5.

The Q output 406 of TFF403 is input to the D terminal of a D type flip-flop (hereinafter abbreviated as DFF) 407, and the Q output 3 of TFF401 is input to the D type flip-flop (hereinafter abbreviated as DFF) 407.
Input to clock terminal CK of 7.

FIG. 5 shows operational waveforms of each part of the embodiment shown in FIG.
The reset pulse 2' input to R of TFFs 401 and 403 is φ with respect to clock 1,405.
When there is a fall between the phase indicated by 1 and the phase indicated by φ2, the Q output 3 of the TFF 401 and the Q output 406 of the TFF 403 are respectively shown in Fig. 5 3-1 and 406-.
1 waveform. At this time, if a DFF 407 that operates at the falling edge of the clock is used, the D input 406 -
Since 1 is always at the “1” level, DFF407
The Q output 408 of is at the "1" level as shown in FIG. 5 408-1.

Next, the reset pulse 2' is applied from φ2 to φ in FIG.
3, the Q output 406 of TFF403 and the Q output 3 of TFF401 are respectively 5th
The waveforms are as shown in Figures 406-2 and 3-2, and the clock 3
Since the D input 406-2 is always at "0" level at the rising edge of -2, the Q output 40 of the DFF 407
8 becomes the "0" level as shown in FIG. 5 408-2.

When the operation shown in FIG. 5 is viewed over a longer period, it becomes as shown in FIG. 6. In Figure 6, the reset pulse 2' is the 5th pulse.
A case with a falling phase indicated by φ2 in the figure is shown. At this time, the TFF 403 is in an unstable operation state with the phase of the output pulse as explained in the TFF operation in Fig. 1.
The Q output 406 repeats 406-1 and 406-2 in FIG. 5, and the output 408 becomes a "1" level or a "0" level.

A voltage 410 is obtained from the output 408 via the low-pass filter 409 in FIG.
02 delay time control voltage.

Although a configuration example using a resistor and a capacitor is shown as an example of the low-pass filter 409, other configurations may be used.

In addition, in the low-pass filter configuration example 409 in FIG. 4,
Connect a capacitor between the voltage 410 output terminal and the “0” level power line 411 (ground here), and between the voltage 410 output terminal and the “1” level power line 41
It is located between 2 rooms. As a result, when the power is turned on, the control voltage that can make the delay time of the phase delay circuit 402 near the center value of the variable value of the control voltage of the phase delay circuit 402 or the center value of the variable delay time of the phase delay circuit 402 Since it is possible to generate a voltage value close to the value as the initial voltage, operation can always be started at the center of the variable phase delay time cell. Phase fluctuations in the input reset pulse 2 due to temperature fluctuations after the power is turned on can be absorbed by increasing or decreasing the delay time of the phase delay circuit.
The above initial operation has the effect of ensuring a sufficiently wide absorbable phase fluctuation range.

The phase of reset pulse 2' changes from φ1 to φ in Figure 5.
2, the voltage value of the control voltage 410 increases toward the "1" level. Also φ2 and φ3
When between, the voltage drops towards the "0" level. When in phase φ2, the output 408 becomes “1” due to a very small phase shift in this vicinity.
Since the generation ratio of the level and the "0" level becomes variable, it becomes possible to maintain the control voltage 410 at a constant voltage level.

Therefore, if the phase delay circuit 402 has a characteristic that the delay time increases when the control voltage 410 becomes high, and the delay time decreases when the control voltage 410 becomes low, the reset pulse 2' is always set to the fifth pulse. Since the phase can be controlled to be as shown in the figure φ2, even if the falling phase of the input reset pulse 2 with respect to the clock 1 has initial variations or temperature fluctuations, the Q of the TFF 401 with respect to the reset pulse 2 can be controlled.
The generated phase of output 3 will not become unstable. In addition, as the phase delay circuit 402, a control voltage 410
As the control voltage 4 becomes lower, the delay time increases and the control voltage 4
If a device with a characteristic that the delay time decreases as 10 becomes higher is used, the reset pulse 2' is always set to φ in FIG.
1 or φ3, even if there are initial variations in the falling phase of input reset pulse 2 with respect to clock 1, or temperature fluctuations, TFF4 with respect to reset pulse 2
The generation phase of the Q output 406 of 03 does not become unstable.

In addition, in this embodiment, the reset pulse 2
pulse 4 for phase detection with respect to clock 1.
05 is used, but the pulse 405 is the inverter 40
4, there are no problems in design and manufacturing as in the conventional delay circuit for setting r.

An embodiment of the above phase delay circuit is shown in FIG.
701 is an inverter, and 702 is an OR circuit.
FIG. 8 shows the operation waveforms of each part in FIG. 7. The phase of the input pulse 2 is delayed by the integral characteristic of the resistor 703, the combined capacitance of the capacitor 704, and the variable capacitance diode 705, and the pulse shown in FIG. 8 is obtained at the inverter output 706. Here, the diode 705 has a characteristic that its capacitance value is variable depending on the applied reverse voltage, and the capacitance value decreases as the applied reverse voltage increases. Therefore, the capacitor 70
4 has a sufficiently larger capacitance than that of the diode 705, and the control voltage 41 is connected to the diode 705 via a high impedance resistor 707.
If 0 is applied, the higher the control voltage, the longer the delay time t
becomes smaller.

Although the pulse 706 in FIGS. 7 and 8 may be used as 2' in FIG. 4, in the present invention, only one pulse edge of the reset pulse (the pulse edge at which the operation of the flip-flop is started) is controlled in phase. If possible, OR circuit 70 in Figure 7
The output 708 of 2 may be designated as 2' in FIG.

FIG. 9 shows another embodiment of the voltage-controllable phase delay circuit 402. 901 and 902 are inverters,
903 is an OR circuit. 904 is P channel
MOS transistors 905 and 906 are N-channel MOS transistors. 904 and 906
The inverter is configured with 905 operates as a variable resistance element to vary the output impedance of the inverter composed of 904 and 906 when outputting a low level, and the higher the voltage 410 applied to the gate terminal, the lower the conduction resistance value.

Therefore, the input pulse 2 is phase-delayed by the resistance value of the MOS transistor 905 and the input end stray capacitance 907 of the inverter 901 or the input end stray capacitance 908 of the inverter 902, and becomes an inverter output 909. Inverter output 909 is a pulse having a phase similar to 706 in FIG. The OR circuit 903 and the output 910 are shown in FIG.
A pulse similar to 8 is obtained.

Here, 9 of the N-channel MOS transistor
From the above-mentioned characteristics of the gate terminal voltage 410 and conduction resistance value of 05, the control voltage 410 in the circuit of FIG.
The higher the value, the smaller the delay time of the pulse 909,
The characteristics are similar to those of the circuit shown in FIG.

Note that instead of connecting two N-channel MOS transistors in series as shown in Figure 9, two P-channel MOS transistors are connected in series,
It is also possible to use that one P-channel MOS transistor as an output impedance variable element. In this case, due to the characteristics of the MOS transistor, the delay circuit becomes such that the pulse delay time increases as the gate terminal voltage increases.

10 and 11 respectively show embodiments different from those in FIG. 4 according to the present invention, and FIG. 12 collectively shows their operating waveforms. In FIGS. 10 and 11, blocks having the same functions as those in FIG. 4 are given the same numbers.

Figure 10 shows the inverter 404 and TFF in Figure 4.
This is an example in which the DFF 101 is used instead of the DFF 403. A DFF 101 that operates at the rising edge of the clock is used, and clock 1 is input to the clock input terminal CK. Pulse 2' is input to the D input terminal. The output 102 of the DFF 101 outputs a "0" level if the D input is at a "1" level at the rising edge of the clock, and a "1" level if the D input is at a "0" level. Here, the falling phase of pulse 2' (waveform diagram shown in FIG. 12 2') in FIG. 10 with respect to clock 1 (waveform diagram shown in FIG. 12 1) in FIG. φ1 explained in
and φ2, the phase relationship between the DFF 101 and Q output 102 in FIG. 10 and the Q output 3 of the TFF 401 is as shown by the broken line a in FIG. 12.

Also, when the falling phase of pulse 2' with respect to clock 1 is between φ2 and φ3 in FIG.
The output 102 and the output 3 have the relationship shown by the broken line b in FIG. 12. Therefore, connect the Q output 3 of TFF401 to the D input of DFF407, and
Q output 102 of DFF101 is connected to the clock terminal CK of
If connected, Q output 408' will be "0" when pulse 2' and the falling edge are between φ1 and φ2 with respect to the phase relationship between clock 1 and pulse 2' explained in FIG.
level, and when it is between φ2 and φ3, “1”
level. In addition, the clock 1 similar to that shown in Fig.
If the phase relationship between and pulse 2' matches, that is, the rising edge of clock 1 and the falling edge of pulse 2', then
A phase instability phenomenon occurs between pulse 2' and the DFF output 102 similar to the case previously explained with TFF in FIG. 1, and as shown in FIG. The Q output of the DFF 101 is obtained such that the relationship becomes the state shown by the broken line a or the state shown by the broken line b. Therefore, as shown in FIG. 12 408', in the embodiment of FIG. 10, a DFF 407Q output whose polarity is inverted from that of FIG. 6 corresponding to the phase relationship between clock 1 and pulse 2' is obtained.

Therefore, the delay time of the phase delay circuit 402 increases as the control voltage 410 becomes lower;
If a control voltage 410 with a characteristic that the delay time decreases as it becomes higher is used, the reset pulse 2' can be controlled to always have the phase of φ2 in FIG. 5 using the phase detection pulse 408' obtained with the configuration shown in FIG. can. Therefore, the generation phase of the Q output 3 of the TFF 401' is stabilized in the same way as in the embodiment of FIG.

Figure 11 is a replacement for TFF401 in Figure 4.
TFF111 and J-K flip-flop (hereinafter J
- KFF) 112 is used.
The K terminal of J-KFF is connected to a power supply line 113 having a voltage value of "1" level. At this time J-
The Q output 114 of the KFF112 goes to the "1" level when the clock input to the clock terminal CK falls when the J terminal input is at the "1" level, and when the clock input to the J terminal is at the "0" level, When it falls, it becomes "0" level.

TFF111 has Q output 11 at the falling edge of pulse 2'.
5 goes to "1" level, but at the falling edge of clock 1 immediately after 115 goes to "1" level, J-
It is reset at the same time as the Q output 114 of KFF112 goes to "1" level, and the Q output 115 goes to "0".
Return to level. Therefore, this next clock 1
At the falling edge of , the Q output 114 of J-KFF returns to "0" level, and at the falling edge of the next pulse 2'.
The Q output 114 maintains the "0" level until the TFF 111 operates. In other words, the waveform becomes as shown in FIG. 12 114.

In Fig. 11, the D input of the DFF407 is the Q output 406 of the TFF403 similar to Fig. 4, and the DFF
Q output 11 of J-KFF as clock of 407
4, as is clear from FIG. 12, a phase detection pulse 408 having the same waveform characteristics as the embodiment of FIG. 4 can be obtained in this case as well. Therefore, if the phase delay circuit 402 has a characteristic that the delay time increases as the control voltage 410 becomes higher, and the delay time decreases as the control voltage 410 becomes lower, the first
The phase detection pulse 408 obtained with the configuration shown in FIG. 1 can control the phase delay circuit 402 in the same way as in FIG.
The generation phase of the Q output 114 of KFF can be stabilized.

In addition, FIGS. 4, 10, and 11 explained above
In addition to the configuration shown in the figure, other configurations may be used, for example, instead of the TFF401 in Figures 4 and 10, pulse 2' is used as the D input and the operation is performed at the falling edge of pulse 1.
Using DFF or TFF in Figures 4 and 11
TFF111, J- in Figure 11 instead of 403
The present invention can also be realized by a configuration using a KFF112 circuit.

Further, in the embodiment described above, the phase of pulse 2' is automatically controlled so that the falling edge of pulse 2' coincides with the rising edge of clock 1 (the phase of φ2 in FIG. 5). We have shown an example in which the output pulse of a flip-flop operates at the falling edge of , and uses pulse 2' as the control signal for operation and non-operation, so that the phase relationship between the control signal pulse 2' and the output pulse of the flip-flop is kept stable. In order to obtain the same pulse phase stabilization effect as in the embodiment, the falling edge of pulse 2' does not necessarily have to coincide with the rising edge of clock 1; in principle, it can be at any phase other than the falling phase of clock 1. It's okay. For example, in the embodiment shown in FIG. 4, if a pulse delay circuit with a delay time t ₁ (however, t ₁ is a time value smaller than one cycle of clock 1) is used instead of inverter 404, the fifth
In the figure, it is possible to automatically control the falling edge of pulse 2' to have a phase shifted to the right by _t1 from the phase of φ1, and even in this case, the phase relationship between the Q output of TFF401 and reset pulse 2' in Figure 4 is can be stabilized.

Furthermore, in the embodiments described above, an example was shown in which pulse 2 is delayed by phase delay circuit 402, but the present invention can also be implemented by configuring clock 1 to be delayed by phase delay circuit 402. Also,
The phase detection pulse generation circuit is also not limited to the DFF407.

FIG. 13 shows the same configuration as FIG. 4, but
The phase delay circuit 402 is used to delay the phase of the clock 1, and the fixed delay circuit 13 is used instead of the inverter 404.
1, instead of DFF407 TFF132,1
33, P channel MOS transistor 134,
An embodiment using a phase detection circuit composed of an N-channel MOS transistor 135 will be shown.

In the embodiment of FIG. 13, TFF 401 is operated by clock 1', TFF 403 is operated by clock 136 which is delayed by clock 1' by _t2 , and TFF 401,
403 is directly controlled by the input reset pulse 2. FIG. 14 shows the operation waveforms of each part in FIG. 13. TFF4 when pulse 2 has a phase between φ ₄ and φ ₃
Q output 406 of TFF 03 and Q output 3 of TFF401 have waveforms of 406-3 and 3-3, respectively, and when pulse 2 has a phase between φ ₃ and φ ₆ , output 40
It is clear from the explanation of FIGS. 4 and 5 that 6 and 3 have waveforms of 406-4 and 3-4, respectively.

Here, the polarity inversion pulse of the output 3 via the inverter 137 is inputted to the TFF 132 as a clock, and the output 406 is inputted as a reset pulse. Further, the polarity inversion pulse of the output 406 is inputted to the TFF 133 via the inverter 138 as a clock, and the output 3 is inputted as a reset pulse. At this time
The waveforms of the output 139 of TFF132 and the Q output 140 of TFF133 are 139 and 140 in FIG. 14, respectively.
It will be like 140.

As a result, when the pulse 2 is between φ ₄ and φ ₅ , the P-channel MOS transistor 134 is conductive and the N-channel MOS transistor 135 is non-conductive, so that the power supply line 113 at the “1” level is connected to the low-pass filter 409. Current flows in and the output voltage 410
increases toward the “1” level. When pulse 2 is between φ ₅ and φ ₆ , transistor 134 is non-conducting and transistor 135 is conducting, and current flows from low-pass filter 409 to “0” level power supply line 141 (ground in the example shown). The output voltage 410 drops toward the "0" level.

Here, the output 7 in FIG. 7 is sent to the phase delay circuit 402.
06 or output 909 in Fig. 9 as the circuit output, that is, pulse 1' output, when pulse 2 is between φ ₄ and φ ₅ , pulse 1' (simultaneously 136) is on the left side in Fig. 14. , and when it is between φ ₅ and φ ₆ , it moves to the right, and the phase is stabilized by the phase relationship of φ ₅ . Therefore, in the embodiment of FIG. 14, for pulse 2,
The generation phase of the output pulse 406 of the TFF 403 is stabilized.

〔Effect of the invention〕

According to the present invention, it is possible to automatically control the phase relationship between the clock and the operation control signal pulse to always maintain a desired relationship, so that the clock operates and the operation and non-operation are controlled by the operation control signal pulse. A phase instability phenomenon in which the generated phase of the flip-flop output signal jumps with respect to the operation control signal pulse phase does not occur.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing TFF, Figure 2 is
The operation waveform diagram of each part of TFF, Fig. 3 is an operation waveform diagram for explaining the operating principle of a known conventional example, and Fig. 4, 1
0, 11, and 13 are block diagrams of embodiments of the present invention, FIGS. 5 and 6 are operational waveform diagrams of each part of FIG. 4, and FIGS. 7 and 9 are concrete implementations of the phase delay circuit 402 of FIG. 4. Example circuit diagram, Figure 8 is the operation waveform diagram of each part of Figure 7, Figures 12 and 14 are 10, 11, 13
FIG. 4 is a waveform chart showing the operation of each part of the embodiment shown in the figure. 1...Clock, 2'...Operation control pulse, 3,
406, 102, 114...flip-flop output, 408...phase detection output, 409...low-pass filter, 402...phase delay circuit.

Claims (1)

[Claims] 1 A first flip-flop whose output logic level is switched by the first phase of the first pulse and whose execution or non-execution of the above operation is controlled by the second pulse; a second flip-flop having an operation in which the logic level of the output is switched in a second phase different from the first phase, and execution or non-execution of the above operation is controlled by a second pulse; and an output of the first flip-flop. The generation phase of the output of the second flip-flop with respect to the first
outputs a voltage of the first voltage value when the relationship is
a phase detection means for outputting a voltage having a second voltage value when a second relationship exists; a low-pass filtering means for low-pass filtering the output of the phase detection means;
1. A pulse generator comprising: a phase delay means having a variable phase delay amount of the first pulse or the second pulse, wherein the output of the low-pass filter means is used as a control voltage of the phase delay means.