JPH0469742A - Electronic equipment - Google Patents

Abstract

PURPOSE:To prevent the unoperability of the system by constituting this equipment so that in response to the reset signal, a CPU executes an auxiliary program first and checks a BIOS program, and rewrites the BIOS program at the time of abnormality. CONSTITUTION:When the supply of a driving voltage VCC to each part is started, a reset circuit 1 detects it, and outputs a reset signal RS. The reset signal RS is supplied to a CPU 2, as well, and the CPU 2 executes an auxiliary program stored in a mask ROM 5 in connection with the turn-on of a power source. The auxiliary program is provided in order to check a BIOS (BASIC INPUT OUTPUT SYSTEM), and when the program is normal, the control is transferred to this BIOS program, and on the other hand, when the program is abnormal, the BIOS program is rewritten. In such a manner, even when abnormality is generated in the BIOS program, the correction can be executed without replacing a storage element in which this BIOS program is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is applied to B I OS
The present invention relates to an electronic device in which a TPUTSYSTEM program is stored in an EEPROM.

(b) Prior Art In recent years, the processing power of electronic devices such as personal computers has increased tremendously, and their functions have continued to increase. By the way, the software (program) for this type of electronic device consists of an application program that is loaded into the main memory of the system from a secondary storage medium such as a disk and executed, and an application program that is pre-stored in the non-volatile memory installed in the system. It consists of basic human output software (hereinafter referred to as BIOS program). The BIOS program plays an important role, such as loading application programs, in setting up the device. Now, due to the expansion of functions as described above, even BIOS programs that support only basic functions are becoming extremely complex. As BrO3 becomes more complex, improvements to BIO9 itself (bug countermeasures,
(Version upgrade, etc.) requests occur frequently. For this reason, if the BIOS program is installed in a non-rewritable mask ROM, the device will have to be disassembled each time an improvement request is made.
ASK R, OM had to be replaced, and the manufacturing and quality of the equipment was not favorable.

Therefore, recently, EEPROM (NEC Technical Report Vol.
42 No. 1.1. /1.989 P22-P23
It has been proposed to incorporate the memory into a flash FROM (in this specification, both are collectively referred to as an EEPROM). With such a configuration, even if it becomes necessary to improve BrO3, there is no need to replace the ROM itself (B
The contents of rO3 can be easily changed.

(c) Problems to be solved by the invention However, in such devices, if an accident such as a power outage occurs during the BIOS program change (rewrite) operation, the BrO3, which controls the basic operation of the system, will be completely disabled. Since it has not been rewritten, the system will not work at all. Furthermore, EEPRO where B I O8 is stored
M is ``--as mentioned above, it can be electrically rewritten, so
Mechanically, the EEPROM is not designed to be easily replaced. For this reason, the EE due to the occurrence of the above accident
Replacing the PROM requires a great deal of time and effort.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and its structural features include a reset circuit that detects the start of supply of power supply voltage and outputs a reset signal, and a BIOS program. an electrically erasable/writable EEPROM in which is stored, and the above-mentioned BIO
A read-only ROM in which an auxiliary program for checking 3 is stored, a CPU that starts operating in response to the reset signal, and a read-only ROM that stores the EEPROM and R.O.
and address conversion means for arranging each address of M,
In response to the reset signal, the CPU first checks the BIOS program by executing the auxiliary program described in -F, and if the program is normal, the CPU executes the BIOS program.
The purpose is to transfer control to the IOS program, and to rewrite the BIOS program in the event of an abnormality.

(e) Operation With such a configuration, even if an abnormality occurs in the BIOS program, it can be corrected without replacing the memory element in which the BIOS program is stored.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, and (1) in the figure is a reset circuit, in which a power switch (not shown) is turned on and driving power VCC is supplied to each part. When it detects that it has started, it outputs reset signals R and S. (2) is a CPU (central processing unit), and the CPU
When U is supplied with the reset signal R5 from the reset circuit (1), it outputs an address signal indicating the FOOOO address (in this embodiment, the address is expressed in hexadecimal) from the terminal AO-A19. (3) is the I10 port, and the boat is connected to port 1 as shown in FIG. When a reset signal is supplied to the PBO terminal from the reset circuit (1) 1. A signal corresponding to the hexadecimal number "FE" is output from the PAO-IPA7 terminal, and when the I10 signal is input from the CPU (2) to the IPBI terminal, the signal is output to IP8-1. A signal corresponding to hexadecimal number rOFJ is output from the PA7 terminal.

(4) is an electrically rewritable EEPROM, (5) is a non-rewritable mask ROM, and both ROMs (4) (
5), the respective address terminals AO to A15 are connected to the address terminals AO to A15 of the CPU (2) via the first address bus ABI.
Connected to A 1.5. In addition, ``2 ROM (
4) The respective data input/output terminals DO to D7 in (5) are connected to the data terminals DO to D of the CPU (2) via the data bus DB.
7 is connected. Also, 00 of EEPROM (4)
BrO3 is stored in addresses 00 to FFFF, and BrO3 is stored in addresses 0000 to FFFF of the mask ROM (5), as will be explained in detail later, to check the above BIO3, and as a result, when there is an abnormality in BIO5. 13 I
An auxiliary program for rewriting the OS is stored.

(6) is an address conversion circuit, which is connected to the CPU (2).
) and address signals output from address terminals A16 to A1.9 and supplied via the second address bus AB2 and I
A chip select signal CS is outputted to each of the ROMs (4) and (5) and other memory elements (not shown) based on the signals output from the IPAO to IPA7 terminals of the 10 ports (3).

Specifically, this address conversion circuit (6) is connected to the first to eighth (JI algebraic OR (XOR) circuits) as shown in FIG.
7a) to (7h), a first AND circuit (8a) having four inverting inputs, a second AND circuit (8b) having four inverting inputs and one non-inverting input, and a four-person OR circuit ( 9) and an inverting circuit (10). The above XO
One input of each of R circuits (7a) to (7h) is 1PA
O~1. PA7@ child is connected, while the 1st and 5th XO
The other inputs of the R circuits (7a) (7e) are connected to the address terminal A16 of the CPU (2), and the second and sixth XOR circuits (7b) (
7f) is the address terminal A17 of the CPU (2).
The other inputs of the third and seventh XOR circuits (7c) (7g) are connected to the address terminal A1g of the CPU (2), and the fourth and eighth
Other inputs of the OR circuits (7d) (7h) are connected to address terminals A1.9 of the CPU (2), respectively. Further, each input of the first AND circuit (8a) is connected to the first to fourth X
It is connected to the outputs of the OR circuits (7a) to (7d), and its output is sent to the chip select terminal C8 of the EEPROM (4) as a chip select signal of the EEPROM (4).
supplied to On the other hand, each inverting input of the second AND circuit (8b) is connected to the fifth to eighth XOR circuits (7e) to (7h), respectively.
), and its non-inverting input has four inputs, respectively 1. PA4~1. PA7
The output of the OR circuit (9) is connected to the output of the OR circuit (9).

The output of the second AND circuit (81) is directly connected to the depth select terminal C8 of the mask ROM (5) and also connected to the chip select terminal C8 of a memory element (not shown) via the inverting circuit (10). has been done. Therefore, the output of the second AND circuit (8b) is output from the mask ROM (5
) and act as a chip select signal for other memory elements. Furthermore, as is clear from the above description, when the mask ROM (5) is selected, other memory elements become unselected, and conversely, when the mask ROM (5) is unselected, other memory elements become selected. The Rukoto.

Next, to explain the operation of this embodiment, first, a power switch (not shown) is turned on, and the drive voltage vC to each part is turned on.
When the supply of C starts, the reset circuit (1) detects this and outputs a reset signal R5.

These reset signals R and S are 1. Since the power is supplied from the PBO terminal to the I10 port (3), the I10 port (3) is 1
．． PAO~1. A signal corresponding to rEFJ is output from the PA7 terminal in hexadecimal notation. Therefore, the first AND circuit (8a) of the address conversion circuit (6) shown in FIG.
The data output from the A16-A19 terminals in (2) is expressed in hexadecimal as "Output is logical only when EJ occurs",
On the other hand, the second AND circuit (8b) is A], 6 of the CPU (2).
~The data output from the A1.9 terminal is displayed in hexadecimal as “
The output becomes logic] only when F is reached. As a result, E.E.
The vacant 11 target address assignments of PROM (4), mask ROM (5) and other memory elements are as shown in FIG. 4(a).

Further, the reset signal R5 is sent to CP via the RT terminal.
It is also supplied to U(2). Therefore, ``Double series'' (CP
U(2) first outputs address data indicating the FOOOO address to the first and second address buses from the AO-A19 terminal.

As a result, the data supplied to the address conversion circuit (6) via the second address bus becomes "F" in hexadecimal, so the first AND circuit (8a) in the address conversion circuit (6)
The output of the second AND circuit (8b) becomes a logic 0, while the output of the second AND circuit (8b) becomes a logic 1. Therefore, only the mask ROM (5) is selected, and the data stored at address 0000 in the mask ROM (5) is transferred to the data bus DB.
It will be sent to CPU (2) via.

Therefore, when the power is turned on, the CPU (2)
(5) The auxiliary program stored in the program will be executed.

This auxiliary program checks the bias as described in -, but specifically performs the processing shown in the flowchart of FIG.

That is, in step S1, B in EEPROM (4)
The total value is calculated by reading out all the data indicating the IOS program and sequentially adding the data (checksum).

Incidentally, each address of the EEPROM (4) is as shown in FIG. 4(a) (EOOOO address to E F
The address is FFFF. Therefore, when reading the above data, 16
The auxiliary program is configured so that data from EOOOO to EFFFF is output in decimal format.

Also, the checksum value of the BIOS program is B.
It is set so that rO3 is always at a certain specific value when it is normal.

Next, step S2 is processed, in which it is determined whether the checksum value calculated in step S1 is a specific value. In such a determination, if it is determined that the value is a specific value, the process proceeds to step S3.

In the S3 step, I1 is input from the I10 terminal of the CPU (2).
0100 is output, and the start address of the BIOS program in EEP R, OM (4) is output from the AO-A19 terminal to start up BrO3.

Specifically, the I10 boat (3
) from the IPAO to IPA7 terminals in hexadecimal format.
” is output, so the mask ROM (5)
becomes unselected and is deleted from the spatial address allocation. Further, the EEPROM (4) is selected only when data indicating "F" in hexadecimal is output from the A16 to A]9 terminals. Therefore, when I10100 is output, the memory spatial address allocation changes as shown in FIG. 4(b).

Furthermore, if the start address of BrO3 in EEPR, OM (4) is, for example, address EOOO, then in step S3, the FE
6S2 where data indicating the OOO address will be output
Returning to step S4, if it is determined in this step that the checksum value calculated in step 81 is not equal to the specific value, the process proceeds to step S4.

In such S4 step, the CPU (2) reads the EEPROM (
4) Rewrite the BIOS program inside.

Specifically, for example, a correct BIOS program sent via a communication port (not shown) or obtained by reading from a secondary storage medium (not shown) such as a floppy disk is stored in an EEPROM (4 ) write inside. Note that the checksum value of this written BiO2 is the above-mentioned specific value.

Thereafter, the process returns to the S1 step and executes the S1 and S2 steps to determine whether or not erroneous rewriting such as dropped bits has occurred during the rewriting operation in the S4 step. If it is determined in such a determination that an erroneous rewrite has occurred, step S4 is processed again. On the other hand, if it is determined that the BIOS program has been correctly rewritten, control is passed to the BrO3 in two consecutive steps by processing step 83.

In this embodiment, the auxiliary program is stored in the mask ROM, but the invention is not limited to this, and it can be stored in the EEPROM.
, or may be stored in other non-volatile memory such as EPROM.

(G) Effects of the Invention According to the present invention, the BIOS program is checked before it is executed, and if an abnormality has occurred, the BIOS program is rewritten.

Therefore, even if an abnormality occurs in the BIOS program, the system will not become completely inoperable.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a main circuit diagram showing main parts of this embodiment, and Fig. 3 is an I/O diagram of this embodiment.
Schematic diagram illustrating the output signals of 10 boats, Figure 4 (a)
(b) is a schematic diagram showing the spatial address allocation of this embodiment,
FIG. 5 is a flowchart for explaining the operation of this embodiment. (1)...Reset circuit, (2)...CPU, (3
)...I10 boat, (4)...EEPROM, (
5)...Mask ROM, (6)...Address conversion circuit

Claims (1)

[Claims] (1) A reset circuit that detects the start of supply of power supply voltage and outputs a reset signal, an electrically erasable/writable EEPROM in which a BIOS program is stored, and the above-mentioned BIOS
a read-only ROM storing an auxiliary program for checking S; a CPU that starts operating in response to the reset signal; and a CPU that starts operating in response to the reset signal;
address conversion means for arranging each address of the EEPROM and ROM in the address space of the PU, and in response to the reset signal, the CPU first checks the BIOS program by executing the auxiliary program, and When the program is normal, such BI
Control is transferred to the OS program, and when an error occurs, the above B
An electronic device characterized by rewriting an IOS program.