JPH0469838B2 - - Google Patents

Info

Publication number
JPH0469838B2
JPH0469838B2 JP62250573A JP25057387A JPH0469838B2 JP H0469838 B2 JPH0469838 B2 JP H0469838B2 JP 62250573 A JP62250573 A JP 62250573A JP 25057387 A JP25057387 A JP 25057387A JP H0469838 B2 JPH0469838 B2 JP H0469838B2
Authority
JP
Japan
Prior art keywords
base material
circuit
conductor
conductive base
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62250573A
Other languages
Japanese (ja)
Other versions
JPH0194695A (en
Inventor
Tatsuo Wada
Masamitsu Takenaka
Toshiro Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toagosei Co Ltd
Original Assignee
Toagosei Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toagosei Co Ltd filed Critical Toagosei Co Ltd
Priority to JP25057387A priority Critical patent/JPH0194695A/en
Publication of JPH0194695A publication Critical patent/JPH0194695A/en
Publication of JPH0469838B2 publication Critical patent/JPH0469838B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、スルーホール付の両面もしくは多層
の導体回路板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing double-sided or multilayer conductor circuit boards with through holes.

(従来の技術) 従来、スルーホール付の両面導体回路板を製造
する方法としては、例えば平板状導電基材の全面
に金属薄膜を形成したのちに、所望のレジストマ
スクを形成し、この平板状導電基材を陰極として
使用する電解メツキ法により導体回路パターンを
形成し、このような平板状導電基材2個を絶縁基
材を介して熱圧着して積層体を形成したのち、所
要の箇所にスルーホールを穴明け加工し、スルー
ホールメツキを行つている。
(Prior Art) Conventionally, as a method for manufacturing a double-sided conductive circuit board with through holes, for example, a metal thin film is formed on the entire surface of a flat conductive base material, a desired resist mask is formed, and this flat conductive substrate is A conductor circuit pattern is formed by an electrolytic plating method using a conductive base material as a cathode, and two such flat conductive base materials are thermocompression bonded via an insulating base material to form a laminate. Through-holes are drilled and through-holes are plated.

かかる両面導体回路板の製造方法において、導
体回路を形成するための電解メツキ工程として
は、高品質の導体回路を短時間で形成することが
可能な、所謂高速メツキ法が賞用されている。即
ち、第19図に示すように、平板状導電基材1の
全面に金属薄膜2を形成したのちに、この金属薄
膜2の導体回路形成領域を除く領域にレジストマ
スク3を形成し、次いで、この平板状導電基材1
を陰極とし、この陰極と平板状陽極(図示せず)
を所定の距離だけ離間させ、両電極間に高速で電
解液を供給することにより銅を堆積させ、導体回
路4,4′を形成する。
In such a method of manufacturing a double-sided conductor circuit board, a so-called high-speed plating method is preferred as the electrolytic plating process for forming conductor circuits, which can form high-quality conductor circuits in a short time. That is, as shown in FIG. 19, after forming a metal thin film 2 on the entire surface of a flat conductive base material 1, a resist mask 3 is formed on the area of this metal thin film 2 excluding the conductor circuit formation area, and then, This flat conductive base material 1
is a cathode, and this cathode and a flat anode (not shown)
are separated by a predetermined distance and an electrolytic solution is supplied between both electrodes at high speed to deposit copper, thereby forming conductor circuits 4, 4'.

(発明が解決しようとする問題点) しかしながら、かかる導体回路形成工程におい
て、導体回路4と導体回路4′とが非常に離隔し
ている場合、即ち、導体回路4,4′が夫々孤立
している場合には、第19図に示すように導体回
路4と4′との間のブランク部分に相当するレジ
ストマスク3aと前記導体回路4,4′との境界
に、所謂、エツジビード(ドツグボーン)5,
5′が集中的に発生する。このエツジビード5,
5′は回路端部に電解電流が集中することにより
端部にメツキ金属が異常堆積する現象であり、こ
の現象が発生すると、回路の膜厚や幅が設計値よ
りも大幅に増大したり、転写積層時にエツジビー
ド部にエア溜まりが生じたり、或いは、転写時に
エツジビードが絶縁基材を突き抜けてシヨート等
の原因となつたりする。更に、高周波回路基板に
おいては、良好な特性を確保するためには回路幅
と絶縁間隔を厳密に設定することが要求されるた
め、かかるエツジビードが発生すると高周波特性
が著しく損なれるという問題が生じる。このエツ
ジビード5,5′の成長は電解メツキ時の電流密
度が高い程著しく、導体回路4,4′の中央の厚
さtに対する、エツジビード5,5′の高さt′の
比、t′/tが1.9から5〜6倍にも及んでしまう。
(Problems to be Solved by the Invention) However, in such a conductor circuit forming process, if the conductor circuit 4 and the conductor circuit 4' are very far apart, that is, the conductor circuits 4 and 4' are isolated from each other. 19, a so-called edge bead (dog bone) 5 is formed at the boundary between the resist mask 3a and the conductor circuits 4, 4', which corresponds to the blank part between the conductor circuits 4 and 4'. ,
5' occurs intensively. This edge bead 5,
5' is a phenomenon in which plating metal is abnormally deposited at the edges of the circuit due to concentration of electrolytic current at the edges. When this phenomenon occurs, the film thickness and width of the circuit increase significantly from the design values, Air may accumulate in the edge bead portion during transfer and lamination, or the edge bead may penetrate through the insulating base material during transfer, causing shoots and the like. Furthermore, in high-frequency circuit boards, it is required to strictly set the circuit width and insulation spacing in order to ensure good characteristics, so the occurrence of such edge beads causes a problem in that the high-frequency characteristics are significantly impaired. The growth of the edge beads 5, 5' becomes more remarkable as the current density during electrolytic plating increases. t increases from 1.9 to 5 to 6 times.

かかる不具合を解消するために、導体回路4,
4′間に予めダミー回路を形成しておき、エツジ
ビードの発生を抑える方法が提案されている(特
開昭58−123793号公報)。この方法においては、
ダミー回路を最終的に目的とする導体回路板に組
み込まない場合は、導体回路の転写積層に先立つ
て当該ダミー回路のみを除去する必要がある。し
かし、金属薄膜2が介在するために、ダミー回路
のみを除去することは極めて困難であるという問
題がある。
In order to eliminate this problem, the conductor circuit 4,
A method has been proposed in which a dummy circuit is formed in advance between 4' to suppress the occurrence of edge beads (Japanese Patent Laid-Open No. 123793/1983). In this method,
If the dummy circuit is not to be incorporated into the final target conductor circuit board, it is necessary to remove only the dummy circuit prior to transferring and laminating the conductor circuit. However, since the metal thin film 2 is present, there is a problem in that it is extremely difficult to remove only the dummy circuit.

一方、金属薄膜2を形成しないで、ダミー回路
及び導体回路の形成を行うと、確かに、ダミー回
路のみの除去は可能となるが、ダミー回路を除去
すると導体回路間では平板状導電基材表面が露出
するため、転写時にこの平板状導電基材表面の微
細なピツトに絶縁物質が侵入して、平板状導電基
材と絶縁物質が強固に密着するために、転写がで
きなくなつてしまい、更に、独立回路のスルーホ
ールメツキの際に当該回路への通電ができなくな
るという問題が生じる。
On the other hand, if a dummy circuit and a conductor circuit are formed without forming the metal thin film 2, it is certainly possible to remove only the dummy circuit, but when the dummy circuit is removed, the surface of the flat conductive substrate is removed between the conductor circuits. is exposed, and during transfer, the insulating material invades the fine pits on the surface of the flat conductive base material, and the flat conductive base material and the insulating material are tightly adhered, making it impossible to transfer. Furthermore, when plating through-holes in independent circuits, a problem arises in that current cannot be applied to the circuits.

本考案は上記従来の問題点に鑑みてなされたも
ので、エツジビードの過度な成長を抑制し、しか
も、転写性が良好な導体回路板の製造方法を提供
することを目的とする。
The present invention has been made in view of the above-mentioned conventional problems, and an object thereof is to provide a method for manufacturing a conductive circuit board that suppresses excessive growth of edge beads and has good transferability.

(問題点を解決するための手段及び作用) 上記目的を達成するために本発明によれば、平
板状導電基材表面の導体回路形成領域及び導体回
路のうち、孤立する導体回路に隣接するダミー回
路形成領域を除く領域にレジストマスクを形成す
る工程と、この平板状導電基材に電解メツキを施
して前記平板状導電基材に導体回路及びダミー回
路を形成する工程と、前記レジストマスクを剥離
する工程と、平板状導電基材表面及び導体回路を
覆つて金属薄膜を形成する工程と、斯く導体回路
が形成された平板状導電基材2個を該導体回路を
互いに対向させ、絶縁基材を介して積層して一体
に圧着又は加熱圧着し積層体を形成する工程と、
この積層体から平板状導電基材のみを剥離する工
程と、この積層体にスルーホールを穴明け加工し
たのちスルーホールの内壁面及び前記積層体の両
面にスルーホールメツキを施す工程と、前記導体
回路同士を電気的に接続する前記金属薄膜をエツ
チング除去する工程とからなるものである。更
に、本発明においては、導体回路及びダミー回路
を形成したのち、所要により、ダミー回路の少な
くとも一部を除去する。
(Means and effects for solving the problem) In order to achieve the above object, according to the present invention, a dummy layer adjacent to an isolated conductor circuit in a conductor circuit forming area and a conductor circuit on the surface of a flat conductive base material is provided. a step of forming a resist mask in an area excluding a circuit forming area; a step of performing electrolytic plating on the flat conductive base material to form a conductor circuit and a dummy circuit on the flat conductive base material; and peeling off the resist mask. a step of forming a metal thin film covering the surface of the flat conductive substrate and the conductor circuit; and a step of forming a metal thin film covering the surface of the flat conductive substrate and the conductor circuit, and placing the two flat conductive substrates on which the conductor circuit has been formed so that the conductor circuit faces each other, a step of laminating them together and press-bonding them together or heat-pressing them to form a laminate;
A step of peeling only the flat conductive base material from this laminate, a step of drilling a through hole in this laminate and then plating the through hole on the inner wall surface of the through hole and both sides of the laminate, and This process consists of a step of etching away the metal thin film that electrically connects the circuits. Further, in the present invention, after forming the conductive circuit and the dummy circuit, at least a portion of the dummy circuit is removed if necessary.

(作用) 孤立する導体回路、具体的には、当該導体回路
の少なくとも一側に所要の間隔を経て隣接の導体
回路が存在しないような導体回路を形成する際、
これらの導体回路に隣接してダミー回路を同時に
形成することにより、エツジビードの過度な成長
を抑制し、回路寸法の大幅な増大や、転写積層時
にエツジビード部に生じるエア溜まりや、エツジ
ビードが絶縁基材を突き抜けることにより生じる
シヨート等の発生を防止する。又、金属薄膜形成
工程を後工程とすることにより、ダミー回路のみ
の除去を容易に行うことができ、しかも、導体回
路の転写性も良好に保持される。更に、スルーホ
ールを形成する回路が独立回路であつても、金属
薄膜が存在するので、通電性が良好に保たれる。
(Function) When forming an isolated conductor circuit, specifically, a conductor circuit in which there is no adjacent conductor circuit on at least one side of the conductor circuit with a required interval,
By simultaneously forming dummy circuits adjacent to these conductor circuits, excessive growth of edge beads can be suppressed, resulting in a significant increase in circuit size, air pockets that occur in edge bead areas during transfer lamination, and edge bead damage to insulating substrates. This prevents the occurrence of shoots, etc. caused by penetrating through. Furthermore, by performing the metal thin film forming step as a post-process, only the dummy circuit can be easily removed, and the transferability of the conductor circuit can also be maintained well. Furthermore, even if the circuit forming the through hole is an independent circuit, the presence of the metal thin film maintains good electrical conductivity.

(実施例) 以下、第1図乃至第15図に基づき、本発明方
法の一実施例を説明する。
(Example) Hereinafter, an example of the method of the present invention will be described based on FIGS. 1 to 15.

先ず、本発明方法の実施に使用される平板状導
電基材11としては、メツキ工程で使用する薬品
に対する耐薬品性、耐電食性を有するものである
ことが望ましく、ステンレススチール板(例え
ば、ハードニング処理を施したSUS630が好適で
ある)、ニツケル板、チタン又はチタン合金板、
銅又は銅合金板等が使用される。この平板状導電
基材2の表面の汚れ、酸化皮膜を除去すると共
に、該表面に所要の粗度を与える前処理工程を施
す(第1図a)ことが好ましい。平板状導電基材
2の表面粗度は、後工程で平板状導電基材11上
に形成される銅薄膜15の密着強度やピンホール
の発生、更には銅薄膜15の表面粗度にも影響を
与える。この表面粗度は後述する平板状導電基材
11の剥離工程(第1図h)において容易に剥離
できる密着性が得られるように設定することが望
ましい。
First, the flat conductive substrate 11 used in the method of the present invention is preferably one that has chemical resistance and electrical corrosion resistance against chemicals used in the plating process, and is preferably made of a stainless steel plate (for example, a hardened plate). (preferably treated SUS630), nickel plate, titanium or titanium alloy plate,
Copper or copper alloy plates are used. It is preferable to perform a pretreatment step to remove dirt and oxide film from the surface of the flat conductive substrate 2 and to give the surface a desired roughness (FIG. 1a). The surface roughness of the flat conductive base material 2 affects the adhesion strength and pinhole formation of the copper thin film 15 formed on the flat conductive base material 11 in a subsequent process, and also affects the surface roughness of the copper thin film 15. give. This surface roughness is desirably set so as to provide adhesion that allows easy peeling in the step of peeling off the flat conductive base material 11 (FIG. 1h), which will be described later.

平板状導電基材11の粗面化処理は具体的に
は、化学的方法、或いは、平板状導電基材11表
面を化学的にクリーニングした後、湿式サンドブ
ラスト(液体ホーニング)等により機械的に粗面
化する方法等が使用される。
Specifically, the surface roughening treatment of the flat conductive base material 11 is carried out by a chemical method, or by chemically cleaning the surface of the flat conductive base material 11 and then mechanically roughening it by wet sandblasting (liquid honing) or the like. A method such as surfaceization is used.

この平板状導電基材11表面の、導体回路1
3,13′及びダミー回路13″が形成される部分
を除いた表面に、フオトレジスト法、印刷法等に
よりレジストマスク12を形成する(第1図b、
第2図)。レジスト剤としては、平板状導電基材
11との密着性にすぐれたものが選択される。具
体的には、感光性レジストフイルムをラミネート
する方法もしくは液状の感光性レジストを塗布後
乾燥することによりレジスト層を形成し、露光・
現像により所望のパターンのレジストマスク12
を形成する。尚、導体回路の線密度が低い場合に
は、例えばスクリーン印刷法によりレジストマス
ク12を形成してもよい。
Conductor circuit 1 on the surface of this flat conductive base material 11
A resist mask 12 is formed by photoresist method, printing method, etc. on the surface excluding the portion where 3, 13' and dummy circuit 13'' are to be formed (FIG. 1b,
Figure 2). As the resist agent, one that has excellent adhesion to the flat conductive base material 11 is selected. Specifically, a resist layer is formed by laminating a photosensitive resist film or by coating and drying a liquid photosensitive resist, and then exposing and drying the resist layer.
A resist mask 12 with a desired pattern is formed by development.
form. Note that when the linear density of the conductor circuit is low, the resist mask 12 may be formed by, for example, a screen printing method.

次に、上述のようにしてレジストマスク12を
形成させた平板状導電基材11を陰極として、こ
れを陽極14に所定の距離(例えば、3〜30mm、
好ましくは、11〜15mm)だけ離間させて対峙さ
せ、高速メツキにより導体回路13,13′及び
ダミー回路13″を銅電鋳する(第1図c、第3
図)。この高速メツキの電解液としては、金属銅
濃度0.20〜2.0mol/、好ましくは、0.35〜
0.98mol/、及び硫酸濃度50〜220g/を含
有する硫酸銅メツキ液でよく、メツキの均一性を
確保するために西独国LPW社製の
CUPPORAPID Hs(商品名)を1.5ml/あて添
加する。又、ピロリン酸銅液等の通常のメツキ液
を使用してもよい。また、電流密度0.15〜4A/
cm2、電極に対する接液スピード2.6〜20m/sec、
電解液温度45〜70℃、好ましくは60〜65℃となる
ように夫々設定する。メツキ液温が45℃未満であ
ると、銅イオンの移動速度が低下するため電極表
面に分極層が生じ易くなり、メツキ堆積速度が低
下する。一方、液温が70℃を越えるとメツキ液の
蒸発量が多くなり濃度が不安定なると共に、液温
高温化による設備的制限が加わる。
Next, the flat conductive base material 11 on which the resist mask 12 has been formed as described above is used as a cathode, and this is connected to the anode 14 at a predetermined distance (for example, 3 to 30 mm,
Preferably, the conductor circuits 13, 13' and the dummy circuit 13'' are electroformed in copper by high-speed plating, facing each other with a distance of 11 to 15 mm (Fig. 1c, 3).
figure). The electrolytic solution for this high-speed plating has a metal copper concentration of 0.20 to 2.0 mol/, preferably 0.35 to 2.0 mol/
A copper sulfate plating solution containing 0.98 mol/, and a sulfuric acid concentration of 50 to 220 g/ is sufficient.
Add 1.5 ml of CUPPORAPID Hs (trade name). Ordinary plating solutions such as copper pyrophosphate solution may also be used. Also, current density 0.15~4A/
cm 2 , liquid contact speed to electrode 2.6 to 20 m/sec,
The electrolytic solution temperature is set at 45 to 70°C, preferably 60 to 65°C. If the plating liquid temperature is less than 45° C., the moving speed of copper ions decreases, making it easier to form a polarized layer on the electrode surface, resulting in a decreased plating deposition rate. On the other hand, when the liquid temperature exceeds 70°C, the amount of evaporation of the plating liquid increases, making the concentration unstable, and equipment restrictions are imposed due to the high liquid temperature.

この電鋳工程において、導体回路13′,1
3′とが許容のエツジビード高さ比t′/tを超え
るような間隔(例えば2mm以上)で離隔している
場合に、その間にダミー回路13″,13″が形成
されるため、電鋳時のエツジビードの成長が抑制
され、後述する転写工程において、導体回路1
3′,13′間のシヨート等の発生が防止されると
いう利点がある。即ち、この工程において、前述
した導体回路13,13′の中央の厚さtとエツ
ジビードの平板状導電基材表面からの高さt′との
比t′/tを1.0〜1.8の範囲に抑えることができる。
尚、このダミー回路13″の形成位置、個数、導
体回路13′との距離等は、導体回路13′,1
3′間の距離等に応じて適宜設定することが好ま
しい。
In this electroforming process, conductor circuits 13', 1
3' are separated by a distance that exceeds the allowable edge bead height ratio t'/t (for example, 2 mm or more), dummy circuits 13'' and 13'' are formed between them. This suppresses the growth of edge beads in the conductor circuit 1 in the transfer process described later.
There is an advantage that the occurrence of shoots etc. between 3' and 13' is prevented. That is, in this step, the ratio t'/t between the thickness t at the center of the conductive circuits 13, 13' described above and the height t' of the edge bead from the surface of the flat conductive base material is suppressed to a range of 1.0 to 1.8. be able to.
Note that the formation position, number, distance from the conductor circuit 13', etc. of the dummy circuit 13'' are different from the conductor circuits 13', 1.
It is preferable to set the distance appropriately depending on the distance between 3' and the like.

又、電流密度と電極に対する接液スピードとを
上述の所定の条件に設定することにより、平板状
導電基材11上に毎分25〜100μmの堆積速度で導
体回路13,13′及びダミー回路13″を堆積さ
せることができ、しかも、堆積する銅粒子を極め
て微細にすることができ、導体回路13,13′
の伸び率は抗張力を損なうことなく16〜25%に達
する。この伸び率は通常のメツキ法により形成さ
れた導体回路の伸び率より1.5〜2倍以上であり
(圧延アニール銅箔と同等以上の値であり)、極め
て柔らかい銅膜を作製することが出来る。このよ
うに圧延アニール銅箔と同等の性能を有すること
から、高折曲性が必要なフレキシブル基板におい
て特に有効である。
Furthermore, by setting the current density and the speed of contact with the electrodes to the above-described predetermined conditions, the conductor circuits 13, 13' and the dummy circuit 13 are deposited on the flat conductive substrate 11 at a deposition rate of 25 to 100 μm per minute. Moreover, the deposited copper particles can be made extremely fine, and the conductor circuits 13, 13'
The elongation rate reaches 16-25% without loss of tensile strength. This elongation rate is 1.5 to 2 times or more than the elongation rate of a conductor circuit formed by a normal plating method (a value equivalent to or higher than that of rolled annealed copper foil), and an extremely soft copper film can be produced. Since it has performance equivalent to that of rolled annealed copper foil, it is particularly effective in flexible substrates that require high bendability.

銅電鋳工程において、導体回路13,13′及
びダミー回路13″が所要の厚み(例えば、2μm
〜300μm)に達した時点で通電及びメツキ液の供
給を停止し、水洗後、レジストマスク12の除去
工程に進む(第1図d、第4図)。このレジスト
マスク12の剥離除去には、例えば、カセイソー
ダ等の溶解液が使用され、この溶解液中に30〜60
秒浸漬してレジストマスク12を溶解除去し、水
洗、乾燥する。
In the copper electroforming process, the conductor circuits 13, 13' and the dummy circuit 13'' have the required thickness (for example, 2 μm).
300 μm), the supply of electricity and plating solution is stopped, and after washing with water, the process proceeds to the step of removing the resist mask 12 (FIG. 1d, FIG. 4). For example, a solution such as caustic soda is used to peel off and remove the resist mask 12.
The resist mask 12 is dissolved and removed by dipping for a second, washed with water, and dried.

しかるのち、最終的に導体回路板に組み込まれ
ないダミー回路13″を除去する(第1図e、第
5図)。具体的には、除去すべきダミー回路1
3″のみを物理的、即ち、機械的に除去する方法、
及び、導体回路13,13′をレジストマスク等
により保護した状態で化学エツチングにより除去
する方法等を使用する。尚、このダミー回路1
3″除去工程は、前記レジストマスク12の除去
工程に先立つて行つてもよく、又、ダミー回路1
3″は必ずしも全て除去するのではなく、回路板
に残留すると支障を来す部分のみ除去し、そうで
ない部分は残留させてもよい。
After that, the dummy circuit 13'' that will not be finally incorporated into the conductor circuit board is removed (Fig. 1e, Fig. 5).Specifically, the dummy circuit 13'' to be removed is removed.
A method of physically, that is, mechanically removing only 3″;
Then, a method is used in which the conductor circuits 13, 13' are removed by chemical etching while being protected with a resist mask or the like. Furthermore, this dummy circuit 1
3'' removal process may be performed prior to the resist mask 12 removal process, and the dummy circuit 1
It is not necessarily necessary to remove all of 3'', but only the portion that would cause trouble if left on the circuit board may be removed, and the other portions may be left.

次に、このようにして導体回路13,13′の
みが形成された平板状導電基材11の全面に金属
薄膜15を形成する。金属としては、銅、ニツケ
ル、亜鉛等を使用し、0.5〜5μmの膜厚となるよ
うに形成される。薄膜の形成方法としては、真空
蒸着、スパツタリング、CVD等のドライ法、並
びに、電解メツキ、無電解メツキ等の湿式法等の
何れの方法も使用することができる。中でも、高
速メツキ法は作業性の面からも優れており、高速
メツキ法により銅薄膜を形成する工程について説
明すると、平板状導電基材11を陰極として、こ
れを第3図のように陽極14に所定の距離3〜30
mmだけ離間させて対峙させ、高速メツキにより平
板状導電基材11及び導体回路13,13′上に
銅薄膜15を電解析出させる(第1図f、及び第
6図)。
Next, a metal thin film 15 is formed on the entire surface of the flat conductive base material 11 on which only the conductor circuits 13 and 13' are formed in this manner. Copper, nickel, zinc, etc. are used as the metal, and the film is formed to have a thickness of 0.5 to 5 μm. As a method for forming the thin film, any of dry methods such as vacuum evaporation, sputtering, and CVD, and wet methods such as electrolytic plating and electroless plating can be used. Among them, the high-speed plating method is excellent in terms of workability. To explain the process of forming a copper thin film by the high-speed plating method, the flat conductive base material 11 is used as a cathode, and this is used as an anode 14 as shown in FIG. at a predetermined distance of 3 to 30
The copper thin film 15 is electrolytically deposited on the flat conductive base material 11 and the conductor circuits 13, 13' by high-speed plating with a distance of mm apart from each other (FIG. 1F and FIG. 6).

この場合の高速メツキ条件としては、45〜70℃
のメツキ液を陰極表面において乱流状態、即ち、
電極間距離3〜30mm、電極に対する接液スピード
が2.6〜20.0m/secになるように陰極電極を回転
するか、固定電極間に強制的に電解液を供給す
る。このとき、メツキ液として、例えば、硫酸銅
メツキ液、ピロリン酸銅液等を使用し、陰極電流
密度0.15〜4.0A/cm2の電流を印加し、薄膜金属層
の堆積速度が25〜100μm/minとなるように設定
することが望ましい。
In this case, the high-speed plating conditions are 45 to 70℃.
The plating solution is placed in a turbulent state on the cathode surface, that is,
The cathode electrode is rotated so that the distance between the electrodes is 3 to 30 mm and the speed of contact with the electrode is 2.6 to 20.0 m/sec, or the electrolyte is forcibly supplied between the fixed electrodes. At this time, for example, copper sulfate plating solution, copper pyrophosphate solution, etc. are used as the plating solution, and a current with a cathode current density of 0.15 to 4.0 A/cm 2 is applied, so that the deposition rate of the thin metal layer is 25 to 100 μm/cm 2 . It is desirable to set it so that it is min.

高速電解メツキされた銅薄膜15は、上述した
通り所要の表面粗度を有する平板状導電基材11
に電解積層されるので銅薄膜15は平板状導電基
材11に適度の密着力で密着しており、次工程で
の転写積層を円滑に行うことが可能となる。
The copper thin film 15 subjected to high-speed electrolytic plating is applied to the flat conductive base material 11 having the required surface roughness as described above.
Since the copper thin film 15 is electrolytically laminated, the copper thin film 15 is in close contact with the flat conductive base material 11 with an appropriate adhesion force, and the transfer lamination in the next step can be carried out smoothly.

次いで、このようにして得られた平板状導電基
材11を2個用意し、これらの平板状導電基材1
1上に形成された導体回路13,13′及び銅薄
膜15を、平板状導電基材15と共に絶縁基材1
6の両面に積層して、ホツトプレスによりこれら
を一体に加熱圧着させる(第1図g、第7図)。
絶縁基材16としては、有機材料、及び無機材料
のいずれのものでもよく、例えば、ガラス、エポ
キシ系樹脂、フエノール系樹脂、ポリイミド系樹
脂、ポリエステル系樹脂、アーラミド系樹脂等の
材料を用いることができる。また、鉄、アルミ等
の導電性材料の表面にホーロウを被覆し、又アル
ミ表面を酸化するアルマイト処理を施して絶縁し
た材料でもよい。一般には、ガラス布等にエポキ
シ樹脂を含浸させ、半硬化状態(Bステージ)に
あるプリプレグに導体回路13,13′及び銅薄
膜15の一部が没入する状態(第8図に示す状
態)に加熱・加圧され、これと接着される。
Next, two flat conductive base materials 11 obtained in this way are prepared, and these flat conductive base materials 1 are
The conductive circuits 13, 13' and the copper thin film 15 formed on the insulating base material 1 together with the flat conductive base material 15 are
6, and heat and press them together using a hot press (FIG. 1g, FIG. 7).
The insulating base material 16 may be either an organic material or an inorganic material, and for example, materials such as glass, epoxy resin, phenol resin, polyimide resin, polyester resin, and aramide resin can be used. can. Alternatively, a material insulated by coating the surface of a conductive material such as iron or aluminum with enamel and performing an alumite treatment to oxidize the aluminum surface may be used. Generally, a glass cloth or the like is impregnated with epoxy resin, and the conductor circuits 13, 13' and a part of the copper thin film 15 are immersed in the semi-cured prepreg (B stage) (the state shown in FIG. 8). It is heated and pressurized to bond it.

この転写工程において、導体回路13,13′
及び銅薄膜15は厚手の平板状導電基材11と一
体に絶縁基材16に積層され、加熱圧着されるの
で、導体回路13,13′は当該平板状導電基材
11に保持されたまま転写されることになり、寸
法安定性が確保される。又、平板状導電基材11
が転写時の転写治具を兼ねるので特別の治具が不
要であり、更に、導体回路13,13′と銅薄膜
15とは強い密着力で結合しているため導体回路
13,13′が転写時にずれて移動する(所謂、
スイングを起こす)ことがなく、寸法安定性が良
いので微細な導体回路パターンを有する高密度回
路にも適用可能である(例えば、パターン幅数
μm〜数十μmが実現出来る)。
In this transfer process, the conductor circuits 13, 13'
The copper thin film 15 is laminated together with the thick flat conductive base material 11 on the insulating base material 16 and bonded by heat and pressure, so that the conductor circuits 13 and 13' are transferred while being held on the flat conductive base material 11. This ensures dimensional stability. Moreover, the flat conductive base material 11
Since it also serves as a transfer jig during transfer, no special jig is required.Furthermore, since the conductor circuits 13, 13' and the copper thin film 15 are bonded with strong adhesive force, the conductor circuits 13, 13' can be transferred easily. Move at different times (so-called
Because it has good dimensional stability and does not cause swing (swing), it can be applied to high-density circuits with fine conductor circuit patterns (for example, pattern widths of several μm to several tens of μm can be realized).

次に、絶縁基材16の加熱固化を待つて平板状
導電基材11を、絶縁基材16に転写された導体
回路13,13′及び銅薄膜15から剥離する
(第1図h、第8図)。このとき、平板状導電基材
11と銅薄膜15との間の密着力より、銅薄膜1
5と導体回路13,13′の密着力の方が大であ
り、更に、平板状導電基材11と銅薄膜15との
間の密着力より、銅薄膜15と絶縁基材16の密
着力の方が大であるから、平板状導電基材11は
導体回路13,13′及び銅薄膜15との界面で
分離して絶縁基材16側には銅薄膜15及び導体
回路13,13′が一体に密着している。
Next, after waiting for the insulating base material 16 to harden by heating, the flat conductive base material 11 is peeled off from the conductor circuits 13, 13' and the copper thin film 15 transferred to the insulating base material 16 (Fig. 1 h, 8 figure). At this time, due to the adhesion between the flat conductive base material 11 and the copper thin film 15, the copper thin film 1
5 and the conductor circuits 13, 13', and furthermore, the adhesion between the copper thin film 15 and the insulating base 16 is greater than the adhesion between the flat conductive base 11 and the copper thin film 15. Since the plate-shaped conductive base material 11 is separated at the interface with the conductive circuits 13, 13' and the copper thin film 15, the copper thin film 15 and the conductive circuits 13, 13' are integrated on the insulating base material 16 side. Closely attached to.

次いで、絶縁基材16の両面に積層された導体
回路13,13の間を接続するためのスルーホー
ル17を形成する(第1図i、第9図)。このス
ルーホール形成工程には、通常の方法例えばドリ
ル等を使用した切削加工を適用することができ
る。しかるのち、後述するスルーホールメツキに
備えて、スルーホール17の内壁面17aを含む
積層体全面に化学銅メツキにより銅薄層18を形
成する(第10図)。
Next, through holes 17 are formed to connect the conductor circuits 13, 13 laminated on both sides of the insulating base material 16 (FIG. 1i, FIG. 9). This through-hole forming step can be performed using a conventional method such as cutting using a drill or the like. Thereafter, in preparation for through-hole plating to be described later, a thin copper layer 18 is formed by chemical copper plating on the entire surface of the laminate including the inner wall surface 17a of the through-hole 17 (FIG. 10).

次に、銅薄層18上の上記スルーホール17の
内壁面1a、スルーホール17開口周縁部即ちラ
ンド部、及び必要に応じてコネクタ部等フラツシ
ユ回路とすることが望ましくない部分を除く領域
にレジストマスク19を形成する(第1図j、第
11図)。この工程は上記第1図dの工程で述べ
たのと同様にして実行することができる。
Next, a resist is applied to the inner wall surface 1a of the through hole 17 on the thin copper layer 18, the peripheral edge of the opening of the through hole 17, that is, the land portion, and if necessary, the area excluding the connector portion and other portions where it is not desirable to form a flash circuit. A mask 19 is formed (FIG. 1j, FIG. 11). This step can be carried out in the same manner as described in the step of FIG. 1d above.

しかるのち、上記レジストマスク19が形成さ
れていない領域に、例えば、ピロリン酸銅浴又は
硫酸銅浴(光沢硫酸銅メツキ液)等を使用した銅
の電解メツキにより、スルーホールメツキを施し
スルーホールメツキ層20を形成したのち(第1
図k、第12図)、レジストマスク19を剥離除
去する(第1図l、第13図)。本発明において
は、上記した化学銅メツキ工程及びこの電解メツ
キによるスルーホール工程を一括してスルーホー
ルメツキ工程と称する。このスルーホールメツキ
工程においては、スルーホール17が形成された
導体回路13が独立回路であつても、絶縁基材1
6の全面に亘り銅薄膜15が形成されているた
め、通電性が極めて高いという利点がある。
Thereafter, through-hole plating is applied to the areas where the resist mask 19 is not formed, for example, by copper electrolytic plating using a copper pyrophosphate bath or a copper sulfate bath (bright copper sulfate plating solution). After forming layer 20 (first
(K, FIG. 12), and the resist mask 19 is peeled off (FIG. 1L, FIG. 13). In the present invention, the chemical copper plating process and the through-hole process by electrolytic plating described above are collectively referred to as the through-hole plating process. In this through-hole plating process, even if the conductor circuit 13 in which the through-hole 17 is formed is an independent circuit, the insulating base material 1
Since the thin copper film 15 is formed over the entire surface of the electrode 6, it has the advantage of extremely high conductivity.

尚、スルーホールメツキ工程は第10図乃至第
12図に示した工程に限定されるものではなく、
例えば、第16図乃至第18図に示す手順を経て
実施することもできる。即ち、スルーホール17
を形成した絶縁基材16表面のランド部、及び必
要に応じてコネクタ部等フラツシユ回路とするこ
とが望ましいない部分を除く領域にレジストマス
ク19′を形成する(第16図)。次いで、化学銅
メツキにより銅薄層18′を形成し(第17図)、
続いて、電解メツキによりスルーホールメツキ層
20′を形成する(第18図)。しかるのち、上記
と同様にしてレジストマスク19′を除去し、銅
薄膜15のエツチングを行う。(第14図)。かか
るスルーホールメツキ工程によれば、無電解メツ
キとスルーホールメツキとを続けて行うことが可
能であるため、作業性が向上するという利点があ
る。但し、上記工程においては、レジストマスク
19′形成後に無電解メツキ即ち化学銅メツキを
行うため、レジスト材としては、無電解メツキが
施されないように例えば触媒毒等を含有し、且
つ、アルカリ性の無電解メツキ液により侵されな
いよう耐アルカリ性のものを選択することが望ま
しい。又、種々の制約から耐アルカリ性のレジス
ト材を使用できない場合は、例えば、酸性ニツケ
ルメツキ等の酸性メツキにより無電解メツキを実
施すればよい。
Note that the through-hole plating process is not limited to the processes shown in FIGS. 10 to 12,
For example, it can also be implemented through the procedures shown in FIGS. 16 to 18. That is, through hole 17
A resist mask 19' is formed on the surface of the insulating base material 16 on which a resist mask 19' is formed, excluding areas where it is not desirable to form a flash circuit, such as the land portion and, if necessary, a connector portion, etc. (FIG. 16). Next, a thin copper layer 18' is formed by chemical copper plating (FIG. 17).
Subsequently, a through-hole plating layer 20' is formed by electrolytic plating (FIG. 18). Thereafter, the resist mask 19' is removed and the copper thin film 15 is etched in the same manner as above. (Figure 14). According to this through-hole plating process, it is possible to perform electroless plating and through-hole plating in succession, so there is an advantage that workability is improved. However, in the above process, since electroless plating, that is, chemical copper plating is performed after the resist mask 19' is formed, the resist material must contain, for example, catalyst poison and an alkaline non-alkaline material to prevent electroless plating. It is desirable to select an alkali-resistant material so that it will not be attacked by the electrolytic plating solution. If an alkali-resistant resist material cannot be used due to various restrictions, electroless plating may be performed using acid plating such as acid nickel plating.

次いで、銅薄膜15及び導体回路13,13′
の表面のエツチングを行い、導体回路板を完成す
る(第1図m、第14図)。この時、必要に応じ
てスルーホールメツキ層20を例えばドライフイ
ルムを使用したテンテイング法等により保護して
もよい。このエツチング工程は、例えば、湿式エ
ツチングにより実行することが可能である。この
工程により、積層体の両面の導体回路13,1
3′に挟まれた各領域では、絶縁基材16が露出
した状態となる。
Next, copper thin film 15 and conductor circuits 13, 13'
The conductor circuit board is completed by etching the surface (Fig. 1m, Fig. 14). At this time, the through-hole plating layer 20 may be protected, for example, by a tenting method using a dry film, if necessary. This etching step can be performed, for example, by wet etching. Through this process, the conductor circuits 13, 1 on both sides of the laminate
The insulating base material 16 is exposed in each region sandwiched between the regions 3'.

更に、上記工程終了後に所望により、導体回路
板の両面にソルダーレジスト印刷を行つて、ソル
ダーレジスト層21を形成してもよい(第1図
n、第15図)。
Furthermore, after the above steps are completed, if desired, solder resist printing may be performed on both sides of the conductive circuit board to form a solder resist layer 21 (FIG. 1n, FIG. 15).

上記実施例においては、孤立する導体回路とし
て、所定間隔以上離隔した2個の導体回路13,
13′を有する導体回路板について記述したが、
孤立する導体回路としてはこれに限るものではな
く、基板上の回路部分と離隔して設けられた端
子、或いは、同様に回路部分と離隔する外枠等、
その少なくとも一側に所要の間隔を経て導体部分
が存在しないような導体部分を有するものであれ
ば上記本発明の製造工程を適用することは極めて
有効である。
In the above embodiment, two conductor circuits 13, which are separated by a predetermined distance or more, are used as isolated conductor circuits.
Although we have described a conductor circuit board having a
Isolated conductor circuits are not limited to these, but include terminals provided separately from the circuit part on the board, or an outer frame similarly separated from the circuit part, etc.
It is extremely effective to apply the manufacturing process of the present invention to any device that has a conductor portion on at least one side of which there is no conductor portion after a required interval.

尚、上記実施例においては、金属薄膜として導
体回路と同種の金属即ち銅薄膜を形成した場合に
ついて記述したが、金属薄膜として導体回路と異
種の金属を用いると第14図に示した金属薄膜の
エツチング工程において、金属薄膜のみを選択的
にエツチングするエツチヤントを使用することに
より作業性が向上するという利点がある。
In the above embodiment, a case was described in which the metal thin film was formed of the same type of metal as the conductor circuit, that is, a copper thin film, but if a metal of a different type than the conductor circuit is used as the metal thin film, the metal thin film shown in FIG. In the etching process, there is an advantage that workability is improved by using an etchant that selectively etches only the metal thin film.

(発明の効果) 以上説明したように本発明によれば、平板状導
電基材表面の導体回路形成領域及び導体回路のう
ち、孤立する導体回路に隣接するダミー回路形成
領域を除く領域にレジストマスクを形成する工程
と、この平板状導電基材に電解メツキを施して前
記平板状導電基材に導体回路及びダミー回路を形
成する工程と、前記レジストマスクを剥離する工
程と、平板状導電基材表面及び導体回路を覆つて
金属薄膜を形成する工程と、斯く導体回路が形成
された平板状導電基材2個を該導体回路を互いに
対向させ、絶縁基材を介して積層して一体に圧着
又は加熱圧着し積層体を形成する工程と、この積
層体から平板状導電基材のみを剥離する工程と、
この積層体にスルーホールを穴明け加工したのち
スルーホールの内壁面及び前記積層体の両面にス
ルーホールメツキを施す工程と、前記導体回路同
士を電気的に接続する前記金属薄膜をエツチング
除去する工程とから構成したので、導体回路の形
成時にエツジビードの過度な成長を抑制して、回
路の膜厚、回路幅等、回路設計値からの逸脱を防
止し、高周波回路にあつては高周波特性の低下を
防止するなどの効果を奏する。しかも、転写性及
びスルーホールメツキ工程における通電性を良好
に保持することができるという種々の利点を有す
る。
(Effects of the Invention) As explained above, according to the present invention, a resist mask is applied to the conductor circuit formation area on the surface of a flat conductive base material and the area of the conductor circuit excluding the dummy circuit formation area adjacent to the isolated conductor circuit. forming a conductor circuit and a dummy circuit on the flat conductive base material by electrolytically plating the flat conductive base material; peeling off the resist mask; A step of forming a metal thin film covering the surface and the conductor circuit, and two flat conductive base materials on which the conductor circuit is formed, the conductor circuits facing each other, laminated with an insulating base material in between, and crimped together. or a step of heat-pressing to form a laminate, and a step of peeling only the flat conductive base material from this laminate;
After drilling through holes in this laminate, through-hole plating is performed on the inner wall surfaces of the through holes and both surfaces of the laminate, and a step of etching away the metal thin film that electrically connects the conductor circuits. This structure suppresses excessive growth of edge beads during the formation of conductor circuits, prevents deviations from circuit design values such as circuit film thickness and circuit width, and prevents deterioration of high frequency characteristics in the case of high frequency circuits. It has the effect of preventing Furthermore, it has various advantages such as being able to maintain good transferability and electrical conductivity in the through-hole plating process.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る導体回路板の製造方法の
製造手順を示す工程フローチヤート、第2図乃至
第15図は、第1図に示す各工程における導体回
路板の断面構成図、第16図乃至第18図は、第
1図におけるスルーホールメツキ工程の他の実施
態様を示す導体回路板の断面構成図、第19図は
従来の導体回路板の製造方法における導体回路形
成工程を示す断面構成図である。 5,5′…エツジビード、11…平板状導電基
材、12,19…レジストマスク、13,13′
…導体回路、13″…ダミー回路、15…金属薄
膜、16…絶縁基材、17…スルーホール、2
0,20′…スルーホールメツキ層。
FIG. 1 is a process flowchart showing the manufacturing procedure of the method for manufacturing a conductive circuit board according to the present invention, FIGS. 2 to 15 are cross-sectional configuration diagrams of the conductive circuit board in each process shown in FIG. 18 are cross-sectional configuration diagrams of a conductor circuit board showing other embodiments of the through-hole plating process in FIG. FIG. 5, 5'... Edge bead, 11... Flat conductive base material, 12, 19... Resist mask, 13, 13'
...Conductor circuit, 13''...Dummy circuit, 15...Metal thin film, 16...Insulating base material, 17...Through hole, 2
0,20'...Through hole plating layer.

Claims (1)

【特許請求の範囲】 1 平板状導電基材表面の導体回路形成領域及び
導体回路のうち、孤立する導体回路に隣接するダ
ミー回路形成領域を除く領域にレジストマスクを
形成する工程と、この平板状導電基材に電解メツ
キを施して前記導電基材に導体回路及びダミー回
路を形成する工程と、前記レジストマスクを剥離
する工程と、導電基材表面及び導体回路を覆つて
金属薄膜を形成する工程と、斯く導体回路が形成
された平板状導電基材2個を該導体回路を互いに
対向させ、絶縁基材を介して積層して一体に圧着
又は加熱圧着し積層体を形成する工程と、この積
層体から平板状導電基材のみを剥離する工程と、
この積層体にスルーホールを穴明け加工したのち
スルーホールの内壁面及び前記積層体の両面にス
ルーホールメツキを施す工程と、前記導体回路同
士を電気的に接続する前記金属薄膜をエツチング
除去する工程とからなることを特徴とする導体回
路板の製造方法。 2 前記導体回路及びダミー回路を形成したの
ち、ダミー回路の少なくとも一部を除去する工程
を有することを特徴とする特許請求の範囲第1項
記載の導体回路板の製造方法。
[Scope of Claims] 1. A step of forming a resist mask in the conductor circuit formation region and the conductor circuit on the surface of the flat conductive base material, except for the dummy circuit formation region adjacent to the isolated conductor circuit, and A step of electrolytically plating a conductive base material to form a conductor circuit and a dummy circuit on the conductive base material, a step of peeling off the resist mask, and a step of forming a metal thin film covering the surface of the conductive base material and the conductor circuit. and a step of forming a laminate by placing two flat conductive substrates on which conductor circuits are formed so that the conductor circuits face each other, laminating them with an insulating substrate interposed therebetween, and press-bonding or heat-pressing them together; A step of peeling only the flat conductive base material from the laminate;
After drilling through holes in this laminate, through-hole plating is performed on the inner wall surfaces of the through holes and both surfaces of the laminate, and a step of etching away the metal thin film that electrically connects the conductor circuits. A method for manufacturing a conductor circuit board, characterized by comprising the steps of: 2. The method of manufacturing a conductor circuit board according to claim 1, further comprising the step of removing at least a portion of the dummy circuit after forming the conductor circuit and the dummy circuit.
JP25057387A 1987-10-06 1987-10-06 Manufacture of conductive circuit board Granted JPH0194695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25057387A JPH0194695A (en) 1987-10-06 1987-10-06 Manufacture of conductive circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25057387A JPH0194695A (en) 1987-10-06 1987-10-06 Manufacture of conductive circuit board

Publications (2)

Publication Number Publication Date
JPH0194695A JPH0194695A (en) 1989-04-13
JPH0469838B2 true JPH0469838B2 (en) 1992-11-09

Family

ID=17209898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25057387A Granted JPH0194695A (en) 1987-10-06 1987-10-06 Manufacture of conductive circuit board

Country Status (1)

Country Link
JP (1) JPH0194695A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100601485B1 (en) * 2004-12-30 2006-07-18 삼성전기주식회사 BA package substrate and its manufacturing method
KR100782403B1 (en) * 2006-10-25 2007-12-07 삼성전기주식회사 Circuit Board Manufacturing Method
KR100782407B1 (en) * 2006-10-30 2007-12-05 삼성전기주식회사 Circuit Board Manufacturing Method
KR100966336B1 (en) * 2008-04-07 2010-06-28 삼성전기주식회사 High Density Circuit Board and Formation Method
JP6381997B2 (en) * 2014-06-30 2018-08-29 京セラ株式会社 Method for manufacturing printed wiring board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5249468A (en) * 1975-10-20 1977-04-20 Fujitsu Ltd Method of producing bothhside printed circuit board
JPS5939917B2 (en) * 1980-12-29 1984-09-27 株式会社小糸製作所 Printed circuit conductor and printed circuit board using the conductor

Also Published As

Publication number Publication date
JPH0194695A (en) 1989-04-13

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