JPH0469866A - Digital data reader - Google Patents

Abstract

PURPOSE:To improve reading accuracy for original data by setting reading timing for digital data in a state where synchronizing cell having the maximum frequency is taken as reference. CONSTITUTION:At about n-fold frequency (n:integer>=3) of the frequency of the digital data which is a read object, a ternary counter 4 and a decoder 6 detect what number -th of synchronizing cell a read clock SCK which consists of 1st to n-th synchronizing cells is. AND circuits 7-9 and counters 10-12 measure what frequency the specified level(high level '1' or low level '0') of the digital data appears in the respective synchronizing cells of the read clock. Then, by taking the synchronizing cell having the maximum frequency as the reference, the read timing for the digital data is set. Thus, the original data is accurately read even though the data is varied on a time base in the case of reading the digital data which flows asynchronously to a system clock.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a digital data reading device suitable for use in reading digital data flowing asynchronously with respect to a reading clock, for example. [Summary of the Invention] The present invention provides a digital data reading device that is suitable for reading digital data flowing asynchronously with respect to a reading clock. period detecting means for detecting the number of the synchronous cell of the read clock consisting of the first synchronous cell to the nth synchronous cell at a frequency (n is an integer of 3 or more); and a frequency measuring means for measuring the frequency at which the reading clock enters each of these synchronous cells, and by setting the reading timing of the digital data based on the synchronous cell with the maximum frequency, the digital data is aligned in the time axis direction. This allows the original data to be read accurately even if it fluctuates. [Prior Art] For example, in a magnetic disk recording/reproducing device, an asynchronous clock system is sometimes adopted in which the reproduced data is read using a system clock that is asynchronous with the reproduced data. Fig. 3 shows an example of a timing chart of a conventional glue [synchronous 11xkunster].
Digital data (...011, 0010...
. . ) is recorded with a period T I). Since the reproduction output of this magnetic disk is approximately equal to the differential of its recording current, its reproduction output and its rectified output are as shown in FIGS. 3B and C, respectively. The binarized digital data Dp becomes asynchronous data. Figure 3 (1) shows the system clock SCK with period TS for reading the asynchronous data, and in this example, the frequency of τ clock SCK (1/TS>) is the frequency of the asynchronous data (data rate 1/TS). '1'I)).For example, the frequency of asynchronous data is set to 4
MB (z, ri11tsuk S CK frequency is 12MHz
It is. However, as described in 0゛〉 below, the reproduced asynchronous data contains jitter, which is a fluctuation in the time axis, l-, and the frequency of the asynchronous data fluctuates. The frequency of Nori1-]Tsuku SCK is)V-
On average, it is only approximately equal to the frequency of the asynchronous data. In addition, as this tarokku SCK, for example, a crystal oscillator (
This is also used when recording)

A reference clock is used. However, the Dtsuku SC
As K, for example, a clock extracted from the reproduced output by a so-called self-clock method may be used. Such self-clock extraction includes, for example, a case where a clock extracted in a servo zone or the like is used to read data in a data sector following that servo zone. If asynchronous data obtained by binarizing the rectified output shown in FIG. 3C is latched at each rising edge of the system clock SCK, synchronous data as shown in FIG. 3E is obtained. The frequency of this synchronized data is 13 times that of the original data, and the amount of data is also three times that of the original data.
It is necessary to compress it to /3. As a compression method, the clock SCK is divided into cells each having three cycles, and if a target cell contains "1", the value of that cell is set to "1", and the target cell is There is a method in which the value of that cell is regarded as "0" when "1 pass" is not included in the cell. In this case, the unit of each period of the tarock SCK is regarded as a synchronization cell, and the 3nth cell is th (n=-
〇, 1. ), the series of synchronous cells at 3 period intervals is the first synchronous cell, and the (3n+1)th σ series of synchronous cells is the second synchronous cell, and the (3n, @-2)th series If the synchronization cell of is the third synchronization cell, its tarokk S
The method of dividing CK into cells each having three periods includes the first
division into cells centered on the synchronized cell (for example, Fig. 3F)
), division into cells centered on the second synchronous cell (for example, FIG. 3G), and division into cells centered on the third synchronous cell (for example, FIG. 3H). For example, when using the cell in FIG. Since the th cell contains a synchronization cell with a value of "1", the value of that cell is considered to be "1". Normally, no matter which of the three cell divisions is used, the data strings obtained from the three series of cells are the same, respectively...l 1.
001..., which is equivalent to the original data string in FIG. 3A. However, as shown in FIG. ) is inverted, so only the data string obtained from cell F in Figure 3 is...11010...
However, the data strings obtained from the other two types of cells do not change. Similarly, FIG. 4 shows a case where one cell (D in FIG. 4) is constructed from each five synchronous cells (C in FIG. 4) of the system clock 5CK (B in FIG. 14), and if asynchronous data ( Fourth
Assuming that the position of the pulse Q in Figure A) is on the central synchronous cell of the cell, the pulse Q fluctuates by two periods of the clock SCK in the negative direction and the positive direction on the time axis, and the pulse QA and Even if the QB changes, the data string read from each cell does not change. Generally, when each cell is composed of an odd number of synchronous cells, in order to minimize the error that occurs in the obtained data string even if there is jitter,
For cells whose original value is "1", it is necessary to set the value of the central synchronization cell to "1". Also, when each cell is composed of an even number of synchronous cells, for a cell whose original value is 1, the value of one of the two central synchronous cells becomes 1. Conventionally, in order to ensure that the value of the central synchronous cell becomes "1", for example, the first "1" that appears in the data area
The cells were divided so that the data in the synchronous cell in the center of the cell corresponding to the data became the data in the central synchronous cell. [Problems to be Solved by the Invention] However, determining cell division based on the first data "1" that appears may result in an incorrect cell division method when the first data fluctuates due to jitter. There is an inconvenience in selecting . In addition, in order to reduce the effect of jitter, methods of lowering the data rate or increasing the frequency of the system clock SCK may be considered, but lowering the data rate will lead to a decrease in data recording density. I don't like it. In addition, increasing the frequency of the clock SCK to improve the resolution of asynchronous data capture is
This necessitates the use of high-speed, expensive integrated circuits and makes system design difficult. In view of the above, the present invention is to enable accurate reading of original data even if the data fluctuates on the time axis when reading digital data flowing asynchronously with respect to the system clock. With the goal. [Means for Solving the Problems] As shown in FIG. 1, for example, the digital data reading device according to the present invention reads data at a frequency approximately n times the frequency of digital data to be read (n is an integer of 3 or more). A cycle detection means (4, 6>) for detecting the number of the read clock SCK consisting of the 1st to nth synchronous cells, and a predetermined level (4, 6>) of the digital data.
frequency measuring means (7) to (12) for measuring the number of times a high level "1" or a low level "0") enters each of the synchronous cells of the read clock, and the maximum frequency of the synchronous cell is used as a reference. The timing for reading the digital data is set as follows. ≦n) When the number of times that the digital data example level “1” enters the synchronous cell reaches the maximum, the system clock is changed in series for n cycles so that the nth synchronous cell is in the center. into cells. Then, for example, the value of a cell containing a synchronized cell with a value of "1" is regarded as "1",
By regarding the value of a cell containing only synchronous cells with a value of "0" as "0", the original data can be read accurately. In this case, for example, the high level “1” of the digital data
Since the system clock can be decomposed into a series of cells so that the synchronized cell with the maximum frequency of "" is in the center, even if some of the digital data fluctuates on the time axis due to jitter, the jitter will not be affected. The original "1" part of the digital data when there is no data enters the synchronization cell in the center of that cell. Therefore, even if there is jitter, the original data can be read accurately. [Operation] This is how it works. According to the present invention, for example, the n-th (1≦m [Example]) An example of the present invention will be explained below with reference to FIGS. 1 and 2. FIG. An example digital data reading circuit is shown in FIG. 1, in which (1) and (2) are respectively input terminals;
<3) is a synchronous circuit, (4) is a ternary counter, and the system shown in FIG. The clock SCK is supplied to the data input terminal of the synchronous circuit (3) via the input terminal (2)4.
Asynchronous data ND having a frequency approximately ⅓ of the frequency of is supplied, and a reset signal is supplied to the clear terminal C[, of the ternary counter (4) via the connection terminal (5). As this asynchronous data ND, the rectified output shown in FIG. 3C and a signal obtained by binarizing this rectified output at a predetermined level can be assumed. The synchronous circuit (3) generates synchronous data SD (FIG. 2, 13) synchronized with the clock SCK from the asynchronous data NII). The most pure synchronous circuit (3) is a D-type flip-flop. Furthermore, when the asynchronous data ND is a mountain-shaped signal as shown in FIG. It is also possible to use a circuit that outputs a signal that becomes high level "1" in the next cycle when the ternary counter (4) is included. ]-da (6), and this Deni 111-da (6) Te:v
- The outputs corresponding to 0, 1, and 2 are supplied to one input terminal of AND circuits (7), (8), and (j)), and these AND circuits (7) to (9) Synchronous data SD is commonly supplied to the other input terminal of the AND circuits (7) to (9), and the outputs of these AND circuits (7) to (9) are input to counters (10) to (12), respectively.
) paste] is supplied to the vine terminal CK, and these counters (1
Commonly connected to the clear terminal CL of 0) to (12) 'T-
Reset (No. 2) is supplied via the counter (13). The 81 number outputs of these counters (10) to (12) are respectively supplied to the discrimination circuit (14), and this discrimination amount/path (14) is connected to the counter (1 , 0), (11) or (12) is the maximum, the 2-bit output becomes 0, 1 or 2, respectively, through the connecting terminals 15) and (16) (not shown) supplied to the control circuit. When the count outputs are equal, the discrimination circuit (14) outputs, for example, the data with the smaller value. In addition, the control circuit also includes connection terminals (17) and (18).
The 2-bit counting output of the ternary counter (4) is also supplied via the ternary counter (4). (19) indicates a delay circuit, and the synchronous data SD output from the synchronous circuit (3) is sent to S via this delay circuit (19).
R7 is supplied to the set terminal of the sophron block circuit (20), and the 2-bit 31 number output of the ternary counter (4) is supplied to the two input terminals of the NOR circuit (21). The output of is supplied to the I noset terminal of the flip-flop circuit (20) and the tallock terminal of the D-type flip-flop circuit (23) through a pulse generation circuit (22) that generates a pulse at the rising edge of the input signal.
The non-inverted output of the 111 circuit (20) is supplied to the data input terminal of the flip-flop circuit (23). The output of this flip-flop circuit (23) becomes the read data RD of this example, and this read data RD is supplied to a control circuit (not shown) via an output terminal (24). The delay time in the delay circuit (19) is determined by the ternary counter (4), the NOR circuit (21) and the pulse circuit (22).
is set approximately equal to the sum of the delay times in . To explain the operation of this example, first, as shown in FIG. 2A, at time t1, the ternary counter (4) and the counter (
10) to (12) are reset. In this case, the count output of the ternary counter (4) changes as <012012... as shown in FIG. 2C, so the first synchronous cell a ( a series of synchronous cells whose counting output of the ternary counter (4) is O), a series of synchronous cellular cells whose counting output of the ternary counter (4) is 1;
Cells consisting of three types of three types of synchronous cells centered on synchronous cell C (a series of synchronous cells whose count output of the ternary counter (4) is 2) are called cell A, cell B, and cell C, respectively. . For example, as shown in FIG. 2 B-D, it is defined that when the value of the synchronization data SD becomes "1" in the synchronization cell a at the center of the cell, the frequency of that cell A increases by 1. . Similarly, it is defined that when the value of synchronous data SD becomes "1" in synchronous cells b and c at the center of cells B and C, the frequency of cell B and the frequency of cell C increase by 1, respectively. In the circuit shown in FIG. 1, the frequencies of each of cells A to C can be counted as follows. That is, because a signal that becomes "1" when the count value of the ternary counter (4) is 0 is supplied to one input terminal of the AND circuit (7) by the action of the decoder (6), the AND circuit (7) The counter (10) corresponding to the circuit (7) has part 3.
A counting pulse is supplied only when the count value of the advance counter (4) is 0 and the synchronization data SD is 1''.Therefore, the frequency of cell A is counted by the counter (10).Similarly, and Since one input terminal of the circuits (8) and (9) is supplied with a signal that becomes "1" when the count value of the ternary counter (4) is 1 and 2, respectively, the AND circuit (8) ) and (9), counters (12) and (13) respectively count the frequency of cell B and the frequency of cell C. When the recording medium is a magnetic disk, the frequency of cells A to C is counted in this way. For example, the area after the header of the servo zone can be used as the area for measuring the frequency.When the synchronization data SD has a structure as shown in Fig. 2, after a predetermined period of time has elapsed from the initial time t1. time t
2, cell A1 as shown in the second diagram, E and F.
The frequencies of cell B and cell C are 3.7 and 1, respectively. Therefore, since the frequency of cell B is the largest, at time t2, data with a value of 1 corresponding to cell B is sent from the discrimination circuit (14) to the control circuit (not shown) via the connection terminals (15) and (16). Supplied. Therefore, this control circuit selects cell B as the cell for reducing the frequency of the synchronous data SD in FIG. 2B to 1/3. However, cell B
is a cell where the count value of the ternary counter (4) of the central synchronous cell is 1, but in this example, that cell B has already been selected, so its control circuit performs an operation to set the number of ships. There's no need. However, for example, if the frequency of cell A is the largest as a result of frequency measurement, the ternary counter (4)
Since the count value of the ternary counter (4) is set to 1 when the count value of (4) Reset the count value. In addition, when a cell is generally composed of n (n = 3.4...) synchronous cells, if n is an odd number, select the cell that has the highest frequency of "1" falling in the central synchronous cell. However, when n is an even number, the cell with the largest number of times that 1" fits in the two central synchronous cells is selected. After cell B is finally selected, the NOR circuit (21) outputs a signal that changes from #0 to “1” when the count value of the ternary counter (4) changes from 2 to 0, and the pulse generator (22) outputs the output of the NOR circuit (21). “0”
A pulse that becomes "1" for a predetermined period when the signal changes from "1" to "1" is supplied to the reset terminal of the flip-flop circuit (20) and the clock terminal of the flip-flop circuit (23). Also, the flip-flop circuit in the previous stage20)
Since the synchronous data SD is supplied to the set terminal of through the delay circuit (19), the output of the flip-flop circuit (23) at the subsequent stage is determined when the count value of the ternary counter (4) changes from 0 to 0 again. If the synchronized data SD becomes "1" even once before returning, it becomes "1", and if the synchronized data SD remains "0", it becomes "0". Therefore, the read data RD which is the output of the flip-flop circuit (23) in this example is the system clock SCK
It is equal to the data obtained when (synchronous data SD) is divided by cell B. Furthermore, in this example, while reading data after selecting that cell, the frequencies of cells A to C are measured at predetermined time intervals in parallel, and the frequency where '1' falls in the central synchronous cell is large. The selection of the cell is updated each time the cell changes.As described above, according to this example, the maximum frequency among the frequencies of cell A to cell C is always determined at a predetermined time interval.・The asynchronous data is synchronized in the cell with the maximum frequency. Therefore, even if the position of "1" of the asynchronous data changes due to jitter during some period during the measurement of the frequency, the final If the value is correct (i.e. without jitter)
When the value of the central 11th period cell is "1", the cell whose value is "1" can be selected.If the final cell is generally composed of n synchronous cells, then the thick- This makes the asynchronous data one on the time axis!I
There is an advantage that the asynchronous data can be read accurately even if the fluctuation does not exceed I(rl-],,)/2 synchronous cells. If you want to measure the maximum frequency of this sea urchin,
Unlike when calculating the average value, there is no need to perform division fj, and all integer/bell processing (→-1 increment, condition judgment, etc.) is possible, so it is easy to execute with a microprocessor, etc. There is. Further, the frequency measurement area may include data of "0", and the cell with the maximum frequency can be measured at t1 at any time regardless of the number of data. It should be noted that the present invention is not limited to the series of embodiments, and can of course take various configurations without departing from the gist of the present invention, such as application to an apparatus that uses an optical disk as a recording medium. [Effects of the Invention] According to the present invention, the reading timing of digital data is set based on the synchronized cell with the maximum frequency, so even if the digital data fluctuates in the time axis direction, the original data can be accurately read. There is a benefit in being able to read.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a digital data reading circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram explaining the cell selection operation of the embodiment, and FIG. 3 is a diagram of a conventional asynchronous clock system. FIG. 4 is a timing chart for explaining the cell selection method. . (3) is a synchronous circuit, (4) is a ternary counter, (6) is a decoder, (10), (11), and (12> are each counter, and (14) is a discrimination circuit. Agent: Matsukuma Hide Mori Kurinoi Synchronous clock system Fig. 3 How to choose cells! Explanatory diagram Fig. 4

Claims (1)

[Claims] Approximately n times the frequency of the digital data to be read (
n is an integer of 3 or more) from the first synchronous cell to the nth
period detecting means for detecting the number of synchronous cells in the read clock consisting of synchronous cells; and frequency measuring means for measuring the number of times a predetermined level of the digital data enters each of the synchronous cells of the read clock. A digital data reading device, characterized in that the reading timing of the digital data is set based on the maximum frequency of the synchronous cells.