JPH0470013A - Parallel processing type frame synchronizing system - Google Patents

Abstract

PURPOSE:To omit the frame synchronizing circuits and the parallel signal rearraying circuits in number accordant with the array state of parallel signals and to extremely reduce the circuit scale by applying the feedback control to the S/P conversion timing based on the result of frame synchronization. CONSTITUTION:The parallel signals 2 are inputted to a frame synchronization detecting circuit 13, and an intra-device frame counter 14 outputs an intra-device frame pulse 4. The reception signal inputted to the circuit 13 is compared with the pulse 4 on a time base. Then the coincidence/discordance of timing is detected and an S/P conversion control signal 5 is outputted. When no coincidence of timing is detected, the feedback control is applied to an S/P conversion timing generating circuit 12 with the signal 5. Then an S/P conversion timing signal 3 has a bit shift. Thus the array of the signals 2 is outputted with shift of one bit with the signal 3 that had a l-bit shift. As a result, both the frame synchronizing circuits end the parallel signal rearraying circuits can be omitted in number accordant with the array state of signals 2. Thus the circuit scale is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a parallel processing type frame synchronization method, and in particular to a frame synchronization bit of a high-speed digital signal that requires serial-to-parallel conversion in frame synchronization of a digital multiplexer. This paper relates to a parallel processing type frame synchronization method using centralized monitoring.

[Conventional technology]

Conventionally, this type of parallel processing frame synchronization method has been
The timing of parallel conversion is arbitrary, a frame synchronization circuit is arranged according to the arrangement state of the parallel signals, and the output is obtained by rearranging the parallel signals based on the arrangement state in which frame synchronization has been established.

[Problem to be solved by the invention]

The conventional parallel processing type frame synchronization method described above is
Since the timing of parallel conversion is arbitrary, a number of frame synchronization circuits and parallel signal re-arrangement circuits are required depending on the arrangement state of the parallel signals, which has the drawback of increasing the circuit scale.

[Means to solve the problem]

The method of the present invention is a parallel processing type frame synchronization method in which frame synchronization is performed after serial-to-parallel conversion of a high-speed digital signal. It has a configuration that detects coincidence/mismatch on the axis and matches the conversion timing of parallel signals with the frame phase within the device to establish frame synchronization.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. Series-
The parallel conversion circuit 11 receives the serial-to-parallel conversion timing signal 3 from the serial-to-parallel conversion timing generation circuit 12.
Convert input signal 1 to parallel signal 2.

The parallel signal 2 is input to the frame synchronization detection circuit 13.

An in-device frame counter 14 that counts based on the frame phase in the device outputs an in-device frame pulse 4, and the received signal input to the frame synchronization detection circuit 13 is compared with the in-device frame pulse 4 on the time axis, and the difference between the two is Timing coincidence/mismatch is detected and a serial-parallel conversion control signal 5 is output. Here, in the case of a mismatch, the serial-parallel conversion timing generation circuit B12 is feedback-controlled by the serial-parallel conversion control signal 5, and the serial-parallel conversion timing signal 3 is bit-shifted. The serial-to-parallel conversion timing signal 3 shifted by 1 bit causes the parallel signal 2 to shift its signal array by 1 bit and output it. Such operations are repeated until the frame synchronization detection circuit 13 obtains a match detection result, and when a match is found, the in-device frame counter 14 performs backward protection and establishes frame synchronization. With this frame synchronization established, the parallel signal 2 obtains a regular signal arrangement.

〔Effect of the invention〕

As explained above, the present invention performs feedback control of the timing of serial-to-parallel conversion using the frame synchronization detection result, thereby eliminating the need for a number of frame synchronization circuits and parallel signal re-arrangement circuits depending on the arrangement state of parallel signals. This has the effect of significantly reducing the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Input signal, 2...Parallel signal, 3...Series-
Parallel conversion timing signal, 4... Frame pulse within the device, 5... Serial-to-parallel conversion control signal, 11... Serial-to-parallel conversion circuit, 12... Serial-to-parallel conversion timing generation circuit, 13... Frame synchronization detection circuit, 14...Internal frame counter.

Claims (1)

[Claims] In a parallel processing type frame synchronization method that performs frame synchronization after serial-to-parallel conversion of a high-speed digital signal, a frame synchronization bit corresponding to the frame phase within the device and a serial
A parallel processing type frame synchronization method that detects coincidence/mismatch on the time axis with a parallel signal after parallel conversion, and establishes frame synchronization by matching the conversion timing of the parallel signal with the internal frame phase of the device.