JPH0470208A - Noise removal circuit - Google Patents

Abstract

PURPOSE:To remove noise which cannot be latched at the rise time of a clock noise signal which could not be removed by providing an edge detecting circuit in a noise removal circuit. CONSTITUTION:A signal inputted to an input terminal A changes to an L-state until a clock inputted to an input terminal B is inputted three times. When DFF 1 latches the L-state, the outputs of DFF 1-3 do not coincide and the outputs of AND gates 4 and 5 also do not change. Thus, the output of J-KFF 6 does not change too. When the change of data which is not detected by the clock inputted to the input terminal B is detected by a counter counting the edge of the change of data and a rise edge detection circuit 13 provided with DFF, an AND gate 15 prevents the output of an AND gate 14 from being transmitted to J-KFF 6. Consequently, a waveform inputted to the input terminal A is not outputted from an output terminal Y.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise removal circuit formed of a logic circuit that removes noise.

[Conventional technology]

Figure 3 is a circuit diagram of a conventional noise removal circuit. In the figure, (1) to (3) are D flip-flops, (4), (5
) is an AND gate in which the Q and QC outputs of D flip-flops (1) to (3) are manually input, respectively, and (6) is an AND gate (4).

The outputs of (5) are input to J and J-, respectively, through flip-flops, the input terminal A is the data input, and the input terminal B is the clock input. FIG. 4 is an operation timing waveform diagram of the circuit of FIG. 3.

Next, the operation will be explained. The D flip-flops (1) to (3) are shifted by a signal (7) input to input terminal A or a clock signal input to input terminal B.

For example, if the D flip-flop has three stages as shown in the figure,
While the clock input to input terminal B is manually input three times,
If the input signal B does not change, the outputs of each D flip-flop will match, and the outputs of the three-man power AND gates (4) and (5) will change.

The change is transmitted to the flip-flop (6) in J-,
It is output to the output terminal Y by the next clock (8).

At this time, if the signal changes before the clock is input three times, the outputs of the D flip-flops (1) to (3) will not match, and the output of the J- flip-flop (6) will not change.

Therefore, the period width of the clock input to input terminal B is T
, when the number of stages of D flip-flops is n, a waveform with a cycle width less than TXn is not allowed to pass.

Furthermore, by changing the values of n and T, the period width of the waveform to be passed can be easily changed.

[Problem to be solved by the invention]

Since the conventional noise removal circuit is configured as described above, the input signal input to the D flip-flop is latched by the rising edge (9) of the clock.

Therefore, even if the signal changes at a time other than when clock B rises, as shown in waveform (10), this cannot be detected and waveform (10)
There was a problem that the output was output as shown in 1).

This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain noise removal that prevents the signal from passing if it changes even once while the signal is less than TXn.

[Means to solve the problem]

The noise removal circuit according to the present invention is provided with an edge detection circuit that uses a counter to detect edges in changes in an input signal input manually to the input terminal A of the noise removal circuit.

[Effect]

The noise removal circuit according to the present invention detects an edge detection circuit if the input signal A changes between when the input signal A changes and when the clock input signal B is input once, and the waveform of the input signal A is changed to the output Y. There is no output from.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a noise detection circuit which is an embodiment of the present invention, and the figure shows a case where the number of stages n of D flip-flops is three. In the figure, (13) is a rising edge detection circuit for input signal A, (14) is a falling edge detection circuit for input signal A, and (15) is a rising edge detection circuit for detecting an edge of input signal A. AND gate (16) that controls the output of (4) is A when the falling edge detection circuit (14) detects an edge.
This is an AND gate that controls the output of the ND gate (5), and the AND gates (15) and (+6) are input to the J- terminal and the K terminal of the flip-flop (6), respectively.

FIG. 2 is a timing waveform diagram of the circuit of FIG. 1.

Next, the operation will be explained. The input signal input to input terminal A changes from the "L" state (low potential state) to the r)[J state (high potential state) as shown in FIG. The D flip-flops (1) to (3) are sequentially shifted according to the input clock signal.

If the signal input to input terminal A does not change while the clock signal is input three times, the D flip-flop (1
) to (3) Q outputs are all in "H" state, 3-man power AND
The output of the gate (4) changes to the "H" state. The change is inputted to J- via the AND gate (15) to one of the foot flops (6). At that time, the QC outputs of flip-flops (1) to (3) are in the "L" state, so
The flip-flop (6) is manually set to the "H" state at J-, and by the next clock, fJ is output from the output terminal Y.
The status is output (see FIG. 2 (8)).

At this time, by the time the clock input to input terminal B is manually input three times, the signal input to input terminal A is
If the state changes to "L" and the "L" state is latched by the D flip-flop (1), the D flip-flop (1) ~
Since the outputs of (3) do not match and the outputs of AND gates (4) and (5) do not change, the flip-flop (6) is connected to J-.
The output of is also unchanged.

In addition, as shown in FIG. 2 (10), a counter that counts the edges of data changes even when undetected data changes are detected by the clock input to input terminal B, and a rising edge detection system equipped with a D flip-flop. Circuit (13
), the AND gate (15) prevents the output of the AND gate (14) from being transmitted to the flip-flop (6). Therefore, the waveform shown in FIG. 2 (10) input to the input terminal A is the waveform shown in FIG.
12) is not output.

Also, when the data input to input terminal A is in the "L" state, the D flip-flops (1) to (3) sequentially latch the "L" state by the clock, and the D flip-flops (1) to (3) The QC outputs of are aligned to the r) (J state, and the output of the three-man AND gate (5) changes to the "H" state. The change passes through the AND gate (16) and is transferred to the flip-flop (6) at J-. At that time, the Q outputs of D flip-flops (1) to (3) are in the "H" state, so the five inputs of flip-flop (6) to J- are "
"L" state is input, and the output terminal Y is input by the next clock.
The "L" state is output from.

Although the above embodiment shows a case in which three stages of D flip-flops are connected, the edge detection circuit (+3) (14) can be provided regardless of the number of stages of D flip-flops.

〔Effect of the invention〕

As described above, according to the present invention, since the edge detection circuit is provided in the noise removal circuit, it is possible to remove noise that cannot be latched at the rising edge of the clock signal, which could not be removed by the conventional noise removal circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a noise removal circuit that is an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the circuit in FIG. 1, and FIG.
The figure is a circuit diagram of a conventional noise removal circuit, and FIG. 4 is a waveform diagram showing the operation of the circuit of FIG. 3. In the figure, (1) ~
(3) is a D flip-flop, (4) (5) (
+5) (16) shows an AND gate, (6) shows a flip-flop at J-, (13) shows a rising edge detection circuit, and (14) shows a falling edge detection circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Agent Masuo Oiwa Figure 1 Figure 2 +Q r-1111--- +2 16: ANDγ- and

Claims (1)

[Scope of Claims] A noise removal circuit composed of a shift register composed of n stages of D flip-flops and a single stage JK flip-flop, comprising: an edge detection circuit composed of a counter and a D flip-flop; A noise removal circuit comprising an AND gate whose input signals are the output signal of the edge detection circuit and the output signal of the shift register, and whose output signal is the input signal of the JK flip-flop.