JPH0470262A - Picture data time base conversion circuit - Google Patents

Abstract

PURPOSE:To convert the time base of picture data at high speed through simple circuit configuration by controlling the update of the write-in address and the read-out address of a picture memory by a control pulse. CONSTITUTION:Input picture data DI is written in the picture memory 10 according to the write-in address AW, and besides, it is read out from the picture memory 10 as output picture data D according to the read-out address AR. The write-in address AW is updated successively in its address every time the control pulse Y becomes logical '1'. Besides, the input picture data DI is inputted continuously synchronously in a write-in clock CW. As for the picture data to be written in the picture memory 10, the input picture data DI at the point of time when the control pulse Y becomes logical '1' is selected and written in. Thus, by reading out continuously the picture data written in the picture memory 10 after being thinned according to the read-out address AR, the picture data whose time base is compressed can be obtained at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image data time axis conversion circuit for reducing and enlarging image data along the time axis.

"Prior Art" Conventionally, various time axis conversions of images have been put into practical use using random access memory (RAM).
Various applications such as image reduction, enlargement, and format conversion are being considered. Incidentally, in time axis conversion of moving images, the control circuit of the image memory is required to operate at high speed in order to access the image memory at high speed. For this reason, relatively large-scale dedicated hardware is used in the control circuit around the image memory.

[Problem to be solved by the invention]

Conventionally, in order to perform time axis conversion of a moving image using an image memory, there is a problem in that an image data time axis conversion circuit using relatively large-scale dedicated hardware is required.

An object of the present invention is to provide an image data time axis conversion circuit that can perform high-speed time axis conversion using simple and small-scale hardware.

[Means to solve the problem]

The image data time axis conversion circuit of the present invention includes an image memory that writes and reads image data in accordance with write and read addresses, a pulse generation circuit that generates control pulses, and a write address generator that generates the write address. and a read address generation circuit that generates the read address, and at least one of the write address generation circuit and the read address generation circuit updates the address in response to the control pulse. Further, the pulse generation circuit may be configured to generate the control pulse according to an arbitrarily set pulse train. Further, the pulse generation circuit may include a feedback shift register circuit including a plurality of registers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and shows a configuration for reducing image data on the time axis.

In the figure, an image memory 10 that stores image data, a write address generation circuit 20 that generates a write address Aw for image data in response to a write clock CW and a control pulse Y, and a write address generation circuit 20 that generates a write address Aw for image data in response to a read clock C1. A read address generation circuit 21 generates a read address AR for image data, and a pulse generation circuit 30 generates a control pulse Y for controlling the write address generation circuit 20.

Next, the operation will be explained.

The input image data D+ is written to the image memory 10 according to the write address At, and is also written to the image memory 10 according to the read address Al1.
1, output image data D from the image memory 10. The data is read out in a closed manner. By the way, the write address generation circuit 20 updates the write address Aw when the control pulse Y output from the pulse generation circuit 30 is logic "1". The operation will now be described with reference to the time chart shown in FIG. FIG. 2(a') shows an example of the control pulse Y, and FIG. 2(b) shows the write address At. The write address At is updated every time the control pulse Y becomes logic "1".

FIG. 6C shows input image data D+, which is continuously input in synchronization with the write clock CW. Same figure (
d) shows the image data to be written into the image memory 10, and the input image data DI at the time when the control pulse Y becomes logic "1" is selected and written. By continuously reading out the image data thinned out and written in the image memory 10 in this manner according to the read address 80, image data with a reduced time axis can be obtained at high speed. .

FIG. 3 is a diagram showing the pulse generating circuit 20, which is a feedback shift register composed of registers 1 to N. The initial values of each register 1 to N are simultaneously input by an initial value signal X. After that, the input initial value is the clock signal C
It cycles through registers 1 to N while shifting to the right in synchronization with w, and the contents of register N are output as control pulse Y.

Therefore, each time it is shifted from left to right N times, it returns to the initial state, so that a control pulse Y having a period of N clocks is obtained. By inputting an initial value of an arbitrary pattern to the pulse generation circuit 30, arbitrary time axis conversion becomes possible.

Although this embodiment has been described using a feedback shift register as the pulse generating circuit, other circuits may be used. Furthermore, although we have described the case where the time axis is reduced by combining the pulse generation circuit with the write address generation circuit, image data with an expanded time axis can be obtained by combining the pulse generation circuit with the read address generation circuit. is clear.

〔Effect of the invention〕

As described above, according to the present invention, by controlling the update of the write address and read address of the image memory using control pulses, it is possible to process time axis conversion of image data at high speed with a simple circuit configuration. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) shows an example of the control pulse Y, FIG. 2(b) shows the write address Aw, FIG. 2(c) shows the input image data D1, and FIG. 2(d) shows the image memory. The third section is the pulse generation circuit 30.
FIG. 1 to N...Register, 10...Image memory, 20.
...Write address generation circuit, 21-..Read address generation circuit, 30..Pulse generation circuit, AR-..Read address, AN-..Write address, Y.. Control pulse.

Claims (1)

[Scope of Claims] 1. An image memory that writes and reads image data in accordance with write and read addresses, a pulse generation circuit that generates control pulses, a write address generation circuit that generates the write address, and the an image data time axis conversion circuit comprising: a read address generation circuit that generates a read address; at least one of the write address generation circuit and the read address generation circuit updates the address in accordance with the control pulse; . 2. The image data time axis conversion circuit according to claim 1, wherein the pulse generation circuit generates the control pulse according to an arbitrarily set pulse train. 3. The image data time axis conversion circuit according to claim 1 or 2, wherein the pulse generation circuit includes a feedback shift register circuit including a plurality of registers.