JPH0470660B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a terminal control device that can control a terminal control board connecting a plurality of terminals from two control channels, the structure of the address bus between each board and the control channel is simplified. This is a terminal control method.

[Industrial Field of Application] The present invention relates to a terminal control method when a terminal control board connected to a plurality of terminals is controlled by two systems of host computers, for example, in a dual manner.

[Prior art] In the conventional device shown in Fig. 4, 1A, 1B
is the A system, B system host system bus, 2A,
2B is a control channel, and 31 and 32 are connection buses that collectively include a control signal bus, a data bus, and an address bus. 41-44... are terminal control boards, 51-5
n indicates a terminal. That is, a plurality of terminals 51 to 5n are connected to one
It is connected to two terminal control boards, and is controlled by either system A or B host computer via the terminal control board. Normally, dual control is used, with each host computer controlling approximately half of the terminals, and if an abnormal condition occurs, the normal host controls all the terminals. Usually, the channel and terminal control boards are equipped with microprocessors to perform various controls. In addition, the terminal control board has a direct memory access section 41-1.
(DMAC) to exchange data between terminals and control channels.

[Problems to be Solved by the Invention] At this time, the number of input/output signal lines such as the terminal control board 41 is extremely large. In other words, in order to connect the buses of two systems, the A system and the B system, in consideration of abnormal conditions, the number of terminals of the connecting connector terminal 41-2 is set to 2.
The design and manufacture of the back panel, especially the terminal board, became complicated and troublesome. Naturally, the price of the connecting bus was also high. SUMMARY OF THE INVENTION An object of the present invention is to provide a terminal control method in which an address register and an address decoder are provided in a control channel, and the number of address buses between a terminal control board and a control channel is reduced, in order to improve the above-mentioned drawbacks.

[Means for Solving the Problems] The means adopted by the present invention to solve the above-mentioned problems is to improve the connection between the plurality of terminals 51...5n and the plurality of terminal control boards 41...44 connected respectively. Data transfer is controlled from two control channels 2A and 2B via a connection bus, and the control channel 2
In a terminal control method in which the transferred data is stored in the channel buffer 25 in A, 2B and transferred to the host side, when data is transferred from the plurality of terminals 51...5n to each control channel 2A, 2B, A common address of the plurality of terminal control boards 41...44 is stored in advance in the address register 24, and the common address is added to the unique address transferred from the plurality of terminal control boards 41...44. Specify an area of the channel buffer 25, store the transfer data in the specified area,
A plurality of terminals 51 from each control channel 2A, 2B
...5n, specify the terminal control board 41 by decoding the address corresponding to each of the plurality of terminal control boards 41...44 using the address decoder 23 in advance,
Furthermore, the plurality of terminals 51...5 each connected to the lower side of the plurality of terminal control boards 41...44.
It is configured by specifying n using the connection bus.

[Effect]

In the present invention, when data is transferred from the terminal to the control channel direction, the terminal Since we are specifying the storage area of the channel buffer that stores the data transferred from the terminal control board to the control channel, by storing common addresses separately in advance, we can reduce the number of address buses between the terminal control board and the control channel by that amount. can be reduced.

Furthermore, when data is transferred from a control channel to a terminal, the terminal control boards connected to the terminals first specify the address by decoding the bits of a part of the address using an address decoder. The specified terminal is specified by sending the remaining address bits through the connection bus (address bus) that connects the control channel and the terminal control board. can reduce the number of address bits required to specify the terminal control board by the decoder.

[Example] Figure 1 is a diagram showing the configuration of an example of the present invention.
A and 1B are A-system and B-system host system buses, 2A and 2B are control channels, and 33 and 34 are connection buses, compared to conventional buses 31 and 32, in particular, the number of address buses is approximately half, 41, 42
... indicates a terminal control board which is the main part of the terminal control device, and 51 to 5n indicate terminals. 21 is a channel bus, 22 is a channel microprocessor, 23
is an address decoder, 24 is an address register,
25 is a channel buffer, and 26 is a direct memory access section. Address decoder 23 and address register 24 operate in predetermined cases, as will be described later.

When data is transferred between a terminal and a control channel using the direct memory access method, an area address of the transfer destination is planned, and the address is known in the microprocessor. The direct memory access control device also sends out the address of the data to be transferred over the address bus prior to the data being transferred. Conventionally, the number of address buses was as large as 20, but according to the present invention, the number can be reduced to, for example, 11.

Now, when data is transferred from the terminal 51 to the control channel 2A, the host computer (not shown)
is channel buffer 25 including control channel 2A.
Since the entire address of the channel buffer 25 is known in advance, a part of the address of the channel buffer 25 is applied to the address register 24 via the microprocessor 22. The address register 24 has a structure shown in detail in FIG. In FIG. 2, 35 is a write register;
6 and 37 indicate gates. Signals AB10-19 are storage addresses for channel buffer 25;
WC is a write command signal for the write register 35, RGS is a signal indicating that the circuit of the address register 24 has been accessed, RC is a signal for reading the contents stored in the write register 35, DM direct memory access operation This is a signal indicating that you are doing something. As mentioned above, channel buffer 25
Address bits AB10-19 are pre-latched in the write register 35 when the signals WC and RGS are present at the same time. Next, when the direct memory access unit 26 operates to transfer data, the upper bits 00 to 09 of the address bits are
The control channel is determined by the designation, and the address of the channel buffer previously designated within the control channel is determined by reading the write register 35, so the data at the address is read and transfer is started. At this time, in FIG. 2, the signal DM is applied for a direct memory access operation and the gate 37 is opened, so the address bits in the write register 34 are output as AB10-19.

Next, a case will be described in which data is transferred from the control channel 2A to the terminal 51. control channel 2
The data prepared in advance in the channel buffer 25 of A is transferred under the control of the direct memory access section 26. At that time, the microprocessor 22 applies the upper 10 bits of the address to the terminal to the address decoder 23, and the lower
The 10 bits are transferred to the terminal control board 41 using 10 predetermined addresses. The address decoder 23 decodes the applied address and transfers it to a predetermined terminal control board 41. The address decoder 23 decodes the applied address and applies a signal to the address bus corresponding to a predetermined terminal control board 41. It is preferable to associate a specific address bus with a specific terminal control board. Therefore, knowing that the terminal control board 41 specified by the upper bit has been designated, the internal microprocessor (not shown) can designate the terminal by the lower address. Therefore, the direct memory access unit 26 in the control channel 2A can transfer the data in the channel buffer 25 to the terminal 51.

FIG. 3 is a diagram showing a specific configuration example of the address decoder 23. As shown in FIG. In FIG. 3, 38 is a setting circuit for the lower address bits, 39 is a comparison circuit, and TMS is a decode signal indicating that the terminal control board has been accessed. Address setting circuit 3
For example, the upper 10 bits mentioned above are set in advance for 8. During data transfer, when the address for accessing the terminal is determined, the higher 10 bits are applied to terminals AB00-09 in Figure 3, so the comparator circuit 3
9, the terminal control board is identified by the output signal TMS when they match. The lower bits of the address then allow a given terminal to access it.

[Effect of the invention] According to the present invention, if the conventional address buses were 2n for each system, the number of address buses would be reduced by half, or
By adding one wire to each half, that is, n+1 wires each, the number can be reduced by 2 (n-1) in both systems. In this way, according to the invention, the number of connection buses between the control channel, the terminal channel and the terminal control board can be greatly reduced,
The configuration of the terminal control board is simplified. For example, the number of driver/receiver/address parity circuits for the connection bus can be reduced.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of an embodiment of the present invention, Figure 2 is a diagram showing the configuration of an embodiment of the present invention.
3 is a diagram showing a specific configuration of the address register and address decoder in FIG. 1, and FIG. 4 is a diagram showing the configuration of a conventional terminal control device. 1A, 1B...Host system bus, 2A, 2
B... Control channel, 23... Address decoder, 24... Address register, 25... Channel buffer, 41-44... Terminal control board, 51
~5n...terminal.

Claims (1)

[Claims] 1. Data transfer between a plurality of terminals 51...5n and a plurality of terminal control boards 41...44 connected to each other is controlled from two control channels 2A, 2B via a connection bus. , the control channel 2A, 2
In the terminal control method in which the transferred data is stored in the channel buffer 25 in B and transferred to the host side, when data is transferred from the plurality of terminals 51...5n to each control channel 2A, 2B, the above-mentioned data is stored in advance. A common address of a plurality of terminal control boards 41...44 is stored in the address register 24, and the common address is added to the unique address transferred from the plurality of terminal control boards 41...44 to create a channel buffer 25. Specify an area, store the transfer data in the specified area, and transmit the data from each control channel 2A, 2B to the plurality of terminals 5.
1...5n, the address decoder 23 decodes the address corresponding to each of the plurality of terminal control boards 41...44 in advance to designate the terminal control board 41, and then The plurality of terminals 51 each connected to the lower side of the terminal control boards 41...44
...5n by the connection bus.