JPH0470797A - Image signal composition device - Google Patents

Abstract

PURPOSE:To eliminate the time image deviation of a composite picture and to compose and display all image lines of an NTSC system image signal and the image signal of a computer. CONSTITUTION:The composition device is equipped with the frame memory 11 for storing one frame of the digitally converted NTSC system image signal, the frame memory 12 for storing one frame of the computer image signal, a memory control circuit 13 which controls the writing and reading of the frame memory 11, a memory control circuit 14 which controls the writing and reading of the frame memory 12, and a composing circuit 15 which composes one signal of the two image signals. Then the image signals are written at respective synchronous rates and then read out in synchronism with frequencies which are double as high as the vertical scanning frequencies and horizontal scanning frequency of the NTSC system. Consequently, a composite picture has no image deviation with time from the NTSC system image signal and all image lines of the NTSC system can be composed and displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image signal synthesis device, and more particularly to an image signal synthesis device that synthesizes an NTSC system image signal and a computer image signal.

[Conventional technology]

Generally, computer image signals differ from NTSC image signals in that they are non-interlaced and have different vertical scanning frequencies and horizontal scanning frequencies. For this reason, the NTS
When combining a C system image signal and a computer image signal, as shown in FIG.
A frame memory 21 is provided to store one frame of an SC image signal, and a memory control circuit 22 generates a write address W at an NTSC horizontal synchronization rate of 15-7 kHz and a vertical synchronization rate of 60 Hz to write an input image signal A.
1 is written to and read from the frame memory 21, a read address R is generated at the horizontal and vertical synchronization rate of the computer image signal B1 and read from the frame memory 21 as the image signal A2. In this way, the NTSC system input image signal A1 is subjected to non-interlace conversion to obtain an image signal A2 synchronized with the computer image signal B1, and then the image signals A2 and B1 are synthesized by the synthesis circuit 23 to produce a composite image signal C. is outputting.

[Problem to be solved by the invention]

In this conventional image signal synthesis device, the vertical scanning frequency of the computer image signal is usually lower than the vertical scanning frequency of 60 Hz of the NTSC image signal. For this reason, as shown in FIG. 4, the speed at which image lines are read out is slower than the speed at which they are written into the frame memory 21, so a time lag of one frame occurs before and after point d. When an NTSC image moves quickly, there is a problem in that the image shifts vertically with the d-point line as a boundary.

In addition, the number of effective image lines of the computer image signal is NT
When the number of effective image lines of the SC image signal is less than 483, there is also the problem that all the image lines of the NTSC image signal cannot be displayed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal synthesis device that can display all image lines of an NTSC image signal in a composite manner without causing temporal image shift in a composite screen for a fast-moving NTSC image signal. It's about doing.

[Means to solve the problem]

An image signal synthesis device of the present invention is an image signal synthesis device for synthesizing an NTSC image signal and a computer image signal, and includes a first memory for storing one frame of the NTSC image signal; a second memory that stores one frame of an image signal; a first memory control circuit that generates a write address and a read address for the first memory; a write address for the second memory; The second to generate the address
The memory control circuit includes a memory control circuit, and a synthesis circuit that synthesizes image signals read from the first and second memories. Further, the first and second memory control circuits may be configured to generate the read address in synchronization with twice the vertical scanning frequency and horizontal scanning frequency of the NTSC image signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a frame memory 11 that stores one frame of a digitally converted NTSC image signal, a frame memory 12 that stores one frame of a computer image signal, It includes a memory control circuit 13 that controls writing and reading of the frame memory 11, a memory control circuit 14 that controls writing and reading of the frame memory 12, and a combining circuit 15 that combines two image signals.

The NTSC image signal AI is written into the frame memory 1]- by the write address WA generated by the memory control circuit 13. In this case, the write address WA is generated at an NTSC horizontal and vertical synchronization rate. Further, the image signal written in the frame memory 11 is sent to the read address RA generated by the memory control circuit 13.
is read out as an image signal A2. In this case, the read address RA is generated at twice the horizontal scanning frequency during writing, so the read image signal A2 becomes a non-interlaced image signal.

On the other hand, the computer image signal B1 is transmitted to the memory control circuit 1.
The data is written into the frame memory 12 using the write address WB generated in step 4. In this case, write address WB
is generated at the horizontal and vertical synchronous rate of the computer image signal. Further, the image signal written in the frame memory 12 is read out as an image signal B2 by the read address RB generated by the memory control circuit 14. In this case, the read address RB has the same horizontal and vertical synchronization rate as the read address RA, i.e. 31.5kH1
and generated at 60Hz. Therefore, image signals A2 and B2 read from frame memories 11 and 12
are in sync with each other. Image signals A2 and B2 are combined by a combining circuit 15 and output as a combined signal C.

FIGS. 2(a) and 2(b) are diagrams showing the writing and reading speeds of image lines. Figure (a) shows the speed of writing and reading in the frame memory 11,
Since they are synchronized with each other, no overtaking phenomenon occurs. FIG. 4B shows the writing and reading speeds in the frame memory 12, and since the synchronization rates are different from each other, an overtaking phenomenon occurs (point e). Normally, the vertical scanning frequency of a computer image signal is lower than the vertical scanning frequency of 60 Hz of an NTSC image signal, so the speed of reading out an image line is faster than the speed of writing an image line into the frame memory 12, so point e An overtaking phenomenon occurs.

However, since computer images do not move much and do not move continuously, it is not noticeable even if the image shifts vertically with the line at point e as the boundary. Further, even if the number of effective image lines of the computer image signal is smaller than the number of effective image lines of the NTSC image signal, all the image lines of the NTSC image signal can be displayed.

〔Effect of the invention〕

As explained above, according to the present invention, a memory for storing one frame of an NTSC image signal and a computer image signal is provided, and the image signals are written at respective synchronous rates, and when read, the NTSC image signal is stored. By reading out in synchronization with twice the vertical scanning frequency and twice the horizontal scanning frequency, there is no temporal image shift in the composite screen even for fast-moving NTSC image signals, and effective images of computer image signals can be read out. Number of lines is NTS
Even if the number of effective image lines is smaller than the number of effective image lines of the C-system image signal, all NTSC-system image lines can be displayed in a composite manner.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
a) is a diagram showing the writing and reading speed of the frame memory 11 shown in FIG. 1, FIG. 2(b) is a diagram showing the writing and reading speed of the frame memory 12 shown in FIG. 1, Fig. 3 is a block diagram showing an example of a conventional image signal synthesis device, and Fig. 4 shows the frame memory 21 shown in Fig. 3.
FIG. 3 is a diagram showing the speed of writing and reading. 11. 12.21...Frame memory, 13
゜14.22...Memory control circuit, 15.23
...Composition circuit, A1 --- NTSC image signal, B1 --- Computer image signal, C
......Synthetic signal, WA, WB, W...Write address, RA, Ra. R...Read address.

Claims (1)

[Claims] 1. In an image signal synthesis device for synthesizing an NTSC image signal and a computer image signal, the NTSC
A first memory that stores one frame of a C-system image signal, a second memory that stores one frame of the computer image signal, and generates a write address and a read address for the first memory. a first memory control circuit; a second memory control circuit that generates a write address and a read address for the second memory; and a synthesis circuit that synthesizes image signals read from the first and second memories. An image signal synthesis device comprising: 2. The first and second memory control circuits are connected to the NT
2. The image signal synthesizing device according to claim 1, wherein the read address is generated in synchronization with twice the vertical scanning frequency and twice the horizontal scanning frequency of an SC type image signal.