JPH0470819A - Active matrix circuit and its manufacture - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an active matrix circuit such as a liquid crystal display (LCD) or an electroluminescence (EL) display using thin film transistors, and a method for manufacturing the same.

[Conventional technology]

FIGS. 5A and 5B show examples of thin film transistors according to the prior art. This thin film transistor is used in an active matrix circuit as shown in FIG. 4, and the like.

FIG. 4 schematically shows the planar structure of an active matrix substrate. Gate lines G1, G2,
G3, . . . run, and source lines S1, S2, S3, . Drain pads D11D12...D21.corresponding to each intersection.
D22...D31, D32... are arranged.

These drain pads form, for example, drive electrodes of a liquid crystal cell. Source line S corresponding to each train pad
t (i=1.2.3...) and gate line Gj (j
=1.2.3...), an insulated gate field effect transistor Tij is arranged between the drain pad Dij and the source line Si according to the signal of the gate line Gj.
to be applied.

These insulated gate field effect transistors T11T12
...T21, T22...T31, T32... are,
It is formed of a thin film transistor using amorphous silicon as shown in FIGS. 5(A) and 5(B).

5(A) is a plan view showing a pattern of a part of the area in FIG. 4, and FIG. 5(B) is a line VB in FIG. 5(A).
- It is a sectional view along VB.

A conventional method for manufacturing a thin film transistor will be described with reference to FIG. 5(B).

A conductive film is formed on a glass substrate 1, and a gate electrode 2 is patterned. On top of that, S iN x , S iOx
A gate insulating film 3 and a two-layer amorphous silicon (a-3i) semiconductor layer 4 having high resistivity and low resistivity are patterned into an island shape. Further, an electrode metal layer is formed, a zero-order transparent conductive film is formed for patterning the source/drain electrodes 5.6, and the train pad 7 is patterned. Finally, the upper part (low resistivity layer) of the semiconductor layer 4 is etched to form a channel.

[Problem to be solved by the invention]

However, when such a thin film transistor is made into an active matrix as shown in FIG. 4, it has the following problems.

During the manufacture of thin film transistors, if a defect such as a source-drain short circuit or a source-gate short circuit occurs in the transistor Tij, the pixel driven by the transistor will be either always ON or always OFF, resulting in a point defect6.
, t, for example, the gate line G1 shown in FIG.
If there is a short circuit between each line at the intersection A of the source line S2 and the source line S2, a line defect occurs. Furthermore, if the gate line G1 is disconnected, the gate signal will not be transmitted to the gate lines after the disconnection, resulting in a line defect.

An object of the present invention is to provide an active matrix circuit of thin film transistors that does not cause point defects or line defects even if a transistor defect, a short circuit between a source line and a gate line, or a disconnection of a gate line occurs, and a method for manufacturing the same. It is.

[Means to solve the problem]

The present invention will be described in detail with reference to FIG.

FIG. 1 shows a conceptual equivalent circuit diagram of a portion of one row in the horizontal direction of the active matrix of the present invention.

In Figure 1, G10 is the gate line, 810.31
1 are source lines, T2O and T41 are insulated gate field effect transistors, and Dl, D2, and D3 are transparent transistors that drive liquid crystal elements or EL elements, respectively.
Drain pads 10.11.12.13 & are switches that connect adjacent drain pads.

That is, as in the equivalent circuit shown in FIG. 1, a switch circuit is added to form an active matrix circuit so that each drain pad can serve as a bypass path for the gate line GIO.

[Effect]

Here, if a defect occurs in the transistor T40 during manufacturing, the connection between the drain of the transistor T40 and the train pad D2 is physically cut, and the switch 12 is
．． 13 is made conductive. As a result, the drain pad D2 is supplied with a driving voltage from the adjacent drain pad D3, so no point defects occur.

Next, when the intersection A of the gate line GIO and the source line S11 is short-circuited, the left and right sides of the intersection A of the gate line GIO are cut off, and the switches 12 and 13 are made conductive.
Furthermore, the drains and gates of transistors T40 and 741 are shorted. Then, the gate line GIO is the transistor T40-drain pad D2-switch 1
It is bypassed by the circuit of 2-switch 13-drain pad D3-transistor T41. As a result, D2 and D3
The point defect of the pixel at will remain, or the line defect due to the short circuit at the intersection A, which has a larger defect, will be repaired. Note that it is preferable to disconnect between the source electrodes of transistors T40 and T41 and the source line (sections α and β in FIG. 2).

Furthermore, if the gate line GIO is disconnected at point B, the line defect after the disconnection point B can be repaired by taking the same measures as the short-circuiting method at intersection A described above.

In an actual thin film transistor, these switches 10.1
1, 12, and 13 are all correction electrodes formed facing each other with a gate insulating film in between so as to straddle adjacent drain pads, and have a structure in which they are insulated from the drain pads at the time of formation. be. These switches 10.11
．． In order to close 12.13, the gate insulating film may be destroyed by irradiation with a high-density energy beam such as a laser beam, and the opposing drain pad and correction electrode may be short-circuited.

〔Example〕

FIGS. 2 and 3 show the planar structure and cross-sectional structure of an embodiment of the active matrix of a thin film transistor according to the present invention. Note that the functional parts equivalent to those in the conceptual equivalent circuit diagram of FIG. 1 are the same. Reference numbers have been given.

A conductive layer is formed on the substrate, and a gate line GIO1Gll is formed.
As shown in the figure, a pattern of correction electrodes [i20.21 is added and patterned to the pattern of , and correction rjhlj is formed at the same time as the gate line. As shown in FIG. 3, a gate insulator 113 and a semiconductor film are deposited on top of this, and as shown in FIG. Pattern 1130-37. Of course, it goes without saying that in an actual active matrix, similar structures are formed in areas other than those shown in the drawings.The gate insulating film is left on the entire surface, and the source line 310,
Sll, drain electrode, drain pad DI-D2,
Form D3. The correction electrode 20 is arranged such that its opposite end portions face the train pads D1 and D2 with the gate insulating film interposed therebetween. Similarly, the correction t[i21 is arranged so as to face the drain pads D2 and D3 at both end portions with the gate insulating film interposed therebetween. Therefore, when manufacturing thin film transistors, the correction electrodes 20 and 21 are the drain pads D.
1, D2, and D3. That is, switches 10.11.12.13 in the conceptual equivalent circuit diagram of FIG.
is equivalent to each being in an open state.

If a defect occurs in the transistor T40 during manufacturing, a YAG laser beam is irradiated to the connection between the drain of the transistor T40 and the train pad D2 to cut them (for example, using a HOYA LR202 laser, a pulse voltage 640V, using an attenuation filter of 5% to 46% transmission), and further irradiates the gate insulating film in contact with both ends of the correction electrode 21 with a laser beam to destroy the insulating film (for example, HO
Using a YA LR202 laser with a pulse voltage of 640 cm and an attenuation filter of 46% to 100% transmission), the correction electrode 21 and the drain pads D2 and D3 are made conductive. As a result, the drain pad D2 is supplied with a driving voltage from the adjacent drain pad D3, so no point defects occur.

Next, if the intersection A of the gate line GIO and the source line S11 is short-circuited, the portions marked with X on the left and right of the intersection A of the gate line GIO are cut, and the gate insulating film in contact with both ends of the correction electrode 21 is cut. irradiate the laser beam to destroy the insulating film and correct @&21 and drain pad D2=, D3
conduction between.

Further, the source electrodes of transistors T40 and 741 are cut from the source line at portions α and β in FIG.

Further, the drains and gates of transistors T40 and T41 are shorted. Then the gate line GIO becomes transistor T40-drain pad p2-correction $pole 2
It is bypassed by the circuit of 1-drain pad D3-transistor T41. As a result, the pixel point defects at D2 and D3 remain, or the line defect due to the short circuit at the intersection A, which has a larger defect, is relieved.

Furthermore, if the gate line GIO is disconnected at point B, the line defect after the disconnection Bl'1 can be repaired by taking measures similar to the short-circuiting method at the intersection A described above.

Next, a method for manufacturing a thin film transistor according to an embodiment of the present invention will be described with reference to FIG. 3, which is a cross-sectional view taken along the line III-III in FIG. 2.

2000~ metal films such as Mo and Cr on glass substrate 1
3,000 people are formed, and the correction electrode 21 and gate electrode 42 (G
IO). On top of that, SiN, Si
A gate insulating film 3 of 3 × × 000 to 6000 such as
Semiconductors 1130 to 37 are patterned into islands at the intersections. These semiconductor films are preferably formed by laminating a high-resistivity a-3i film and a low-resistivity a-3t film. On top of this, a t-pole metal layer such as MOlAR is formed with a thickness of 3000 to 8000.
Also, a source/drain t-pole 5.6 is formed and patterned.

Then, 500 to 2000 drain pads D1, D2, etc., which are transparent electrodes, are formed. After I7&, the low resistivity a-3ig on the channel portion of the transistors 1 to 1 is etched, leaving the high resistivity a-3ill channel to form a channel.

Although the present invention has been described above in accordance with the embodiments, the present invention is not limited to these embodiments; for example, various changes,
It will be obvious to those skilled in the art that improvements, combinations, etc. are possible.

〔Effect of the invention〕

As described above, according to the present invention, even if a pixel point defect due to a transistor defect or a line defect due to a short circuit at the intersection of the gate line and the source line or a disconnection of the gate line occurs during manufacturing, the correction electrode By using the train pad to form a bypass circuit, point defects and line defects can be relieved.

Since this correction tri can be formed using the same material and the same photomask in the same process as the gate line formation, it can be formed without adding any special process or increasing the number of manufacturing steps.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram showing the concept of the present invention, and FIG. 2 is an equivalent circuit diagram showing the concept of the present invention.
3 is a plan view showing an embodiment of the present invention, FIG. 3 is a sectional view showing an embodiment of the present invention, FIG. 4 is a diagram schematically showing an active matrix circuit, and FIGS. 5(A) and (B) 1A and 1B are a partial plan view and a cross-sectional view of a conventional active matrix thin film transistor. 2 Gate electrode 3 Gate insulating film 4.30-37 Semiconductor film 5 Source electrode 6 Drain electrode Tll-T i 3, T21-T23, T31-T33
, T2O, T41 insulated gate field effect transistors D1-D3, D11-D13, D21-23, D31-
D33 Drain pads 01 to G3, GIO1Gll Gate line S1 to S3.5IO1Sll Source line 20.21 In the corrected electrode diagram, 1 Board patent applicant Stanley Electric Co., Ltd. Agent
Patent Attorney Keishibu Takahashi Figure 1 Figure 2 Active matrix according to the prior art Figure 5 Display of the case 1990 Patent Application No. 185046 2 Title of invention Active matrix circuit and its manufacturing method Case for amending the same Relationship address name

Claims (2)

[Claims] (1) In an active matrix in which a plurality of thin film transistors formed by laminating a gate electrode layer, a gate insulating film, a channel layer, and a source/drain electrode layer on a substrate and a plurality of electrode pads driven by the thin film transistors are arranged. . The active matrix further includes a correction electrode formed on the substrate so as to straddle between two adjacent electrode pads with the gate insulating film interposed therebetween. (2) A method for manufacturing an active matrix having a plurality of thin film transistors formed by stacking a gate electrode layer, a gate insulating film, a channel layer, a source/drain electrode layer, and an electrode pad on a substrate, the method comprising: a gate on the substrate; A method for manufacturing an active matrix, including the step of simultaneously forming a correction electrode that straddles between two adjacent electrode pads with the gate insulating film in between when forming the electrodes.