JPH0470939A - Cassette judging device for electronic equipment - Google Patents

Abstract

PURPOSE:To inhibit the use of an improper cassette which is produced by copying, etc., by judging an improper cassette when a proper code is inputted before a prescribed count time. CONSTITUTION:The cassette judging means 11 - 18 count the time at output of a clear signal, the inverse of CONTROL and judge that a cassette 3 loaded to a family computer main body part 1A is proper when a proper code, the inverse of OE is inputted from an output circuit 16 at a prescribed count time. When the code, the inverse of OE is inputted before the prescribed count time or the code, the inverse of OE is not inputted even after the prescribed time, an improper cassette 3 is judged. Thus only the proper cassette 3 is usable and an improper cassette is judges as a copy cassette for example. Then the use of the improper cassette 3 is electrically inhibited.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention distinguishes whether a cassette installed in an electronic device such as a game machine is an original cassette or a copied cassette, and The present invention relates to a cassette discriminating device that electrically prohibits the use of a cassette when it is determined that the cassette is a cassette that has been tampered with.

(Prior Art) Conventionally, for example, in a game machine where a main cassette and a sub cassette are combined and attached to the main body and connected to a TV to enjoy games, a read only memory (ROM) etc. built into the cassette is used. The data, programs, etc. stored in the memory can be copied relatively easily using a memory copy device. As a result, original game software created by various companies over a long period of time was copied, and a large number of copy cassettes containing the software were copied, causing enormous losses to the original manufacturers.

(Problems to be Solved by the Invention) Since it is possible to easily make a copy cassette using the conventional cassette described above, in the present invention, the cassette attached to the main body is a copy cassette in which original software is copied. The technical problem to be solved is to identify such cases and make the copy cassette unusable so that the original manufacturer does not suffer any disadvantage.

(Means for Solving the Problem) The technical means for solving the above problem is to read various data, programs, and A cassette discrimination device is provided that determines whether a cassette having a memory storing a unique code, etc. is a proper cassette, and when it is determined that it is not a proper cassette, electrically disables the use of the cassette. , a timer circuit that inputs and counts a clock signal of a predetermined frequency and outputs a time limit signal when a predetermined count value is reached;
a time count clear circuit that clears the count value of the timer circuit every time an external clear signal is input;
an output circuit that outputs the unique code when a read request signal from the control circuit is input while the time limit signal is not output; and an output circuit that outputs the clear signal at time intervals according to a cassette discrimination program of the control circuit. a clear signal output means for outputting a clear signal; and a cassette attached to the main body that counts time from the time when the clear signal is output, and when the unique code from the output circuit is input at a predetermined count time. On the other hand, if the unique code is input before the predetermined count time is reached, or if the unique code is not input even after the predetermined count time has passed, the cassette is determined to be a proper cassette. cassette discriminating means for discriminating that the cassette is not a valid cassette.

(Function) According to the cassette discriminating device in the electronic device having the above configuration, the cassette discriminating means counts time from the time when the clear signal is output, and the unique code from the output circuit is detected at a predetermined count time. When input, the cassette installed in the main body is determined to be a proper cassette, but when the unique code is input before the predetermined count time is reached, or even if the predetermined count time is exceeded. If the unique code is not input, it is determined that the cassette is not a proper cassette. Therefore, only appropriate cassettes can be used, and it is possible to determine that an inappropriate cassette is, for example, a copica set, and electrically prohibit the use of that cassette.

(Example) Next, an example of the present invention will be described with reference to the drawings.

Figure 1 shows a double cassette type Famicom for gaming.
The main cassette 3 with the sub-cassette 2 attached thereto is used by inserting it into the cassette insertion slot 4 of the Famicom main body IA. Furthermore, the Famicom 1 has a microcomputer (control circuit) CPU,
It has a built-in clock circuit, power supply circuit, etc. The main cassette 3 stores the main program for the game, and the sub cassette 2 stores the sub program and a unique code (confirmation code) to be described later. By replacing it with , you can, for example, change part of the game's story.

FIG. 2 shows a determination circuit for communicating with the microcomputer CPU built in the Famicom main body IA to determine whether the double cassette is a proper cassette. Note that this discrimination circuit is built in the sub-cassette 2.

In the discrimination circuit of FIG. 2, the flip-flop 11.1
2, 13.14 constitutes a timer circuit (counter circuit), and when a predetermined number of clock signals (CLK) from the clock circuit built in the Famicom 1 are input,
Of the flip-flops 15 and 16, a logic H time limit signal is output from the output terminal Q of the flip-flop 16. On the other hand, flip-flop 1
1. 12, 13, 14, 15, and 16 are cleared by a logical clear signal (control signal) CONTROL from the microcomputer CPU built into the Famicom I. Among these, flip-flops 11, 12, 13, and 14 have logic H at their clear terminals.
The count value of the timer circuit is cleared when the signal is applied, and the flip-flop 15.1
6 is designed to be reset when a logic signal is applied to the clear terminal. Therefore, the time count clear circuit is configured such that a clear signal is applied to the clear terminals of the flip-flops 11, 12, 13, and 14 via the NOT gate 17. flip flop 1
The two-man power OR gate 18 inputs the output signal (OUT) from the output terminal Q of the Famicom I and the unique code read request signal (OE) from the microcomputer CPU built in the Famicom I. , a logic signal is output when both the unique code read request signal (OE) are logic logic, and when the output signal (ROM OE) of the two-man OR gate 1B is logic logic, the sub cassette 2 The unique code can be read from the built-in ROM of the Famicom 1, and the unique code can be transmitted via the main cassette 3 to the microcomputer CPU built in the Famicom I.

FIG. 3 shows a timing chart of the discrimination circuit provided in the sub-cassette 2.

When the power is turned on to the Famicom 1 after inserting the main cassette 3 with the sub cassette 2 inserted into the cassette insertion slot 4, a square wave clock signal (CLK) as shown in FIG. 3(A) is generated. is output from the Famicom 1 clock circuit. This clock signal (CLK) is input to the flip-flop 11, and thereafter the flip-flop 11
, 12°13.14. When a predetermined number of clock signals (CLK) are input, a logic H signal is output from the output terminal Q of the flip-flop 16. However, the logic clear signal (CONTR) from the microcomputer CPU as shown in FIG.
OL) is output at the time interval T1 and is cleared before the count value of the timer circuit reaches a predetermined value, a logic H signal will not be output from the output terminal Q of the flip-flop 16. However, as shown in area P in FIG. 3(B), the clear signal (CONTROL) is
If no input is received even after passing I, the output signal of the flip-flop 16 (O
UT) is inverted to logic H.

FIG. 3(D) shows the unique code read request signal (OE) from the microcomputer CPU built into the Famicom 1.
) is a time chart. FIG. 3(E) shows a 2-channel system for making it possible to read the unique code from the built-in ROM of the sub-cassette 2 and transmitting the unique code to the microcomputer CPU built in the Famicom 1 via the main cassette 3. Output signal of human-powered OR gate 18 (R
OMOE) is a time chart.

As shown in FIG. 3(C), FIG. 3(D), and FIG. 3(E), the timing corresponding to the Q area of FIG. 3(C), that is, the output signal (OLJT) of the flip-flop 16 is When in the logic H state, a unique code read request signal (OE
) is output (R4), the output signal (ROMOE) of the two-man OR gate 18 is not logical. That is, the two-man OR gate 18 prevents the built-in ROM of the sub-cassette 2 from reading the unique code.

On the other hand, when the output signal (OUT) of the flip-flop 16 is in a logical state, the program read request signal (OE) is output from the microcomputer CPU (R1, R2,
R3, R5), the output signal (ROM OE) of the two-man OR gate 18 becomes 81.82.83. Since it becomes logical in S4, 81. S2. At each timing of S3.84, the unique code in the built-in ROM of the sub-cassette 2 is enabled to be read.

Next, cassette discrimination control through communication between the microcomputer CPU and the discrimination circuit will be explained with reference to the flowchart shown in FIG.

The main cassette 3 is set in the family computer 1 with the sub cassette 2 inserted into the main cassette 3 as the cassette to be discriminated. Thereafter, the power of the Famicom I is turned on, and with the microcomputer CPU initialized, the clear signal is sent from the microcomputer CPU to the discrimination circuit (protection IC) as shown in step S1. In step S2, a request signal (OE) for reading the unique code (confirmation code) of the ROM built into the sub-cassette 2 is output. It is determined in step S3 whether or not the unique code has been read out, and if the unique code is not read out even after a predetermined time has elapsed, it is determined that the sub cassette 2 is not connected as shown in step S4. . On the other hand, if a unique code is read out, it is determined in step S5 whether or not the code is compatible with the game of that cassette. If it is determined in step S5 that the unique code does not match the game content, use of the sub-cassette 2 is disabled as shown in step S6. On the other hand, if it is determined that the unique code is suitable for the game, the time counter of the microcomputer CPU is set to zero in step S7. In the next step S8, the clear signal is sent to the discrimination circuit (protection IC). Thereafter, in step S9, a request signal (
OE) is output. In step 810, a check is made to see if a unique code has been entered. As a result of the check, if a unique code is input, step 81
1, the time elapsed since the clear signal was output is checked.

If the unique code is input at the predetermined time, it is determined that the cassettes (main cassette 3 and sub cassette 2) inserted into the Famicom 1 are correct, and the cassettes are inserted as shown in step 812. Proceed through the game.

On the other hand, as a result of the check in step 810, if the unique code is not input, the count value of the time counter is incremented by 1 as shown in step 813, and then step S
At step 14, it is determined whether the count value of the time counter has reached the time limit. As a result of that judgment,
If the time limit has not yet been reached, proceed to step S.
On the other hand, if the time limit has been reached or exceeded, as shown in step 815, it is determined that the cassette inserted into the Famicom I is not appropriate, and is, for example, a copied cassette, and the Famicom I is inserted. An error message is displayed on the display of the cassette, and use of the cassette is electrically prohibited.

(Effects of the Invention) As described above, according to the present invention, the time from when the clear signal is output from the control circuit is counted, and when the unique code of the cassette is input at the predetermined count time,
While the cassette installed in the main body of the electronic device is determined to be a proper cassette, if the unique code is input before the predetermined count time is reached, or even after the predetermined count time is exceeded, the unique code is not recognized. If no input is made, it can be determined that the above cassette is not a proper cassette, so only proper cassettes can be used, and incorrect cassettes made by copying etc. cannot be electrically used. I can do it. Therefore, there is an effect that the original manufacturer of the cassette can be prevented from suffering a loss.

[Brief explanation of the drawing]

The drawings relate to an embodiment, and FIG. 1 is a perspective view showing how the main cassette and sub cassette are inserted into the Famicom, FIG. 2 is a circuit diagram of a discrimination circuit, and FIG. 3 is a waveform showing a timing chart of the discrimination circuit. FIG. 4 is a flowchart of cassette discrimination control. l: Famicom IA: Famicom main unit 2: Sub cassette 3: Main cassette 4: Cassette insertion slot 11.12, 13, 14, 15, 16: Flip-flop 17: Not gate 18 Nior gate

Claims (1)

[Claims] Whether a cassette that is attached to the main body of an electronic device and has a memory that stores various data, programs, unique codes, etc. read out by a control circuit built into the electronic device is an appropriate cassette. The cassette discriminating device electrically disables the use of the cassette when it is determined that the cassette is not a proper cassette, and counts by inputting a clock signal of a predetermined frequency.
A timer circuit that outputs a time limit signal when a predetermined count value is reached, a time count clear circuit that clears the count value of the timer circuit every time an external clear signal is input, and the time limit signal is output. an output circuit that outputs the unique code when a read request signal from the control circuit is input in a state where the read request signal is not read, and a clear signal output that outputs the clear signal at time intervals according to the cassette discrimination program of the control circuit. and a means for counting time from the time when the clear signal is output, and when the unique code from the output circuit is input at a predetermined count time, the cassette installed in the main body is determined to be a proper cassette. On the other hand, if the unique code is input before reaching the predetermined count time, or if the unique code is not input even after the predetermined count time, the cassette is determined to be not a proper cassette. 1. A cassette discriminating device for an electronic device, comprising a cassette discriminating means for discriminating.