JPH0471274A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect an inner circuit from an overinput by a method wherein an inner terminal is connected both to a bipolar type semiconductor and an input clamping MOS type semiconductor element. CONSTITUTION:A MOS type transistor 8 is composed of an n<+> diffused region formed in a P well to be a P<+> diffused region and a polysilicon made gate G. Next, when an input terminal IN is impressed with a negative high voltage, the gate G of an input clampling MOS type transistor 8 is impressed with the negative voltage so that a source and a drain may be made conductive to turn the MOS type transistor 8 in the on-state. By this MOS type transistor 8 turned in the on-state, the connecting terminal 5 in an inner circuit A is clamped on the ground potential at a reference potential point 9 not to impress the inner circuit A with the negative high voltage. Furthermore, when the input terminal IN is impressed with an electrostatic high voltage, a bipolar type transistor 1 is turned on not to impress the inner circuit A with the high voltage. Through these procedures, the erroneous operation in the inner circuit A can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to semiconductor integrated circuits, and in particular to countermeasures against high negative voltages.

(Prior Art) FIG. 4 is a circuit diagram of a conventional semiconductor integrated circuit, and FIG. 5 shows a schematic pattern of the same circuit on a chip. In FIGS. 4 and 5, 1 is a bipolar transistor whose collector is connected to the input terminal IN via a resistor 2, and whose emitter and base are connected to a reference potential point 9, which is a ground potential, through a contact portion C2C. It is. Further, the collector of the bipolar transistor 1 is connected via a resistor 3 to a connection terminal 5 of an internal circuit A via a contact portion C. The resistor 2.3 is formed by n10 diffusion regions in the P well, and the internal circuit A has two M transistors connected to the reference potential point 9 and the power supply potential point 10.
The bipolar transistor 1 is composed of an O5 type transistor 6゜7, while the bipolar type transistor 1 has an
The wells constitute a lateral npn) transistor.

Note that this semiconductor integrated circuit is formed of an n-type substrate.

In the semiconductor integrated circuit configured as described above, when a high electrostatic voltage is applied to the input terminal IN, the breakdown of the pn junction of the bipolar transistor 1 causes a base current to flow, and the collector There is a low impedance between the emitter and the internal circuit A, so that no high voltage is applied to the internal circuit A.

(Problem to be Solved by the Invention) However, in the conventional semiconductor integrated circuit described above, when a negative high voltage is applied to the input terminal IN, the voltage between the collector of the bipolar transistor 1 and the diffusion region and the P-well increases. A forward voltage is applied to the pn junction of the pn junction, and minority carriers are injected into the p-well. There is a problem in that the internal circuit A malfunctions due to the diffusion of minority carriers. Further, when the internal circuit A is a C-MOS integrated circuit, there is a problem that it causes latch-up in addition to malfunction.

The present invention has been made in view of the above, and an object of the present invention is to prevent the internal circuit from malfunctioning in response to negative high voltage.

(Means for Solving the Problems) In order to achieve the above object, the means taken by the present invention are as follows:
Bipolar type semiconductor and MO for manual clamping on the input terminal
It is designed to be connected to an 8-type semiconductor element.

Specifically, a bipolar semiconductor element has a collector connected to an input terminal to which an input signal is applied, an emitter and a base connected to a reference potential point, and a gate connected to the input terminal via a resistor. The structure includes an MO8 type semiconductor element whose drain is connected to the reference potential point via a resistor, and whose source is connected to the reference potential point through a resistor, and whose drain is connected to an internal circuit.

(Function) With the above configuration, in the present invention, when a negative high voltage is applied to the input terminal, the negative voltage is applied to the MO6O6 type semiconductor element, and the MO3 type semiconductor element is turned on. By turning on this MO8 type semiconductor element, the input side of the internal circuit is clamped to the reference potential. As a result, a negative high voltage is not applied to the internal circuit, and malfunction of the internal circuit is prevented.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit of the present invention,
Figure 2 shows the schematic pattern on the chip of the same circuit;
The figure shows a schematic cross-sectional view of the chip. This figure 1~
In FIG. 3, IN is an input terminal, 1 is a bipolar transistor which is a semiconductor element configured as a lateral npn) transistor in which an n+ diffusion region and a P well are formed on an n substrate; 2.3. 4 is a resistor formed by an n+ diffusion region, and 8 is a MO which is a semiconductor element for input clamping.
The MOS transistor 8 is an S-type transistor.
The structure is such that an n0 diffusion region is formed in a P well, which is a P0 diffusion region, and a polysilicon gate G is provided. Further, 5 is a connection terminal to which an internal circuit A is connected, and the internal circuit A is connected to two MOS transistors 6 and 7 connected to a reference potential point 9 and a power supply potential point 10.
The reference potential point 9 is at ground potential.

The collector of the bipolar transistor 1 is connected to the input terminal IN via a resistor 2 through a contact portion C, and the emitter and base are connected to a reference potential point 9.

Further, the gate G of the MOS type transistor 8 is connected to the input terminal IN by the contact part C through a resistor 2.3, the drain is connected to the gate G by the contact part C through the resistor 4, and the source is connected to the above-mentioned Reference potential point 9
It is connected to the. Then, the MOS type transistor 8
The drain of is connected to the connection terminal 5 of the internal circuit A. Furthermore, the gate electrode G of the MOS transistor is
It is formed to be thicker than the gate electrode Gl of the MOS transistor 6.7 of the internal circuit A, so as to increase the withstand voltage.

Next, the operation of the semiconductor integrated circuit of this embodiment configured as described above will be described below.

First, when a negative high voltage is applied to the input terminal IN, a negative voltage is applied to the gate G of the input clamping MOS type transistor 8, so that the source and drain are electrically connected and the MO8 type transistor 8 turns on. This M.O.
By turning on the S-type transistor 8, the connection terminal 5 of the internal circuit A is clamped to the ground potential of the reference potential point 9, and a negative high voltage is not applied to the internal circuit A.

Furthermore, when an electrostatic high voltage is applied to the input terminal IN,
Bi-bord transistor 1 is not turned on and high voltage is not applied to internal circuit A.

(Effects of the Invention) As described above, the present invention connects a conventionally used bipolar semiconductor to an input terminal and connects a MOS semiconductor element for input clamping to the input terminal, thereby achieving a negative When a high voltage of Malfunctions of internal circuits can be reliably prevented.

Also, when the internal circuit is composed of a C-MOS integrated circuit,
Latch-up can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit of the present invention, FIG. 2 is a pattern diagram showing a schematic pattern on a chip of the same circuit, and FIG.
4 is a circuit diagram of a conventional semiconductor integrated circuit, and FIG. 5 is a pattern diagram showing a schematic pattern on the chip of the same circuit. 1...Bipolar type transistor 2, 3.4...Resistor 5...Connection terminal 8...MOS type transistor 9 for input clamp...
・Reference potential point IN...Input terminal A...Internal circuit 1...Bipolar type transistor 2, 3.4...Resistor 5...Connection terminal 8...MOS type transistor 9 for input clamping・・・
・Reference potential point IN... Input terminal A... Internal circuit [-] Figure C ~ Figure 2 Figure 4 Cause

Claims (1)

[Claims] (1) A bipolar semiconductor element whose collector is connected to an input terminal to which an input signal is applied, and whose emitter and base are connected to a reference potential point, a gate connected to the input terminal via a resistor, and a resistor connected to the gate. 1. A semiconductor integrated circuit comprising: a MOS semiconductor element having a drain and a source connected to the reference potential point via a MOS semiconductor element, and a MOS type semiconductor element having a drain connected to an internal circuit.