JPH047128B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses an electronic tuner, digitizes the tuning voltage applied to the electronic tuner, stores it in a non-volatile memory in correspondence with the channel number, and when selecting a channel, tunes voltage data from the non-volatile memory. The present invention relates to a channel selection device that performs channel selection by reading data.

Using an electronic tuner consisting of a voltage-controlled tuning circuit using variable capacitance diodes, the tuning voltage is encoded into a digital signal and stored in non-volatile memory in correspondence with each channel number. The tuning voltage data corresponding to the desired channel number is read out, the tuning voltage data is digital-to-analog converted (hereinafter abbreviated as DA conversion), and applied to the electronic tuner for tuning, as well as automatic fine tuning circuit. (hereinafter abbreviated as AFT circuit), or by installing a circuit such as a fine adjustment circuit,
The tuning voltage data is slightly changed by the control signals output from these circuits, and the tuning frequency of the electronic tuner is finely tuned.Fine tuning is performed by dealing with tuning frequency shifts due to oscillation frequency fluctuations of the electronic tuner's local oscillation circuit. Channel selection devices for this purpose have been well known. In such a tuning device, the change in the tuning frequency of the electronic tuner (hereinafter abbreviated as tuning voltage control sensitivity) with respect to a minute change in the tuning voltage, that is, a minute change in the tuning voltage, which is an analog quantity, differs depending on the receiving channel number. Since the deviation between channel numbers is several tens of times larger, AFT (Auto
If the tuning voltage data is changed by the same value for each channel number using the control signal from the fine tuning circuit or the fine tuning circuit, the step of slight change in the tuning frequency of the electronic tuner will be large between the selected channel numbers. different. If this change step is too large, it may not be possible to set the correct tuning point, or
If it is small, problems may arise such as it takes time to set the correct tuning point. Conventionally, the channels to be received are divided into channel groups based on the receiving frequency band or the tuning voltage control sensitivity value, and the amount of minute change in the tuning voltage data is adjusted according to the channel group. I dealt with it by making changes. However, there are still variations in the tuning voltage control feeling within the channel group, and control elements such as variable capacitance diodes in electronic tuners,
Due to variations in the parts used, etc., there is still a deviation of several times or more in the step of minute change in the tuning frequency caused by the control signal, and the above-mentioned problem has not been sufficiently improved.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a tuning device that can set tuning points accurately and with little variation in setting time even when there are variations between channel numbers or manufacturing variations of electronic tuners. It is about providing.

In order to achieve the above-mentioned purpose, the present invention calculates the difference between the tuning voltage data of the selected channel number and the channel number that is separated from the selected channel number by a substantially constant number of channels, and then calculates the difference based on this value.
The amount of miniaturization of the tuning voltage data by the control signal of the AFT circuit or fine adjustment circuit is varied and set. Hereinafter, the content of the present invention will be explained using the drawings. FIG. 1 is a tuning curve showing the relationship between the tuning voltage and the tuning frequency of an electronic tuner having a tuning circuit using a variable capacitance diode as a voltage control element. In FIG. 1, the horizontal axis shows the tuning voltage, and the vertical axis shows the tuning frequency. Generally, television, radio, etc. signals are spaced apart by approximately a constant frequency interval "K". The signals arranged at frequency intervals of K have channel numbers n-3, n-2, n.
Channel numbers are set consecutively such as -1, n, n+1, n+2, etc. In order to tune and receive each channel signal, the electronic tuner has a tuning voltage.
V _T (n-3), V _T (n-2), V _T (n-1), V _T
(n), V _T (n+1), and V _T (n+2) are applied. Tuning voltage V _T of selected channel number “n”
(n) and, for example, the next channel number (n
-1, n+1) tuning voltage V _T (n-1), V _T (n+
The difference from 1), dV _T (n-1), dV _T (n+1), is
This is approximately equivalent to the change in the tuning voltage required to change the tuning frequency by the frequency interval K at the tuning point of channel number "n". If the tuning voltage of this difference is divided into N and standardized, and then changed by dV _T (n-1)/N or dV _T (n+1)/N according to the control signal from the AFT circuit or fine tuning circuit, the tuning frequency can also be adjusted. It changes in approximately 1/N steps of the frequency interval K. By determining the difference in tuning voltage at each channel number and performing a similar operation, it is possible to significantly reduce the deviation between channel numbers in the tuning frequency change step caused by the fine adjustment control signal. In the tuning device using the present invention, the tuning voltage of this difference is digitally encoded and stored in a nonvolatile memory, and the tuning voltage data of these channel numbers is read out and a subtraction operation is performed. This makes it easier to stop. By further dividing this calculation result into N, the amount of slight change in the tuning voltage data due to the fine adjustment control signal can be immediately determined, and even if there are variations in tuning voltage control sensitivity not only between channel numbers but also during the manufacturing of the electronic tuner. ,
This is to make the steps of minute changes in the tuning frequency caused by the fine adjustment control signal approximately the same.

The present invention will be explained in detail below using examples.
FIG. 2 explains the fine tuning operation by the channel selection device of the present invention. 1 is an electronic tuner, 2 is D-
A converter, 3 is a non-volatile memory, 4 is a tuning switch, 5 is a tuning control circuit, 6 is a data selector, 7
1 is a first reversible counter, 8 is a first shift register, 9 is a subtraction operation circuit, 10 is a second shift register, 11 is a division circuit, 12 is a fine count signal generation circuit, 13 is a clock pulse generation circuit,
14 is a second counter, 15 is a fine adjustment control circuit,
16 is a fine adjustment key. First, the channel selection operation will be explained with reference to FIG. Channel selection switch 4
When a channel number is input, tuning voltage data corresponding to the channel number is first read from the nonvolatile memory 3 by a control signal from the channel selection control circuit 5 and input to the data selector 6. Based on a signal from the tuning control circuit 5 that is input to the data selector 6, the read tuning voltage data is input to the first shift register.

Next, according to the control signal of the tuning control circuit 5, the tuning voltage data of the selected channel number and a certain channel (in this embodiment, a tuning number that is one channel apart) are read out from the nonvolatile memory 3, and the data selector 6
Enter. At the same time as this second tuning voltage data reading, the tuning control circuit 5 generates a shift signal for the first shift register 8, outputs the tuning voltage data of the tuning channel number, and outputs the tuning voltage data to the data selector 6.
The data selector 6 inputs the tuning voltage data of the selected channel number outputted from the first shift register 8 to the first shift register, and also inputs the tuning voltage data of the selected channel number one channel away from the first shift register 8. Tuning voltage data is output to the subtraction calculation circuit 9. The subtraction operation circuit 9 selects and distinguishes between the subtracted signal and the subtraction signal of both tuning voltage data using the control signal from the channel selection control circuit 5, performs a subtraction operation, and inputs the subtraction result to the second shift register 10. Thereafter, using a control signal from the tuning control circuit 5, the tuning voltage data of the tuning channel number stored in the first shift register 8 is preset as a counter value in the first reversible counter 7, and based on this counter value, D- The A converter 2 performs pulse width modulation, and the integrating circuit converts the voltage into an analog tuning voltage, which is applied to the electronic tuner 1 to tune to the signal of the selected channel number and perform tuning. In electronic tuners, etc., there is a limit to the variable range of the variable capacitance diode, which is the control element, and even if the channel numbers are continuous, the signal frequency bands are different, so all channel numbers are different, as shown in Figure 1. It is rare for the tuning voltage to change continuously. For example, for television signals in Japan, the receiving frequency band is channel number 1~3,4~
They are divided into three channel groups, 12, 13 to 62, and the tuning voltage changes are not continuous for channel numbers 3 and 4 and channel numbers 12 and 13. Also, regardless of whether the channel number to be compared is above or below the selected channel number, there is no tuning voltage data for the channel number to be compared for either the highest or lowest channel number of this receivable channel group. become. Therefore, depending on the channel number you select,
The channel selection control circuit 5 memorizes whether the channel number to be compared should be selected as an upper (larger) channel separated by a certain channel number or a lower (smaller) channel separated by a certain channel number. Sometimes,
The tuning voltage data is read out by determining whether the channel number is above or below to be compared according to the channel number. As a result, the subtraction calculation circuit 9 determines whether the channel number to be compared from the channel selection control circuit 5 is above the selected channel number or not. , the tuning voltage data of the selected channel number and the tuning voltage of the channel number a certain channel number apart are selected and distinguished as the augend and the subtrahend, and are always positive or negative. The tuning voltage data of one difference is
This is the input to the shift register 10 of. In the embodiment of the present invention, tuning voltage data with a positive difference is always input to the second shift register 10.

Next, an outline of the fine tuning operation in such a tuning device will be explained. With the fine adjustment key 16,
When the fine adjustment operation is performed, a fine adjustment operation signal is input to the fine adjustment control circuit 15. A fine adjustment control signal is inputted from the fine adjustment control circuit 15 to the fine adjustment count signal generation circuit 12. On the other hand, the amount of slight change in the tuning voltage data during fine adjustment control is calculated by dividing the difference tuning voltage data stored in the second shift register 10 by the circuit 1.
The signal is divided into N parts by 1 and input to the fine adjustment count signal generation circuit 12. In the fine adjustment count generation circuit, when the fine adjustment control signal is input, it generates a fine adjustment count signal corresponding to the digital data of the minute change in the tuning voltage data, and inputs it to the first reversible counter 7 to change the counter value. That is, the tuning voltage data preset in the first reversible counter is changed, the tuning voltage output value of the DA converter 2 is changed, and the electronic tuner 1 is finely tuned. The output of the clock pulse generating circuit 13 is used for pulse width modulation in the DA converter 2, and is also used as a count clock for the second counter 14 for fine adjustment and as a fine adjustment count signal.
Next, this fine tuning operation will be explained in more detail. FIG. 3 shows a first fine adjustment circuit according to the present invention, and explanations of parts that perform the same operations as those in FIG. 2 will be omitted. In Figure 3, 32 is a comparison circuit, 33 to 36
is a NOR gate, 33, 34 is 40, 35,
36 each constitute 41 RS flip-flops. 42 is a delay circuit with a time equivalent to one clock. The differential tuning voltage data from the subtraction operation circuit 9 is now obtained as 10-bit digital data and stored in the second shift register 10. If the step of minute change in the tuning frequency due to the fine adjustment control signal is, for example, 1/64 of the frequency interval of one channel, the amount of minute change in the tuning voltage data due to the fine adjustment control signal can be calculated by dividing the difference tuning voltage data by N = 64. Stop. The difference in tuning voltage data is expressed in two values, H (signal 1) and L (signal 0), and is stored in the second shift register, so dividing it by 64 means that the shift register's LSD (Least Significant
Digit) side is obtained by truncating 5 bits,
The minute change is stored as 5-bit digital data on the MSD (Most Significant Digit) side, and in the divider circuit 11, it is simply stored as MSD of the second shift register.
It is only necessary to select the value of the side 5 bits. Now, the fine tuning operation when a value of "01010" (change of 9 digits) is obtained as the value of the 5 bits on the MSD side of the differential tuning voltage data will be explained with reference to the timing chart shown in Figure 4. . By operating the fine adjustment operation key 16, the fine adjustment control circuit 15
A fine adjustment control signal h shown in FIG. 4 is output. This signal resets the second counter 14 for fine adjustment and is input to the delay circuit 42. After a delay of one clock, the RS flip-flop 34 is set by the signal g, and the signal "1" is output from the NOR 33 as shown in j. ” for fine adjustment count signal.
In addition to the AND gate 43, the clock pulse of the clock pulse generation circuit 13 is input to the first reversible counter 7.
In addition, the tuning voltage data starts changing. On the other hand, the second counter for fine adjustment is composed of 5 bits, and the counter value is input to the comparator circuit 32, and the data is compared with the 5 bits on the MSD side of the second shift register 10. When they match, the comparator circuit inputs the counter value. 32 outputs a coincidence signal. Therefore, the fine adjustment counter 14 reset by the fine adjustment control signal starts counting at the same time as the RS flip-flop 40 is set, and when the counter value becomes "01010" and matches the data of the 5 bits on the MSD side of the second shift register, The comparison circuit 32 outputs a match signal of i, resets the RS flip-flop 40, closes the AND gate 43, and stops outputting the clock pulse to the first counter. The clock input of the tuning voltage data by this one fine adjustment operation becomes 9 digits, which is the same as the necessary fine change step "01010". A similar operation is performed for other data, and the tuning voltage data is changed by the same amount as the minute change in the tuning voltage data obtained by the division circuit 11.

Note that during fine adjustment control, the fine adjustment direction designation signal is output from the fine adjustment control circuit 15 to the RS flip-flop 41 to change the output signal of the RS flip-flop 41. The output signal of this RS flip-flop 41 is input to the first reversible counter 7,
In the first reversible counter, the counter value is increased or decreased during fine tuning in accordance with the output signal of the RS flip-flop 41, thereby changing the tuning voltage data in accordance with the fine tuning direction, that is, fine tuning the tuning frequency.

Fine adjustment is performed in this way, but the amount of slight change in the tuning voltage data is determined by dividing the difference tuning voltage data by N and rounding off the fraction (second shift register
(Selection of 5 bits on the MSD side), the value is smaller than the actual difference tuning voltage data by 1/N, but it is a value close to 1/N. As a result, the tuning voltage output value of the DA converter 2 changes similarly, and the step of minute change in the tuning frequency of the electronic tuner also changes at a value close to approximately 1/N of the frequency interval "K" of one channel. Since this standardization of the amount of minute change in the tuning voltage during fine tuning control is performed every time a channel is selected, the step of minute change in the tuning frequency between channel numbers will be approximately the same value, and the deviation between channel numbers will be significantly reduced. It is something that can be done. In addition, if there are variations in tuning voltage control sensitivity during the manufacture of electronic tuners,
Tuning voltage data corresponding to the electronic tuner is stored in a non-volatile memory and is standardized based on this tuning voltage data, so that the slight change step of the tuning frequency becomes approximately the same value. FIG. 5 shows a second fine adjustment circuit according to the present invention. Figures 2 and 3
Descriptions of those that perform the same operations as those shown in the figure will be omitted. Fifth
In the figure, 50 to 53 indicate counter stages for 4 bits on the LSD side of the first reversible counter, and 54 indicates counter stages for 4 bits on the LSD side of the first reversible counter.
It shows counter stages for 6 bits on the MSD side.
60 to 63 are OR gates, and 70 to 74 are AND gates. Similar to the fine adjustment circuit shown in FIG. 3, the differential tuning voltage data is stored in the second shift register 10 as a 10-bit value. Since the division circuit 11 similarly divides the amount of minute change in the tuning voltage data by N=64, the MSD of the second shift register 10
In this embodiment, the position signal of the most significant bit of this divided data is further applied to the AND of the fine adjustment count signal generation circuit 12.
70-74. For example, when the tuning voltage data of the difference divided by N is "00100" from the LSD side, the position is only from c of the divider circuit 11, when it is "00111" it is from a, and when it is "11000" it is from b. The highest position signal a that outputs the signal is
The lowest position signal e is input to AND74, and so on to AND70. On the other hand, fine adjustment control circuit 15
outputs a fine adjustment control signal of only one clock during fine adjustment operation and adds it to AND70~74.
74 is selected and outputted to the first reversible counter 7.

The first reversible counter 7 is composed of a 10-bit counter, and the 5-bit counter stage on the LSD side is connected to the fine-adjustment count signal generation circuit 12.
Fine adjustment count signal from directly or OR60
Input through 63 and 51 in the second and subsequent rows
In each stage of 56 to 56, carry and down signals from the counter in the previous stage are also input through OR60 to 63. When the value obtained by dividing the differential tuning voltage data by N using such a fine adjustment circuit is a value of "10100" (5 digits), the division circuit 11 outputs a position signal "1" of c. This signal is input to AND72 and opens this gate. During fine adjustment operation, the fine adjustment control signal of only one clock from the fine adjustment control circuit 15 is selected and output by this AND72, and the OR
61 and is input to the third counter stage 52 of the first reversible counter 7. In this first reversible counter 7, the 3
The count value after the counter stage of the second stage is changed by one digit. LSD of first reversible counter 7
Since the third counter stage from the side inputs and counts a ^22- digit signal, the tuning voltage data is slightly changed by 4 digits during the fine adjustment operation. In this way, only the most significant bit of one signal of minute change amount data is changed, and minute change data less than that is truncated. For example, even if the minute change amount data of the tuning voltage data is “00001” (16 digits), it is “11111”.
(31 digits), but the tuning voltage data only changes to the same “00001” (16 digits), so
In the second fine adjustment circuit according to the present invention, during fine adjustment control, the tuning voltage data changes between 1/N and about 1/2N of the tuning voltage data for one channel, that is, approximately 1/2 of the frequency interval of one channel. The tuning frequency changes slightly in frequency steps from /N to 1/2N. This means that the variation in the fine tuning change step of the tuning frequency is larger than in the first fine tuning circuit of the present invention, but even if there is variation in the tuning voltage control sensitivity between channel numbers or during the manufacturing of the electronic tuner, the variation is about twice as large. deviation, which can be significantly improved compared to the conventional example. Compared to the first fine-tuning circuit, this second fine-tuning circuit does not require the fine-tuning counter used in the first fine-tuning circuit, which simplifies the circuit.In addition, the tuning voltage data can be changed immediately, and the amount of minute change in the tuning voltage data is small. When is large, there are advantages such as faster fine tuning changes in the tuning frequency.

In addition, in the division circuit that divides the difference tuning voltage data in the first and second fine adjustment circuits of the present invention by N, if the difference tuning voltage data is less than N digits, a slight change in the tuning voltage during fine adjustment will occur. The quantity is "0", that is, it cannot be changed. For this purpose, the amount of slight change in the tuning voltage is set to the minimum 1
Either use a circuit configuration that changes the tuning frequency by the number of digits (in this case, the minute change in the tuning frequency will be larger than 1/N), or change the tuning voltage data so that the difference in tuning voltage data is greater than or equal to N digits. This can be solved by increasing the number of configuration bits. In addition, although the operation of the fine adjustment circuit has been described above,
It is clear that a similar operation is performed in the fine adjustment by the AFT circuit.

As described above, according to the present invention, fine adjustment and AFT
It is possible to significantly reduce the deviation of the fine change step of the tuning frequency due to fine tuning of the circuit, and by appropriately selecting the fine change step,
Problems such as the fine tuning change step being too large and not being able to set an accurate tuning point, or too small and taking a long time to set to the tuning point have been solved, and accurate tuning point setting with less variation in setting time has been solved. I can do it.

As described above, according to the channel selection device of the present invention, between the channel numbers of the signals received during fine tuning operation of the tuning frequency by the AFT circuit or the fine tuning circuit,
Even if there are variations in the tuning voltage control sensitivity during the manufacture of electronic tuners, it is possible to make the minute change steps of the tuning frequency almost the same and to significantly reduce the deviation, making it accurate and eliminating variations in the setting time. This has the advantage that fewer tuning points can be set.

[Brief explanation of drawings]

FIG. 1 is a graph showing a tuning curve of an electronic tuner for explaining the outline of the content of the present invention, FIG. 2 is a block diagram showing an embodiment of a tuning device according to the present invention, and FIG. 3 is a graph showing an embodiment of a tuning device according to the present invention. A circuit diagram showing a first embodiment of a fine adjustment circuit of a tuning device; FIG. 4 is a signal waveform diagram for explaining the operation of the fine adjustment circuit shown in FIG. 3;
FIG. 5 shows the second fine adjustment circuit of the tuning device according to the present invention.
It is a circuit diagram showing an example of. 1...Electronic tuner, 2...D-A converter, 3
...Nonvolatile memory, 5...Tuition selection control circuit, 7...
...First reversible counter, 9...Subtraction operation circuit, 1
0... Second shift register, 11... Division circuit, 12... Fine adjustment count signal generation circuit, 15...
...Fine control circuit.

Claims (1)

[Claims] 1. An electronic tuner having a voltage-controlled tuning circuit, and tuning voltage data for a channel corresponding to a channel number to be tuned by converting a tuning voltage applied to the electronic tuner into a digital signal. and a nonvolatile memory that permanently stores the channel number, and when selecting a channel, the tuning voltage data corresponding to the desired channel number is read from the nonvolatile memory, and the tuning voltage data is digital-to-analog converted and sent to the electronic tuner. In a tuning device that performs tuning by applying voltage, it calculates the tuning voltage data of the difference between the selected channel number and the tuning voltage data of a channel number that is separated from this channel number by an approximately constant number of channels, and also calculates the tuning voltage data of the difference. An arithmetic circuit is provided that divides the voltage data by a substantially constant value and standardizes it as a fine adjustment voltage data change amount, and the tuning voltage data of the selected channel number read from the nonvolatile memory at the time of channel selection is stored in a memory configured as a counter. means for storing and digital-to-analog converting the tuning voltage data set in the counter and applying it to the electronic tuner for tuning; and an automatic fine tuning circuit for generating an AFT signal or a fine tuning circuit for generating a fine tuning signal. The tuning voltage data of the counter is changed by the fine tuning voltage data unit calculated for each channel selected by the AFT signal or the fine tuning signal, and the tuning frequency of the electronic tuner is fine tuned. A channel selection device characterized by: 2. When calculating the difference between the tuning voltage data of a selected channel number and a channel number that is approximately a certain number of channels away from this selected channel number, the tuning voltage data of a channel number that is a certain number of channels away from the selected channel number is calculated. 2. The tuning device according to claim 1, wherein the tuning voltage data of the difference is obtained by changing the positive and negative directions from the channel number according to the selected channel number.