JPH0473324B2 - - Google Patents

Description

Detailed Description of the Invention The present invention uses an electronic tuner, digitizes the tuning voltage applied to the electronic tuner, stores it in a nonvolatile memory in correspondence with the channel number, and when tuning, tunes voltage data from the nonvolatile memory. The present invention relates to a channel selection device that reads out and selects a channel.

Using an electronic tuner with a voltage-controlled tuning circuit using variable capacitance diodes, the tuning voltage is encoded into a digital signal and stored in non-volatile memory in correspondence with each channel number.When selecting a channel, it is output from the non-volatile memory. The tuning voltage data corresponding to the desired channel number is read out, the tuning voltage data is digital-to-analog converted (hereinafter referred to as -A conversion), and applied to the electronic tuner for tuning, and a fine tuning circuit etc. is installed. Using the control signal output from this circuit, the tuning voltage data is slightly changed to finely tune the tuning frequency of the electronic tuner. (abbreviated as "signal frequency offset"), high-frequency modulated signals from video game equipment, etc., or deviations in the signal frequency set in the channel number of CATV signals (hereinafter abbreviated as "signal frequency offset").
Tuning devices that perform fine tuning in response to this are well known. With such a tuning device, if you make a mistake in the fine tuning operation of the tuning frequency during fine tuning,
There is a drawback that the change in the tuning frequency is too large, such that signals of other channel numbers different from the selected channel number are tuned and received.

An object of the present invention is to provide a tuning device that eliminates the drawbacks of the prior art described above and can prevent tuning to a signal with a channel number different from the selected channel number due to an error in fine tuning operation during fine tuning. There is a particular thing.

In order to achieve the above-mentioned object, the present invention calculates the difference in tuning voltage data between a selected channel number (hereinafter referred to as the selected channel number) and a channel number that is approximately a constant number of channels away from the selected channel number. Tuning voltage data is obtained, and based on this value, a range of change in the tuning voltage data during fine tuning is set, thereby limiting the range of change in the tuning frequency. The contents of the present invention will be explained below with reference to the drawings. FIG. 1 is a tuning curve showing the relationship between the tuning voltage and the tuning frequency of an electronic tuner having a tuning circuit using a variable capacitance diode as a control element. In FIG. 1, the horizontal axis shows the tuning voltage, and the vertical axis shows the tuning frequency. Generally, television, radio, etc. signals are spaced apart by a roughly constant frequency interval "K". The signals arranged at every frequency interval K have channel numbers, n-3, n-2, n-1, n, n+1, n.
Channel numbers are set consecutively, such as +2. In order to tune and receive each channel number, the electronic tuner has tuning voltages V _T (n-3) and V _T (n-3).
2), V _T (n), V _T (n+1), and V _T (n+2) are applied. Here, the tuning voltage V _T (n) of the selected channel number n and the tuning voltage V T (n-1), _{V T of} the adjacent channel number (n-1, n+1), for example.
(n+1) difference dV _T (n-1), dV _T (n+1)
is almost necessary for the change in the tuning voltage required to change the tuning frequency by the frequency interval K of one channel at the tuning point of channel number n. Therefore, the tuning voltage of the difference corresponding to the change in the frequency interval K of this one channel is
Based on dV _T (n±1), find the tuning voltage change value that will not receive signals of different channel numbers, and calculate this value by integrating this and the minute change in the tuning voltage during fine tuning. In comparison, if the integrated tuning voltage during fine tuning is large, the fine tuning operation is stopped and the tuning frequency is not changed any further.
This prevents reception of different channel numbers.

The contents of the present invention will be explained in detail below using examples. FIG. 2 explains the fine tuning operation by the channel selection device in the first embodiment of the present invention.
In Figure 2, 1 is an electronic tuner, 2 is a D-A converter,
3 is an integration circuit, 4 is a nonvolatile memory, 5 is a channel selection switch, 6 is a channel selection control circuit, 7 is a data center, 8 is a first reversible counter, 9 is a first shift register, and 10 is a subtraction operation 11 is a second shift register, 12 is a division circuit, 13 is a fine adjustment count signal generation circuit, 14 is a clock pulse generation circuit, 15 is a first up counter, 16 is a fine adjustment control circuit, 17 is a fine adjustment operation key, 18 is a second reversible counter, 19 is a second division circuit, 20 is a first comparison circuit, 21 is a fine adjustment stop circuit, second reversible counter 18, second division circuit 19, first comparison circuit 20 , the fine adjustment stop circuit 21 constitute a fine adjustment range limiting circuit 30. Referring to FIG. 2, the channel selection operation will first be explained. When a channel number is input by the channel selection switch 5, the channel selection control circuit 6
Tuning voltage data corresponding to the channel number is read from the nonvolatile memory 4 by the control signal and inputted to the data selector 7. At this time, the data selector 7 inputs the read tuning voltage data to the first shift register 9 in response to a signal from the channel selection control circuit 6. Next, according to the control signal of the channel selection control circuit 6, the tuning voltage data of the selected channel number and a certain number of channels, for example, a channel number separated by one channel in this embodiment, is read from the nonvolatile memory 4, and the data selector Enter 7.
At the same time as this second tuning voltage data read,
A shift signal for the first shift register 9 is generated from the tuning control circuit 6, and tuning voltage data of the tuning channel number is outputted and inputted to the data selector 7 and the subtraction calculation circuit 10. At this time, data selector 7
Then, the tuning voltage data of the selected channel number output from the first shift register 9 is inputted again to the first shift register 9, and the tuning voltage data of the channel number one channel away is inputted to the subtraction operation circuit 10. The subtraction operation circuit 10 performs a subtraction operation by selecting and distinguishing between the two tuning voltage data, the signal to be subtracted and the subtracted signal, using the control signal from the channel selection control circuit 6, and the second shift register 11 receives the difference as a result of the subtraction. Enter tuning voltage data.

Thereafter, by the control signal from the tuning control circuit 6,
The tuning voltage data of the selected channel number stored in the first shift register 9 is preset as a counter value in the first reversible counter 8, and based on this counter value, the D-A converter 2 performs pulse width modulation. , it is converted into an analog tuning voltage by the integrating circuit 3, and applied to the electronic tuner 1 to tune to the signal of the selected channel number and perform tuning. Next, the fine adjustment operation will be explained. When a fine adjustment operation is performed using the fine adjustment operation key 17, a fine adjustment operation signal is inputted to the fine adjustment control circuit 16. A fine adjustment control signal is input from the fine adjustment control circuit 16 to the fine adjustment count signal generation circuit 13. On the other hand, the amount of minute change in the tuning voltage data during fine adjustment control is obtained by dividing the difference tuning voltage data input into the second shift register 11 by N in the first division circuit 12, and this value is used as the fine adjustment count signal. When the fine adjustment control signal from the fine adjustment operation is inputted to the generation circuit 13, the fine adjustment count generation circuit 13 generates a fine adjustment count signal corresponding to the digital data of the calculated minute change amount and outputs it to the fine adjustment stop circuit 21. do. If the fine adjustment stop signal is not input to the fine adjustment stop circuit 21, the fine adjustment count signal is input to the first reversible counter 8, and the fine adjustment control circuit 1
6, the counting direction of the first reversible counter 8 is changed to increase or decrease the counter value, that is, the tuning voltage data preset in the first reversible counter 8 is changed, and the electronic tuner The tuning frequency is finely tuned by changing the output value of the tuning voltage applied to 1. On the other hand, the fine adjustment stop circuit 21
The fine count signal from the second reversible counter 1
8, and counts up or down depending on the fine adjustment direction of the fine adjustment control circuit 16.
Calculate by integrating the changes in tuning voltage data during fine adjustment operations. Further, from the difference tuning voltage data stored in the second shift register 11, the second division circuit 1 calculates a range of change in the tuning voltage data such that a signal with a different channel number is not received during fine adjustment operation.
Find it in 9. The first comparison circuit 20 integrates the change range of the tuning voltage data during the fine adjustment operation (hereinafter referred to as fine adjustment control range data) and the change in the tuning voltage data during the fine adjustment operation obtained by the second reversible counter 18. The values (hereinafter abbreviated as fine adjustment operation integrated data) are compared according to the fine adjustment direction signal of the fine adjustment control circuit 16, and if the fine adjustment operation integrated data matches the fine adjustment control range data, a fine adjustment stop signal is generated and the fine adjustment is stopped. The output of the fine adjustment count signal from the circuit 21 is stopped, and the change in the count value of the first reversible counter 8 is stopped to prevent fine adjustment, thereby keeping the tuning frequency change of the electronic tuner 1 within a preset tuning frequency change range. This prevents signals with different channel numbers from being received during fine adjustment operations. First, the fine adjustment circuit of the channel selection device of the present invention will be explained using the drawings. FIG. 3 shows a fine adjustment count signal generation circuit 13 according to the first embodiment of the present invention.
This shows the parts in more detail, and the parts that perform the same operations as those in FIG. 2 are given the same numbers and their explanations are omitted. In Figure 3, 31 and 32 are OR gates, which constitute a flip-flop (abbreviated as FF) 33, 34 is an AND gate, 35 is a second comparison circuit, and 36 is a delay circuit equivalent to one clock. These constitute the fine adjustment count signal generation circuit 13. The differential tuning voltage data from the subtraction operation circuit 10 is now obtained as 8-bit digital data and stored in the second shift register 11. If the step of minute change in the tuning frequency due to the fine adjustment control signal is, for example, 1/32 of the frequency interval K of one channel, then the amount of minute change in the tuning voltage data due to the fine adjustment control signal will be the tuning difference that is almost necessary for the change in the tuning frequency of one channel. It is found by dividing (dividing) the voltage data by N=32. The difference in tuning voltage data is stored as a binary digital signal, so minute changes in the tuning voltage data are stored in the second shift register 1.
LSD (Least
It is obtained by cutting off 4 bits on the MSD (Most Significant Digit) side, and 4 bits on the MSD (Most Significant Digit) side are
It is determined as a bit value, and the first division circuit 12 only needs to select the value of the 4 bits on the MSD side of the second shift register 11. Now, if the differential tuning voltage data is, for example, "01110110" from the LSD side, the minute change amount will be "0110" of 4 bits on the MSD side. The fine adjustment operation of the fine adjustment circuit shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. When the fine adjustment operation key 17 is operated, a fine adjustment control signal is outputted from the fine adjustment control circuit 16 as shown in d of FIG.
This fine adjustment control signal d is the first signal consisting of 4 bits.
It is also input to the up counter 15 of c to reset the counter, and is also input to the delay circuit 36, which outputs the delayed signal of c after a time delay equivalent to one clock.
The FF 33 is set and a "1" signal of f is output to open the gate of the AND 34, and the clock pulse of the clock pulse generation circuit 14, that is, the fine adjustment count signal, is applied to the fine adjustment stop circuit 21. After the first up counter 15 is reset, it starts counting at the same timing as the FF 33 is set, and the counter value of the first up counter 15 and the value of the 4 bits on the MSD side of the second shift register 11 are transferred to the second up counter 15. The comparison circuit 35 checks for a match, and if there is a match,
In this example, when the first up counter value reaches "0110", the reset signal c is output, FF33 is reset, and the gate of AND34 is closed.
Stop outputting the fine adjustment count signal to 1. The number of clocks of the fine adjustment count signal due to this one fine adjustment operation is 5 digits, which is the same as "0110" and the amount of slight change in the tuning voltage data obtained by the division circuit 12. Even if tuning voltage data with other differences is obtained, the same operation is performed to generate a fine adjustment count signal that can change the tuning voltage data by the same amount as the amount of slight change in the tuning voltage data obtained by the first division circuit 12. do. During fine adjustment operation,
The fine count signal can be obtained in this way,
The amount of minute change in the tuning voltage data is obtained by dividing the difference tuning voltage data into N parts and rounding down the fraction (4 bits on the LSD side of the second shift register 11 are rounded down). The value will be smaller than the value multiplied by 1/N, but it will be a value close to 1/N. As a result, when the guard of the fine adjustment stop circuit 21 is opened and fine adjustment is possible, the tuning voltage of the second reversible counter 8 is changed by this fine adjustment count signal, and accordingly, the tuning frequency of the electronic tuner 1 is changed by a minute change step. also has a value close to 1/N of the frequency interval of one channel. Since this value is calculated each time the difference tuning voltage is selected, the value will be approximately 1/N even if the selected channel number changes. Next, the fine adjustment range control operation in the fine adjustment operation will be explained in more detail using the drawings. FIG. 5 shows a more specific circuit configuration of the fine adjustment range limiting circuit 30 of the tuning circuit of the present invention shown in FIG.
Components that perform the same operations as those shown in the figures are given the same numbers and their explanations will be omitted. 41-47 in Figure 3 are ER
(Exdsive R), 48 is NR gate, 49~
51 is an AND gate, 52 and 55 are inverters,
53 is an NR gate, and these are the first comparator circuit 2.
0 is configured, and 54 is an AND gate that constitutes the fine adjustment stop circuit 21. For example, change the control range of the tuning frequency during fine tuning so that the signal of the adjacent channel is not received.
Assuming that the frequency interval K of one channel is set to 1/2 in the high frequency direction (hereinafter abbreviated as positive direction) and the low frequency direction (hereinafter abbreviated as negative direction) from the tuning point, the frequency is stored in the second shift register. The value obtained by dividing the tuning voltage data with a difference approximately equal to the tuning frequency change of one channel by 1/2 indicates the tuning voltage control range during fine adjustment operation. In this case, the fifth
In the figure, the difference tuning voltage data is stored in binary form in the second shift register 11 consisting of 8 bits, and the control range of the tuning voltage during fine adjustment is truncated by 1 bit on the LSD side and 7 bits on the MSD side. It can be found by selecting . Therefore, the second division circuit 19 only needs to perform this data selection. On the other hand, the second reversible counter 18 that integrates the tuning voltage data during fine adjustment operation is composed of 8 bits, and the data after dividing the LSD 7 bits of this second reversible counter and the second shift register 11 is the LSD. , match MSD side and ER41~47
is being input. Further, the 8th bit data of the second reversible counter 18 is input to the AND 51, and its sign is inverted by the inverter 55.
Enter 50. When a channel is selected in FIG. 5, the tuning voltage data of the positive difference corresponding to the selected channel number is input to the second shift register 11, and a reset signal is output from the channel selection control circuit 6. Reset the second reversible counter 18. If the difference tuning voltage data is set to "01110110" from the LSD side with the same value as when explaining the fine tuning circuit operation, the tuning frequency change range is 1/2 of the frequency interval K of one channel in this example, so the tuning The voltage data change range is 1/2 of the tuning voltage data of this difference,
In other words, the LSD side data of the binary digital data is truncated by 1 bit, resulting in "1110110". In the first comparison circuit, ER41 to ER47 is the range of change in tuning voltage data. of the second shift register 11
It checks whether the 7 bits on the MSD side match the data on the second reversible counter 18, and after a new channel is selected, a reset signal is input to the second reversible counter 18, and all the data on the counter becomes "0". From, ER
43, 45-47 output is “1”, ER41, 4
2,44 output becomes "0". ER41-47
The output of ER is input to NR48 and AND49, but the output values of ER are "1" and "0" mixed, and the outputs of NR50 and AND51 are both "0". Therefore, the output of AND50-51 is “0”, N
The output of OR53 becomes “1” and fine adjustment stop circuit 2
“1” is input to the AND54 of 1 and the gate opens,
Fine control is possible. When a fine tuning operation is performed, a signal is sent from the fine tuning control circuit 13 to indicate whether to fine tune the direction of fine tuning from the tuned frequency point, that is, in the direction of higher frequencies (positive signal "1") or in the direction of lower frequencies (negative signal "0"). and output the first reversible counter 8,
second reversible counter 18, inverter 52,
In addition to being input to the AND 51, the fine adjustment count signal generation circuit 13 generates a fine adjustment count signal. The fine adjustment count signal outputted via the AND 54 of the fine adjustment stop circuit 21 is input to the clock input terminals on the LSD side of the first reversible counter 8 and the second reversible counter 18, and is input to the fine adjustment direction signal from the fine adjustment control circuit 13. Perform counting operation accordingly. At this time, the counting operations of the first reversible counter 8 and the second reversible counter 18 are performed synchronously. If the fine adjustment operation continues in the positive direction after tuning, and the value of the second reversible counter 18 as the fine adjustment operation integrated data is LSD.
When it becomes "1110110" from the side and matches the change range of the tuning voltage data after division, the outputs of ER41 to 47 all become "0" and the output of NR48 becomes "1". At this time, if you try to continue the fine adjustment operation in the positive direction, the fine adjustment control circuit 1
Since the fine adjustment direction signal of signal "1" is output from No. 3 and the data of the 8th bit of the second reversible counter is "0", the output of the inverter 55 is also "1".
Therefore, the output of AND50 is “1” and N
The output of R53 generates a “0” fine adjustment stop signal.
The gate of AND54 is closed to stop the output of the fine adjustment count signal, stop the fine adjustment operation, and stop any further change in the tuning frequency in the positive direction. When a fine adjustment operation in the negative direction is performed in this state, the signal in the fine adjustment direction becomes "0", the output of AND50 becomes "0", and the N
The output of OR53 becomes "1", the gate of AND54 opens, a fine adjustment count signal is output, and fine adjustment operation becomes possible again. After this, if the fine adjustment operation in the negative direction is continued, the data of the second reversible counter 18 becomes all "0" once, and then becomes all "1". After that, when a fine adjustment operation is further performed in the negative direction, the second reversible counter 18 continues to count down, and when the data becomes equal to "0001001" which is the 1's complement of the 7 bits on the MSD side of the second shift register 11, the ER41 ~47
The outputs of all of them become "1", and the output of AND49 also becomes "1". When attempting to continue the fine adjustment in the negative direction, the signal in the fine adjustment direction is "0", the output of the inverter 52 is "1", and the 8th bit data of the second reversible counter 18 is also "1". Therefore, the output of AND51 becomes “1” and NR
53 becomes "0", a fine adjustment stop signal is output, the gate of BND 54 is closed, the output of the fine adjustment count signal is stopped, the fine adjustment operation is stopped, and further changes in the tuning frequency in the negative direction are stopped. In this state,
For fine adjustment in the positive direction, since the signal in the fine adjustment direction becomes "1", the output of AND51 becomes "0", so N
The output of R53 also becomes "1", the output of the fine adjustment stop signal is stopped, the gate of AND54 is opened, and the fine adjustment count signal is output, so that fine adjustment operation in the positive direction is possible. As described above, even if the fine adjustment operation in the negative or positive direction is performed alternately, the fine adjustment beyond the set tuning voltage change range will not be performed.

The 8th bit data of the second reversible counter 18 is used to determine whether the fine tuning frequency point is in the positive direction or negative direction from the tuning frequency point determined by the tuning voltage data of the selected channel number after the fine tuning operation.
When in the negative direction, the second shift register 11
The 7 bits on the MSD side and the data of the second reversible counter 18 match, making fine adjustment in the positive direction impossible, and when the data is in the positive direction, the second shift register 11
This is to prevent the one's complement of the second reversible counter from matching with the 7-bit data on the LSD side, making fine adjustment in the negative direction impossible.

According to the operation described above, during fine adjustment, when the tuning voltage data exceeds a value that is almost the same as the change range of the set tuning voltage data,
There is no change in the tuning voltage during fine tuning, and therefore, in this embodiment, the change in the tuning frequency is limited to approximately 1/2 of the frequency interval K of one channel, and reception of signals of different channel numbers can be prevented. In addition, in the tuning device using the present invention, the tuning voltage corresponding to each channel number is stored in a nonvolatile memory,
At the time of channel selection, the difference tuning voltage data is obtained according to the channel number, so in the embodiment of the present invention, the range of change of the tuning voltage during fine tuning operation is set based on this difference tuning voltage data. Even if there are variations not only between channels but also during production of electronic tuners, etc., a substantially equal tuning frequency change restriction range can be obtained during fine adjustment operations, and reception of signals of different channel numbers can be prevented.

Next, a second embodiment of the present invention is shown in FIG. In FIG. 6, parts that perform the same operations as in FIG. 2 are given the same numbers, and their explanations are omitted. 60 in Figure 6
is a third reversible counter, and 61 is a detection circuit.
In the second embodiment of the present invention, as in the first embodiment, in the fine tuning circuit, the tuning frequency changes in steps of 1/N of the frequency interval K of one channel for each fine tuning operation. Here, the tuning frequency change range in the positive direction or negative direction from the tuning frequency point during fine tuning operation is set to 1/M of the frequency interval K of one channel so that signals with different channel numbers are not received.
shall be. In the first embodiment of the present invention, changes in tuning voltage data during fine tuning were obtained by directly integrating the changes, but in this second embodiment, the fine adjustment control signal necessary for one fine adjustment operation was obtained by using a third reversible counter. Find it by integrating it. In this embodiment, the detection circuit 61 determines whether the number of fine adjustment operations, that is, the cumulative number of fine adjustment control signals, has exceeded N/M, and if more fine adjustment operations are performed, the fine adjustment direction from the fine adjustment circuit 16 is determined. Fine adjustment stop circuit 2 outputs a fine adjustment stop signal according to the signal.
1, a fine adjustment count generation circuit 13 for fine adjustment control signals.
Stop the output to , stop the output of the fine adjustment count signal, and prevent fine adjustment operation, keep the change range of the tuning frequency during fine adjustment operation to within approximately 1/M of the frequency interval K of one channel, and perform fine adjustment operation. This prevents users from tuning to and receiving different channel numbers at different times. In the second embodiment of the present invention, compared to the first embodiment, there is a slight deviation between channels in the amount of tuning frequency change during one fine adjustment operation, and this causes a slight deviation in the frequency change control range. This has the advantage of simplifying the circuit configuration. FIG. 7 shows the second embodiment of the present invention.
This figure shows a more specific circuit configuration of the fine adjustment range limiting circuit 30 for explaining the fine adjustment range control operation of the embodiment in more detail.
Components that perform the same operations as those in FIGS. In Figure 7, 62 is an inverter, 64 and 65 are NR gates, and 63 is an AND
At the gate, these detect the circuit 61, and 66
Each fine adjustment stop circuit 21 is configured by an AND gate. Now, the change range of the tuning frequency during fine tuning operation is M = 2, that is, 1/1 of the frequency interval K of one channel.
2, the change step of the fine adjustment circuit is set to N=32 as in the fine adjustment circuit of the first embodiment, and the tuning frequency change in one fine adjustment operation is set to K/32. In this case, it is sufficient to prevent the counter value accumulated by the third reversible counter 60 of the fine adjustment control signal from changing by more than M/N=16. First, when a new channel selection is performed, the third reversible counter 60 consisting of 5 bits is reset by a signal from the channel selection control circuit 6, and all counter values become "0". After that, when a fine adjustment operation is performed, a fine adjustment control signal is outputted from the fine adjustment control circuit 16 and added to the AND 66. At this time, the third
The counter values of the reversible counters are all “0”, and the output signals of AND63 and AR64 are also “0”.
The output value of NR65 is "1", which opens the gate of AND66, and the fine adjustment control signal is output from AND66, inputted to the fine adjustment count signal generation circuit, outputs the fine adjustment count signal, and outputs the fine adjustment control signal from the first reversible counter 8. A fine adjustment operation is performed by increasing or decreasing the counter value according to a fine adjustment direction signal output from the fine adjustment control circuit 16. At this time, the fine adjustment control signal is integrated and counted by the third reversible counter 60 according to the fine adjustment direction signal. Now, after selecting a new channel, the fine adjustment operation in the positive direction is performed continuously, the fine adjustment control signal is output 15 times, the counter value of the third reversible counter 60 becomes "11110" from the LSD side, and then the fine adjustment operation continues. When attempting to perform fine adjustment in the direction, the fine adjustment signal in the positive direction is "1", so the output of AND63 is 1,
The output of NR65 becomes "0", outputs the fine adjustment stop signal, closes the gate of AND66, stops the output of the fine adjustment control signal, stops the fine adjustment operation by preventing the output of the fine adjustment count signal, and prevents further forward movement. Stop tuning frequency change.

When a fine adjustment operation in the negative direction is performed in this state, the fine adjustment direction signal becomes "0", the output of AND63 becomes "0", and accordingly, the output of NR61 becomes "1", opening the gate of AND66 to perform fine adjustment in the negative direction. Perform the action. After this, the fine adjustment operation in the negative direction continues, and the counter values of the third reversible counter 60 all become "0" and then all become "1", and then continue to count down until the counter value reaches "00001".
becomes. If you try to continue the fine adjustment operation in the negative direction in this state, the output of NR64 becomes “1”.
Therefore, the output of NR65 becomes "0", outputting a fine adjustment stop signal, prohibiting input of the fine adjustment control signal to the fine adjustment count signal generation circuit 13, and stopping the fine adjustment operation by not outputting the fine adjustment count signal. Stop any further change in the tuning frequency in the negative direction. In this state, fine adjustment operation in the negative direction is not performed, but when fine adjustment operation in the positive direction is performed, the fine adjustment direction signal becomes "1", so the output of ANDNR64 becomes "0", and the output of NR65 also becomes "1".
The gate of AND66 opens and fine adjustment becomes possible. In this example, the number of fine adjustment circuits in the positive direction is 1 more than the number of times set at 15 times of the third reversible counter value "11110".
There are fewer times, and in the negative direction it is “00001”, but
When counting down, all “0” to all “1”
Since there is a count state, the number of changes is suppressed to 16 times as set, and the amount of tuning frequency change due to one fine adjustment operation is 1/32 of the frequency interval of one channel, so
The range of change in the tuning frequency during the fine tuning operation is limited to approximately 1/2 of the frequency interval K of one channel set in the positive and negative directions, and reception of signals of different channel numbers can be prevented. In the tuning circuit using the present invention, the tuning voltage corresponding to the channel number is stored in a non-volatile memory, and the difference tuning voltage data is obtained every time a channel is selected, so the amount of tuning frequency change due to one fine tuning operation is a value close to 1/N of the frequency interval K of one channel even if there are variations not only between selected channel numbers but also during the production of electronic tuners, etc., so in this second embodiment of the present invention as well. , even if there are variations not only between channel numbers but also during the production of electronic tuners, a tuning frequency change range during fine tuning operation with little deviation can be obtained,
This can prevent signals from different channel numbers from being received.

In addition, in the electronic tuner used in the channel selection circuit of the above embodiment, there is a limit to the capacitance variable range of the variable capacitance diode that is the control element, and even if the channel numbers are consecutive, the signal frequency band is different. As shown in Figure 1, it is rare for the tuning frequency to change continuously for all channel numbers.For example, the receiving frequency bands for television signals in Japan are channels 1 to 3, 4 to 12, and 13 to 62. It is divided into three channel groups, and the changes in the tuning voltage of channel numbers 3 and 4, 12 and 13 are not continuous,
Furthermore, when calculating the difference between the selected channel number and a channel number that is separated by a certain number of channels, regardless of whether the selected channel number is larger or smaller, the maximum or minimum of the receivable channel group is calculated. For either channel number, there are no channel numbers that are separated by a certain number of channels. In order to prevent these, it is necessary to select whether the selected channel number is larger or smaller from the selected channel number, which is a certain number of channels apart from the selected channel number to be compared. In this embodiment, the channel selection control circuit 6 stores the magnitude of a channel number separated by a certain number of channels from the selected channel number to be compared according to the channel number, and when selecting a channel, according to the stored magnitude signal, Read out the tuning voltage data of channel numbers separated by a certain number of channels to be compared. For example, in a tuner that receives television signals in Japan, the interval between the selected channel number and the channel number to be compared is set to 1, which is a fixed number of channels, and the tuning voltage data of the smaller channel, that is, the -1 channel is usually read out. In this case, there is no channel number with the minimum channel number 1, so the +1 channel with the higher channel number,
Furthermore, since the reception frequency bands are different for the channels below 4 and 13, which are the lowest limits of the reception frequency band, and the tuning voltage data is discontinuous, the tuning voltage data on the +1 channel side is also read out. In addition, since the magnitude relationship of the tuning voltage data of the channel number separated from the selected channel number by a certain number of channels to be compared with the selected channel number differs depending on the selected channel number, the channel to be compared stored in the channel selection control circuit 6 is Depending on the size of the selected channel number, the tuned voltage data of the channel number separated by a certain number of channels is compared with the read selected channel number and is input into the subtraction calculation circuit 10 after being selected into a subtraction signal and a subtracted signal. However, tuning voltage data with a positive or negative difference is always obtained. For example, in the above example, if the electronic tuner is configured with a single superheterodyne receiver, generally the larger the channel number, the larger the tuning voltage, that is, the tuning voltage data. At this time, when trying to obtain tuning voltage data with a positive difference, if the channel number to be compared is -1 channel, the subtracted signal is the tuning voltage data of the channel number that is a certain number of channels away, and the signal to be subtracted is the selected channel number. tuning voltage data, and the channel to be compared is +1
In the case of a channel, the subtracted signal is the tuning voltage data of the selected channel number, and the signal to be subtracted is the tuning voltage data of the channel number separated by a certain number of channels. Although the number of differential channels is set to one channel in the present invention, it goes without saying that similar effects can be obtained with other numbers of channels.

As described above, according to the channel selection device of the present invention,
The fine adjustment frequency change range of the fine adjustment circuit can be set to a nearly constant value not only among all channel numbers, but also even when there are manufacturing variations in electronic tuners. By setting a value that does not occur, even if there is a mistake in operation during fine tuning, the change in the tuning frequency will be kept within the set fine tuning change range, and reception of a signal with a channel number different from the selected channel number will be prevented. can.

In the above explanation, only the fine tuning operation has been described, but the same effect can be obtained by fine tuning operation such as an automatic fine tuning circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the tuning curve of an electronic tuner for explaining the outline of the content of the present invention, FIG. 2 is a block diagram showing a first embodiment of the present invention, and FIG. 3 is a diagram similar to that of FIG. A block diagram showing the main parts to explain the operation, FIG. 4 is a signal waveform diagram to explain the operation of the circuit in FIG. 3, and FIG. 5 is a second diagram to explain the operation of the circuit in FIG. FIG. 6 is a block diagram showing the second embodiment of the present invention, and FIG. 7 is a main part of the block diagram in FIG. 6 for explaining the operation of FIG. 6. FIG. DESCRIPTION OF SYMBOLS 1...Electronic tuner, 2...D-A converter, 4...Nonvolatile memory, 6...Tuition selection control circuit, 8...First reversible counter, 10...Subtraction operation circuit, 11...Second shift register, 12... First division circuit, 13...
Fine adjustment count signal generation circuit, 16... Fine adjustment control circuit, 18... Second reversible counter, 20... Second division circuit, 21... Fine adjustment stop circuit, 30... Fine adjustment range limiting circuit, 60... Third reversible counter.

Claims (1)

[Scope of Claims] 1. An electronic tuner having a voltage-controlled tuning circuit, a memory that stores tuning voltage data corresponding to a channel number, and when tuning, reading tuning voltage data for a desired channel number from the memory. , comprising means for performing D-A conversion of the tuning voltage data and applying it to the electronic tuner for tuning, and a fine tuning circuit that slightly changes the tuning voltage data to finely tune the tuning frequency of the electronic tuner. In the channel selection device, when tuning voltage data for a desired channel number is read from the memory during tuning, the tuning voltage data for a channel number that is a certain number of channels away from the desired channel number is read from the memory. means for calculating a variation range as a limit of the tuning voltage data using a tuning voltage difference that is the difference between the two; and finely adjusting the tuning frequency of the electronic tuner by slightly changing the tuning voltage data by the fine tuning circuit. means for calculating a unit amount of minute change in the tuning voltage data using the tuning voltage difference, and changing the tuning voltage data by the fine tuning circuit by the unit amount of the calculated minute change, When the tuning frequency is fine-tuned, the unit amount of the slight change in the tuning voltage data is
an integrating means for integrating, a comparing means for comparing the integrated value by the integrating means with a change range of the tuning voltage data as the limit, and generating an output when the former exceeds the latter; and a comparing means for generating an output from the comparing means. A tuning device comprising: fine adjustment operation stopping means for stopping the fine adjustment operation by the fine adjustment circuit when the fine adjustment circuit has reached the fine adjustment circuit.