JPH0472384B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a heterojunction electric field device which is suitable for linear amplification elements and integrated circuit elements by preventing characteristics from changing over time and improving gate breakdown voltage. The present invention relates to an effect transistor and its manufacturing method.

(b) Background of technology Aiming to further improve the performance and cost performance of information processing equipment, higher speeds and lower power consumption of semiconductor devices are being promoted. Many transistors have been proposed that use much larger compound semiconductors such as gallium arsenide (GaAs).

Among these compound semiconductor transistors,
Heterojunction field effect transistors (hereinafter abbreviated as heterojunction FETs) are currently known, and have achieved an increase in carrier mobility from a structural standpoint through space-separated doping and interfacial quantization of electrons. As the fastest semiconductor device, its rapid commercialization is expected.

Furthermore, heterojunction FETs are expected to be used not only in digital circuits, but also as transistors for analog circuits, and there is a demand for improved characteristics as analog transistors, such as increased breakdown voltage.

(c) Prior Art and Problems An example of a conventionally known heterojunction FET is shown in a cross-sectional view in FIG.

In Figure 1, 1 is a semi-insulating GaAs substrate, 2
3 is a non-doped GaAs layer, 3 is an n-type aluminum gallium arsenide (AlxGa ₁ -xAs) layer, and the aluminum (Al) composition ratio x is, for example, 0.3. 4
is an AlxGa ₁ -xAs layer, and the Al composition ratio x is equal to that of layer 3 at the interface with layer 3, and gradually decreases upward to x=0. 5 is an n ⁺ type GaAs layer. Note that 6 is the non-doped GaAs layer 2.
This is a two-dimensional electron gas formed near the heterojunction interface with the AlGaAs layer 3. 7 is a source electrode;
8 is a drain electrode, and 9 is a gate electrode.

In the heterojunction FET with the above structure, the n-type AlGaAs layer 3 doped with impurities is called the electron supply layer, and since it has a lower electron affinity than the GaAs layer 2, it is absorbed by the electrons transferred from this layer to the GaAs layer 2. The two-dimensional electron gas 6 is located near the heterojunction interface.
is formed. This two-dimensional electron gas 6 functions as a gate channel of the heterojunction FET, and the two-dimensional electron surface concentration, that is, the impedance between the source electrode 7 and the drain electrode 8, is controlled by the voltage applied to the gate electrode 9. be done.

In the above-mentioned heterojunction FET, the n ⁺ type GaAs layer 5 is provided for the purpose of reducing the contact resistance of the source electrode 7 and the drain electrode 8 with the semiconductor substrate, and is used as a gate electrode that comes into occasional contact with the semiconductor substrate. 9 is provided in contact with the AlGaAs layer 4. Many also increase the gate threshold voltage with the AlGaAs layer 4
It is adjusted depending on the thickness.

To realize this structure, a heterojunction FET
Conventionally, in the manufacturing process, a gate pattern mask 10 is provided on a semiconductor substrate on which a source electrode 7 and a drain electrode 8 are provided, as shown in FIG.
A recess in which the n ⁺ type GaAs layer 5 and a portion of the AlGaAs layer 4 are selectively removed is usually formed by wet etching.

In the conventional heterojunction FET with the above structure,
Its properties change over time. That is, for example, the saturation value Idss of the source-drain current and the transfer conductance gm gradually decrease compared to their initial values. Also, the gate's shot resistance voltage gradually decreases.

The decrease in the source-drain current Idss and the transfer conductance gm is caused by the decrease in the electron surface concentration of the two-dimensional electron gas 6. This decrease in electron surface concentration is caused by the fact that the uppermost semiconductor layer around the gate electrode 9 is AlGaAs, and Al easily combines with oxygen (O ₂ ), and traps are formed as oxygen is taken into the semiconductor layer. This is thought to be due to a decrease in the number of electrons transitioning to the non-doped GaAs layer 2.

It is also believed that the decrease in the gate shot breakdown voltage is due to the aforementioned change in the semiconductor layer around the gate electrode 9.

A heterojunction FET that addresses the current situation as explained above and prevents changes in characteristics over time and improves reliability.
is requested to be provided.

(d) Object of the Invention An object of the present invention is to provide a semiconductor device, particularly a heterojunction FET which is prevented from aging as described above and has good and stable characteristics, and a method for manufacturing the same.

(e) Structure of the Invention A semiconductor device as an object of the present invention includes a first undoped gallium arsenide layer, an aluminum gallium arsenide layer containing donor impurities, and a second arsenide layer on a semi-insulating gallium arsenide substrate. A two-dimensional electron gas is provided near the heterojunction interface between the first gallium arsenide layer and the aluminum gallium arsenide layer, and the thickness of the second gallium arsenide layer is set to a gate electrode. A semiconductor in which the gate electrode completely covers the aluminum gallium arsenide layer that is thinned in the vicinity and exposed by cutting just below the gate electrode, and the gate electrode extends to the thin part of the second gallium arsenide layer. provided by the device.

As an example of the semiconductor device, the second gallium arsenide layer may be connected to a third gallium arsenide layer;
and a fourth gallium arsenide layer containing donor impurities at a higher concentration than the gallium arsenide layer, and the gate electrode is in contact only with the third gallium arsenide layer.

By completely covering the aluminum gallium arsenide layer exposed in the second region with the gate electrode, changes in characteristics over time are prevented. On the other hand, a new parasitic capacitance is generated at the contact surface between the side surface of the gate electrode and the second gallium arsenide layer, which lowers the cutoff frequency. Therefore, in the present invention, by providing a thin portion in the second gallium arsenide layer and forming the gate electrode in contact with only that portion, it is possible to completely cover the aluminum gallium arsenide layer without increasing parasitic capacitance. .

The semiconductor device also includes growing a non-doped first gallium arsenide layer, an aluminum gallium arsenide layer containing donor impurities, and a second gallium arsenide layer on a semi-insulating gallium arsenide substrate; A gate pattern mask having an opening is provided on the second gallium arsenide layer, and isotropic etching is performed using the opening to reduce the thickness of the second gallium arsenide layer to form a first region. Then, selectively performing anisotropic etching on the second gallium arsenide layer using the opening to remove the second gallium arsenide layer within the first region to form a second region. and then deposit gate metal to form the aluminum arsenide in all of the second areas.
Preferably, the manufacturing method includes the steps of forming a gate electrode in contact with the gallium layer and terminating within the first region, and then removing the gate pattern mask.

(f) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.

FIGS. 3a to 3g are cross-sectional views showing the main manufacturing steps of an embodiment of the present invention.

See Figure 3a. On the semi-insulating GaAs substrate 21, a non-doped
An n-type GaAs layer 22 with a thickness of, for example, about 0.3 to 3 [μm], an Al composition ratio x of 0.3, and silicon (Si) doped to about 2×10 ¹⁸ [cm ^-3 ]
The AlxGa ₁ -xAs layer 23 is made to have a thickness of about 30 [nm], for example, and then impurities are doped in the same way as the layer 23, and the Al composition ratio x is equal to that of the layer 23 at the interface with the layer 23 and gradually decreases. The n-type AlxGa ₁ -xAs layer 24 where x=0 is formed to a thickness of, for example, 30 [nm].
Furthermore, for example, Si may be added in an amount of 2×10 ¹⁷ to 7×10 ¹⁷ [cm
^-3 ] doped n-type GaAs layer 25 to a thickness of about 50 [nm], for example, Si is doped to about 1×10 ¹⁸ to 4
n ⁺ type GaAs layer 26 doped to about ×10 ¹⁸ [cm ^-3 ]
is continuously epitaxially grown to a thickness of, for example, about 100 [nm]. Along with the above semiconductor layer formation, the n-type AlxGa ₁ − of the non-doped GaAs layer 22
A two-dimensional electron gas 27 is formed near the heterojunction interface with the xAs layer 23. In this example, the growth is performed by a molecular beam crystal growth method.

The non-doped GaAs layer 22 and the n-type AlxGa ₁
- Non-doped AlxGa ₁ - between the xAs layer 23
Inserting an xAs layer is also often done. Further, the impurity doping of the GaAs layers 25 and 26 is a means to ensure low resistance connection between the source electrode and the drain electrode, which will be described next, and may be replaced by other means as described later ^. GaAs
The structure of this embodiment in which layer 26 is provided is the most practical.

Refer to FIG. 3b. The semiconductor substrate is subjected to mesa etching for isolation between elements or formation of high resistance regions. (Illustration omitted) Next, the source electrode 28 and the drain electrode 29 are made of, for example, gold/germanium (AuGe (Ge 12% by weight)).
and gold (Au) are sequentially deposited, patterned and disposed, and alloyed to form a low resistance contact.

Refer to FIG. 3c. An electron beam resist such as Fujitsu's positive resist CMR-100 is applied onto a semiconductor substrate, heated, and subjected to direct electron beam exposure and development to obtain a gate pattern mask 30.

Refer to Figure 3d. Hydrofluoric acid (HF) is
The n ⁺ type GaAs layer 26 is removed by etching using an etching solution or the like. Usually this etching is n
It also affects the type GaAs layer 25. That is, by measuring the source-drain current during etching,
Etching is terminated approximately halfway through layer 25.

Refer to FIG. 3e. A second etching process is performed using a reactive ion etching method. In this example, in a gas with a flow rate ratio of dichlorodifluoromethane (CCl ₂ F ₂ ): helium (He) = 1:1, a pressure of about 5 [Pa], a frequency of 13.56 [MHz], a power density of about
A power of 0.18 [W/cm ² ] is applied to selectively remove the n-type GaAs layer 25 in the wet recess region, affect the n-type AlxGa ₁ -xAs layer 24, and stop the process. The etching rate of the AlGaAs layer 24 is about 1/200 of that of the GaAs layer, which has sufficient selectivity, so that it is easy to control the termination of etching, and furthermore, the etched surface becomes a good flat surface.

Since this second etching process proceeds almost perpendicularly to the surface of the semiconductor substrate faithfully to the pattern of the gate pattern mask 30, the recess has a two-stage shape as shown.

Refer to FIG. 3f. For example, a gate metal such as aluminum (Al) is applied to the semiconductor substrate in a vacuum from a direction perpendicular to the semiconductor substrate surface through a gate pattern mask 30 at a distance of approximately 500 mm.
~800 [nm] deposited. As a result, a gate electrode 31 is formed as illustrated in the figure. If the gate electrode 31 is formed by this method, the exposed surface of the n ⁺ type AlGaAs layer 24 will be completely covered with the gate electrode 31, and the gate electrode 31 will be completely covered with the n + type AlGaAs layer 24.
It never touches 6.

Refer to FIG. 3g. By peeling off and removing the gate pattern mask 30, unnecessary gate metal 32 is lifted off, and a heterojunction FET device is completed.

The electrical characteristics of the conventional example and the embodiment of the present invention are that the saturation current between the source and drain electrodes and the transfer conductance of the conventional example when left at room temperature for 100 hours decrease by 10 to 30%, and the series connection between the source and gate electrodes decreases by 10 to 30%. Resistance increases by about 10-30%. Also, the shock resistance is reduced by 10 to 40%. Also, in accelerated tests by heating, changes in diameter occur in a short period of time. Compared to the conventional examples described above, the variations in the characteristics of the embodiments of the present invention are all within several percent. In accelerated testing by heating
Highly reliable heterojunction comparable to GaAs MESFET
A FET element is obtained.

In the above embodiment, the drawing shows a depletion type, but when the AlGaAs layer under the gate is on the order of 2×10 ¹⁸ , it is a depletion type if it is 30 [nm] or more, and the thickness is 10 to 15 nm. When it is below [nm], it becomes an enhancement type.

As clarified by the above explanation, in the conventional heterojunction FET, the AlGaAs layer is exposed around the gate electrode, whereas in the heterojunction FET of the present invention, the AlGaAs layer is exposed around the gate electrode. The area that had previously been covered is now covered with a GaAs layer.
Changes in characteristics over time in the conventional structure described above are prevented. Further, by covering the AlGaAs layer in this manner, the influence of the surface air layer on this layer is reduced, and the effect of increasing the areal density of the two-dimensional electron gas, that is, increasing the transfer conductance gm, can be obtained.

The carrier concentration of the GaAs layer surrounding the gate electrode is, for example, 1×10 ¹⁸ which is suitable for ohmic contact.
If it is about 4×10 ¹⁸ [cm ^-3 ], this will lead to a decrease in shot resistance voltage and an increase in parasitic capacitance. In particular, the reduction in gate breakdown voltage is a serious problem for linear amplification elements for analog circuits, which require a higher breakdown voltage than digital circuits. Taking this point into consideration, in the above embodiment, an n-type GaAs layer 25 and an n ⁺ type GaAs layer 26 having different carrier concentrations are formed on the AlGaAs layer 24.
The n ⁺ type GaAs 26 is layered with the carrier concentration suitable for forming an ohmic contact electrode.
The GaAs layer 25 has a carrier concentration of about 5×10 ¹⁷ [cm ^-3 ] or less, which can maintain the gate breakdown voltage at a required level of about 5 [V] or more.

Regarding the vicinity of the gate electrode, it is advantageous for the GaAs layer to have a lower carrier concentration in terms of gate breakdown voltage and parasitic capacitance. n-type in the above embodiment
The reason why the carrier concentration of the GaAs layer 25 is selected to be about 2×10 ¹⁷ [cm ^-3 ] or higher is because of the low resistance connection between the source electrode 28 and the drain electrode 29 and the two-dimensional electron gas 27, as described above. The carrier concentration of the GaAs layer 25 is set to the above value on the premise that impurities are selectively introduced into these ohmic connection regions by a method such as ion implantation or selective epitaxial growth. If it is lower than in the example, effects such as an improvement in gate breakdown voltage and a reduction in parasitic capacitance can be obtained. Further, it is also possible to omit the n ⁺ type GaAs layer 26 based on the above-mentioned means.

In the present invention, the shot contact surface of the gate electrode with the AlGaAs layer and the GaAs coating layer are provided by the two-stage recess structure as described above. Of these two surfaces, the AlGaAs layer surface is a heterojunction
Although it largely controls the characteristics of the FET, the manufacturing method of the present invention makes it possible to form a surface with good flatness with good reproducibility.

(g) Effect of the invention As explained above, the present invention enables GaAs-
In an AlGaAs-based heterojunction FET, by covering the AlGaAs layer with a GaAs layer and providing a gate electrode on a two-stage recessed structure, parasitic capacitance is reduced, changes in characteristics are prevented, and transfer conductance is reduced. Increase is achieved. Furthermore, it is possible to select the impurity concentration of the GaAs layer, and it is possible to improve the gate breakdown voltage and reduce the parasitic capacitance. This improvement in gate breakdown voltage is particularly effective for linear amplification heterojunction FETs.

Further, the manufacturing method of the present invention can produce the heterojunction.
By manufacturing the FET, it is easy to form the active layer region uniformly and with good reproducibility, which greatly contributes to the practical application of the heterojunction FET.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional example of a heterojunction FET, FIG. 2 is a sectional view showing an example of a manufacturing method for forming a recess in the conventional example, and FIGS. It is a sectional view showing a state in a manufacturing process. In the figure, 21 is a semi-insulating GaAs substrate, 22
is a non-doped GaAs layer, 23 and 24 are n-type
AlxGa ₁ −xAs layer, 25 is n-type GaAs layer, 26 is n ⁺
27 is a two-dimensional electron gas, 28 is a source electrode, 29 is a drain electrode, 30 is a gate pattern mask, and 31 is a gate electrode.

Claims (1)

[Scope of Claims] 1. A non-doped first gallium arsenide layer, an aluminum gallium arsenide layer containing donor impurities, and a second gallium arsenide layer are sequentially stacked on a semi-insulating gallium arsenide substrate, In a semiconductor device in which a two-dimensional electron gas is formed near a heterojunction interface between a gallium arsenide layer and the aluminum gallium arsenide layer, and a gate electrode is connected to the aluminum gallium arsenide layer, a region near the gate electrode is provided. The second gallium arsenide layer is formed of a third gallium arsenide layer formed thinner than the second gallium arsenide layer, and the gate electrode is formed within the gate electrode window of the third gallium arsenide layer. completely covers the aluminum gallium arsenide layer exposed in the third layer, and the gate electrode
A semiconductor device characterized in that the semiconductor device extends only to the surface of the gallium arsenide layer. 2. A step of growing a non-doped first gallium arsenide layer, an aluminum gallium arsenide layer containing donor impurities, and a second gallium arsenide layer on a semi-insulating gallium arsenide substrate, and the second arsenide layer. Providing a gate pattern mask having openings on the gallium layer, and performing isotropic etching using the openings to reduce the thickness of the second gallium arsenide layer to form a third gallium arsenide layer. Then, selectively anisotropic etching is performed on the third gallium arsenide layer using the opening, and the third gallium arsenide layer is removed within the third gallium arsenide layer to remove the aluminum arsenide. forming an opening exposing the gallium layer; and then depositing a gate metal to contact the aluminum gallium arsenide layer in the entire area of the opening and terminating within the third gallium arsenide layer; A method for manufacturing a semiconductor device, comprising the steps of forming an electrode and then removing the gate pattern mask.