JPH0472873A - Picture display device - Google Patents

Abstract

PURPOSE:To effectively use the dynamic range of a display means and to display a picture of good quality by operating an auto-pedestal processing part only in the effective display period for an input video signal by the operation control of a control part. CONSTITUTION:A double-speed video signal subjected to the aspect ratio conversion processing by an aspect ratio conversion circuit 8 is selectively supplied to an auto-pedestal processing circuit 10 through a switch circuit 9 for signal switching. The auto-pedestal processing circuit 10 detects the minimum signal level of the input video signal and automatically controls the signal level based on the detection result. That is, the auto-pedestal processing circuit 10 is operated only in the effective display period for the input video signal to detect the minimum signal level of the input video signal and controls the signal level of the video signal based on the detection result. Thus, the malfunction of the auto-pedestal processing circuit 10 is prevented, and the dynamic range of the display means is effectively used to display the picture.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention detects the minimum signal level of an input video signal,
It relates to an image display device equipped with an autopedestal processing unit that controls the signal level of a video signal based on the detection result, and is applied to an image display device such as a television receiver having a display means for a display screen with a wide aspect ratio. .

B1 Summary of the Invention The present invention detects the minimum signal level of an input video signal,
In an image display device equipped with an autopedestal processing section that controls the signal level of a video signal based on the detection result, the autopedestal processing circuit can be operated by providing a control section that operates the autopedestal processing circuit during an effective display period for the input video signal. Preventing malfunction of the pedestal processing unit,
This allows for image display with good image quality.

C3 Prior Art Conventionally, image display devices such as television receivers, which display images based on video signals on display means such as cathode ray tubes and liquid crystal displays, have been widely known. In such an image display device, by providing an autopedestal processing unit in the video signal processing system that detects the minimum signal level of the human-powered video signal and controls the signal level of the video signal based on the detection result, the above-mentioned problem can be achieved. The dynamic range of the display means is effectively utilized to display images of good quality.

By the way, in current television broadcasting, the aspect ratio of the display screen is 4=3. but,
Second generation EDT V scheduled for implementation in the future
In extended definition TV (extended definition TV) broadcasting and high-definition television broadcasting such as high-definition television, it is planned to widen the screen aspect ratio to 16=9.

Therefore, in the future, in addition to the current 4:3 standard aspect ratio television broadcast, it is expected that 16:9 wide aspect ratio television broadcast will be performed side by side. Development of an image display device that can also display images is currently underway.

In such an image display device, for example, using a display means with a display screen having a wide aspect ratio of 16:9,
Various methods as shown in No. 131m have been proposed as methods for displaying images of video signals with a standard aspect ratio of 3.3.

That is, the first method, as shown in FIG. 13A, cuts the upper and lower regions P, , P2 of the image PN of the standard aspect ratio video signal, and displays the image on the entire wide aspect ratio display screen. This is a method for displaying P3. In this first method, the standard aspect ratio video signal is overscanned in the vertical direction of the screen and displayed on the wide aspect ratio display screen without any modification.

The second method, as shown in FIG. 13B, masks the right side l'' if area A□ of the wide aspect ratio display screen, and converts the image P of the standard aspect ratio video signal into the above wide aspect ratio. In this second method, the standard aspect ratio video signal is horizontally reduced to 3/4 to correspond to the difference in aspect ratio from the wide aspect ratio display screen. After compressing the time axis, a frame signal for displaying the right side area AR in, for example, black is added, and the image is displayed on the wide aspect ratio display screen using the same mask scan as usual.

The third method, as shown in FIG. 13C, uses both left and right side areas A1 of a wide aspect ratio display screen. o+
This is a method of masking A Ilo and displaying the image P of the standard aspect ratio video signal in the center of the wide aspect ratio display screen. In this third method, the standard aspect ratio video signal is horizontally scaled by 3/3 to correspond to the aspect ratio difference with respect to the wide aspect ratio display screen.
By compressing the time axis to 4, the above left and right side areas ALO,A
A frame signal corresponding to ll0 is added and displayed on the wide aspect ratio display screen using the same mask scan as usual.

Furthermore, in the fourth method, as shown in FIG. 13D, the left site area AL of the wide aspect ratio display screen is masked, and the image P of the standard aspect ratio video signal is converted into the wide aspect ratio image P. This method displays on the right side of the display screen. In this fourth method, a video signal with a standard aspect ratio is time-compressed horizontally to 3/4 in accordance with the difference in aspect ratio with respect to a display screen with a wide aspect ratio, and the left side area A0. A mask signal corresponding to the image is added and displayed on the wide aspect ratio display screen using the same mask scan as usual.

D1 Problem to be Solved by the Invention By the way, in an image display device that displays a wide aspect ratio image and a standard aspect ratio image using a display means of a wide aspect ratio display screen, an autopedestal processing section is provided to display the image. When the image quality of the image is to be improved, if the signal level of the mask signal is within the level detection range of the autopedestal processing section,
There is a problem in that the black level is erroneously detected, the autopedestal processing section malfunctions, and it is not possible to display an image by effectively utilizing the dynamic range of the display means.

The present invention has been proposed in view of the above circumstances, and is intended to prevent malfunctions of the autopedestal processing unit and display a wide aspect ratio image and a standard aspect image using a display means for a wide aspect ratio display screen. It is an object of the present invention to enable an image display device configured to display a ratio image to display an image by effectively utilizing the dynamic range of the display means.

E6 Means for Solving the Problems In order to achieve the above-mentioned object, the image display device according to the present invention detects the minimum signal level of the input video signal and adjusts the signal level of the video signal based on the detection result. The present invention is characterized by comprising an autopedestal processing section for controlling the autopedestal processing section, and a control section for operating the autopedestal processing section described above during an effective display period for the human-powered video signal.

F1 action In the image display device according to the present invention, the autopedestal processing section whose operation is controlled by the control section operates only during the effective display period for the input video signal, detects the minimum decomposition level of the human input video signal, and The signal level of the video signal is controlled based on the detection result.

G. Embodiments Hereinafter, embodiments of the image display device according to the present invention will be described in detail with reference to the drawings.

The image display device (1) shown in FIG. 1 is one in which the present invention is applied to a high-definition television receiver that displays images using a picture tube (2) having a display screen with a wide aspect ratio of 16:9. It is.

This image display device (1) includes a BS tuner circuit (3) for satellite transmission and reception and a U/V tuner circuit (4) for terrestrial broadcast reception.

The Muse signal obtained as the reception output of the high-definition broadcast by the BS tuner circuit (3) is supplied to the Muse decoder circuit (5), and is decoded into a high-quality video signal by the Muse decoder circuit (5).

Further, the NTSC video signal obtained as the received output from the BS tuner circuit (3) or the U/V tuner circuit (4) is sent to the frame double speed conversion circuit (7) via the input switching switch circuit (6). This frame double speed conversion circuit (7) receives the N
For the TSC video signal, frame double speed conversion processing is performed to convert the interlaced scan mode video signal into a progressive scan mode, that is, a double speed video signal. The double speed video signal obtained by this frame double speed conversion circuit (7) is supplied to an aspect ratio conversion process (8). This aspect ratio conversion circuit (8) is the same as the frame double speed conversion circuit (7).
Regarding the double-speed video signal obtained by
) and performs aspect ratio conversion processing for displaying on both sides of the display, and also forms a control signal that indicates the effective display period of the video signal in each of the above systems, for example, in logic rH.

The high-quality video signal obtained by decoding the muse signal by the muse code circuit (5) and the double-speed video signal subjected to aspect ratio conversion processing by the aspect ratio conversion circuit (8) are transferred to a switch circuit for signal switching. (9
) selectively via the autopedestal processing circuit (10)
supplied to This autopedestal processing circuit (10)
operates during the period when the control input terminal (IOA) is supplied with a logic "H" control signal from the aspect ratio conversion circuit (8), detects the minimum signal level of the input video signal, and detects the minimum signal level of the input video signal. The human video signal is subjected to autopedestal processing that automatically controls the signal level based on the result. The video signal whose signal level is automatically controlled by the autopedestal processing circuit (10) is transmitted to the video output circuit (
11) to the picture tube (2), and an image is displayed on the picture tube (2)'s wide aspect ratio display screen of 16:9.

This image display device (1) accepts control input from a remote controller (12) to control the switching of each of the switching switch circuits (6) and (9), and the aspect ratio conversion circuit (8). A system controller (13) is provided for controlling various operations such as controlling the operation of the camera and controlling the switching of the deflection angle of the picture tube (2) by the deflection circuit (14).

In the image display device (1) of each embodiment, the aspect ratio conversion circuit (8) is configured as shown in FIG. 2, for example.

That is, as shown in FIG. 2, the aspect ratio conversion circuit (8) includes an analog-to-digital converter (22) that digitizes an input video signal band-limited by a low-pass filter (21), and this A/D converter (22). a dual baud 1 line memory (23) for performing time axis compression processing on the image data digitized by the converter (22);
A frame data adding circuit (24) adds frame data (j) to the image data read from this line memory (23), and blanking data is added to the image data to which the frame data has been added by this frame data adding circuit (24). The blanking data addition circuit (25) converts the image data to which the blanking data has been added into analog data and passes it through the low-pass filter (25).
7) outputs via a digital-to-analog converter (2).
6) A write clock generation circuit (28) that generates the timing for writing image data to the line memory (23), etc., and a read clock generation circuit (28) that generates the timing for reading image data from the line memory (23). It includes a circuit (29), a countdown circuit (30) that generates the timing necessary for processing the image in the vertical direction, and the like.

The write clock generation circuit (28) is a PLL circuit that forms 8f, , o reference signals necessary for A/D and memory write processing, and is, for example, as shown in FIG. A phase comparator (41) to which the double-speed horizontal synchronizing signal 2H formed by the frame double-speed conversion circuit (7) is supplied as a reference signal, and the phase comparison output from this phase comparator (41) is sent to the low-pass filter (42). A voltage-controlled oscillator (43) that is supplied as a control signal via the voltage-controlled oscillator (43), a counter circuit (44) that counts the oscillation output of this voltage-controlled oscillator (43), and a decoder circuit that decodes the counting output of this counter circuit (44). (45) etc.

This write clock generation circuit (28) has a frequency that is 910 times higher than the horizontal synchronization signal 2H (approximately 28MH).
A signal z) is generated by the voltage controlled oscillator (43), and this signal is divided into 1/910 by a counter circuit (44) and a decoder circuit (45) to obtain a comparison signal 2HW.
A closed loop is constructed by forming a signal 2HWref for comparison and comparing the phase of this comparison signal 2HWref with the -1- horizontal synchronization signal 2H in the phase comparator (41). By decoding the count output from the counter circuit (44) in the decoder circuit (45), a clock signal AD1, which provides the operation timing of the A/D converter (22), as shown in FIG. -J- line memory (
23), a write clock Wck that provides timing for writing image data into the line memory (23), a write control signal W8° that limits the write section of the line memory (23), and a signal that initializes the write address pointer in the line memory (23). Sen I□Control'! ■Signal W r s
form t.

Further, the read clock generation circuit (29) generates a PLL signal which forms a reference signal necessary for memory read processing.
, a circuit that generates two types of g4B signals depending on the display mode.

This read clock generation circuit (29) is, for example, a fifth
As shown in the figure, a phase comparator (51) to which the double-speed horizontal synchronizing signal 2H formed by the frame double-speed conversion circuit (7) is supplied as a reference signal;
) is supplied as a control signal via a low-pass filter (52) to a voltage-controlled oscillator (53).
), a counter circuit (54) that counts the oscillation output of this voltage controlled oscillator (53), a decoder circuit (55) that decodes the count output of this counter circuit (54), etc.

In this read clock generation circuit (29), the voltage controlled oscillator (53) and the decoder circuit (55) are each controlled by control data corresponding to the display mode given from the system controller (13) to the control register (31). When the operation is switched and the control data of the display mode (mode O) according to the above-mentioned first method is received, the PLL circuit forms a reference signal with a frequency of 8 fSc similarly to the above-mentioned write clock generation circuit (28). When receiving the control data for the display modes (modes 1 to 3) according to the second to fourth methods described above, the write clock generation circuit (28) generates an 8.
A PLL circuit is configured to form a reference signal with a frequency of fSc, and the display mode F according to the first to fourth methods described above is configured.
(mode 1 to 3) control data is received, 4/3
A PLL circuit is configured to form a reference signal of twice the frequency, that is, 1213 times the reference frequency 2H (approximately 38 MHz).

Then, the decoder circuit (55) decodes the counting output from the counter circuit (54), thereby converting the output from the D/A converter (1-) to the D/A converter (26) as shown in FIG.
) is the clock signal DA that provides the operation timing. , a read clock Rck that provides timing for reading image data from the line memory (23), a write control signal R8 that defines a read section of the line memory (23), a read address pointer in the line memory (23). Reset control signal R for initializing
,,SL, a new horizontal synchronization signal N is added to the control signal HP, c, which is necessary for adding the frame data and autopedestal processing, and the control signal HB, which is necessary for adding the plank data.
This read clock generation circuit (which forms EW2H etc.)
29) 1.Various control signals R, , , R
, St, Hp, c are the control registers (3
The generation timing is switched by the control data given to 1), and the output is performed at a timing corresponding to the display position of each screen according to the display mode (modes O to 3).

The above-mentioned FIG. 6 shows the display mode (
The case of mode 2) is shown.

In addition, in this read clock generation circuit (29), even when there is no signal during broadcast reception and the reference signal 2H is no longer input, the voltage controlled oscillator (53) of the PLL circuit operates in free-run mode. By continuing to operate in this state, stable timing can be generated.

Furthermore, the line memory (23) is an FTFO type line memory in which data can be written and read asynchronously, and as shown in FIG.
Eli, N, Awi (60) 61m includes a write address pointer (61) that provides a write address, and a read address pointer (62) that provides a read address to the memory cell array (60), and is connected via an input huffer (63). The input data Wdata input manually is input to the memory cell array (61) specified by the write address given by the write address pointer (61).
Output data Rdata written in the memory cell of the memory cell array (60) and read from the memory cell of the memory cell array (60) specified by the read address given by the read address pointer (62) is output via the output bumper (64). The configuration is as follows.

In this line memory (23), the write address pointer (61) is supplied with the write clock signal Wck generated by the write clock generation circuit (28) and each control signal W afi+ w, st. In addition, the above read address pointer (62)
are supplied with the read clock signal Rck generated by the read clock generation circuit (29) and each control signal Re, , +Rr sL. moreover,
The input huffer (63) is connected to the A/D converter (2).
The image data digitized by step 2) is supplied as input input data Wdata.

Input data Wdata inputted to the memory cell array (60) via the manual buffer (63) is input to the write control signal W8. by the write address pointer (61). ．． is written into the memory cells of the memory cell array (60) that are accessed in synchronization with the rise of the write clock signal Wcm during the period of logic rH.

As shown in the 8th episode, the write address pointer (61) is counted up by the write clock signal Wck during the period when the write control signal W- is at logic rH, and the write address pointer (61) is set to the next address of the memory cell (60). access the memory cell at address. Further, the write address pointer (61) is inhibited from being a count amplifier when the write control signal We11 becomes logic "■,". As a result, writing of data to the memory cell array (60) is interrupted.

This write control signal Wen limits the data write section. Furthermore, the write address pointer (61) is connected to the reseno I/control signal W r S L
is initialized in synchronization with the rising edge of write clock signal Wck during the period of logic rH, and accesses the memory cell at address 0.

Note that the write address pointer (61) to which the read clock signal Rck and each control signal R1, Rr□ generated by the read clock generation circuit (29) are supplied also corresponds to the write address pointer (61).
Perform the same operation as in 1).

This line memory (23) can write and read data asynchronously, and by increasing the frequency of the read clock signal Rck to 4/3 times the frequency of the write clock signal Wck, the image can be read in the horizontal direction. Aspect ratio conversion processing is performed to compress the image to 3/4 and display the image in the second to fourth display modes (modes 1 to 3) described above.

Note that the display mode of the above-mentioned first method (mode I O
), the write clock signal Wck and the read clock signal Rck have the same frequency.

Further, the countdown circuit (30) includes, for example, as shown in FIG.
The comparison signal 2 HWref formed by 28) is output to the clock signal WH via the output Hanofa (46).

It is composed of a counter circuit (7]) supplied as a counter circuit (7), a decoder circuit (72) for decoding the count output by this counter circuit (7]), and the like.

Here, the comparison signal 2HWref generated by the write clock generation circuit (28), that is, the clock signal WHcLk, has a rising edge that is a double-speed horizontal synchronization signal generated by the frame double-speed conversion circuit (7). 2H, and is synchronized with the horizontal synchronization signal 2I-1 with a steady phase error. That is, the clock signal WH1° is the horizontal synchronizing signal 2H.
It is considered to be the same as

The counter circuit (71) includes a waveform correction circuit (
73), it is reset with a reset control signal rst2 obtained by removing the jitter component from the vertical synchronization signal (2), and 525 (the number of double-speed scanning lines) clock signals W1-1cLk are counted.

Furthermore, the decoder circuit (72) decodes the count output from the counter circuit (71) to
As shown in FIG. 10, a new vertical synchronization signal NEW V
The vertical video section used for adding the blanging data is defined by the logic rH, and the control signal vp.
, c.

Note that the counter circuit (71) receives a reset control signal rst formed by the decoder circuit (72) described in 1.
1 and the vertical synchronizing signal V by the waveform correction circuit (73), or is reset by the logical sum of the cent control signal rst2. As a result, even if the vertical 1υj signal ■ cannot be detected at the correct position due to weak electric field conditions during broadcast reception,
2) Stable cent control signal rst formed by
l ensures correct resetting of the counter circuit (72). Further, the waveform correction circuit (73) is
In order to stably rinse the counter circuit (72), the relationship between the clock signal WHc+-, that is, the double-speed horizontal synchronization signal 2H and the vertical synchronization signal ■ is determined, and this relationship conforms to the EDTV standard. The cent control signal rst2 is output when it is within a certain tolerance range based on the standard, and is not output at other times.

In this countdown circuit (30), the clock for the counter circuit (71) is not the double-speed horizontal synchronization signal 2H generated by the frame double-speed conversion circuit (7), but is compared using the write clock generation circuit (28). Clock signal W formed from HWref
Since Hcly is used, even if there is no signal due to weak electric field conditions during broadcast reception and the double-speed horizontal synchronization signal 2H is interrupted, the write clock generation circuit (2) can be used.
Since the clock signal W11cLk is output by the free run of the voltage controlled oscillator (43) in 28), the counter circuit (71) continues the counting operation and outputs the vertical synchronization signal NEWV and the control signal ■P as stable signals. , c can be output.

Here, each control signal Wen+w, st generated by the write clock generation circuit (28) and each control signal generated by the read clock generator (29) for each display mode (mode O to 3) are Signal R8, R
FIG. 11 shows the relationship between □ and the addresses of the write address pointer (61) and read address pointer (62) in the run memory (23).

In the aspect ratio conversion circuit (8) having such a configuration, the dot sequential mode, that is, double speed video signal formed by the frame double speed conversion circuit (7) is band limited by the low pass filter (21) and subjected to anti-aliasing processing. The data is then digitized by the A/D converter (22). And this A/D converter (22)
Accordingly, the image data obtained by digitizing the video signal mentioned above is manually inputted to the line memory (23) mentioned above, and is processed by the write clock signal W- generated by the write clock generation circuit (28) and each control signal. W. , Wr□ is written into the line memory (23).

Note that the write control signal W is generated by the write clock generation circuit (28). 7 becomes logic "L" in the blanking section of the input video signal, interrupts writing of data to the line memory (23), and writes only the video section necessary for processing. ) to save space.

Data in the blanking section that is not written here is added by the reading side circuit.

The reset control signal W r s t generated by the read clock generation circuit (29) that performs read control of the line memory (23) is the reset control signal W generated by the write clock generation circuit (28).
It occurs at a position delayed by one horizontal scanning period from r□.

This prevents collisions between write addresses and read addresses.

``Two-speed first method display mode (mod
e O) does not perform horizontal compression processing, so the read control signal R generated by the read clock generation circuit (29). The timing of A is the same as that of the second imperial write control signal We. In this display mode (mode O), the write clock signal Wck and the read clock signal Rck have the same frequency, so that the video data read from the line memory (23) is only delayed by the IH. The image will be almost the same as the one on the writing side.

In addition, display modes (m
In odes 1 to 3), video data is read from the line memory (23) and the corresponding position video is displayed in an interval in which the read control signal Ren corresponding to each display mode is logic "I". These display modes (mo
In de 1 to 3), the read clock signal Rck has a frequency 4/3 times that of the write clock signal Wck, so that the video data in the line memory (23) is processed at a speed 4/3 times that of the writing side. As a result, a display image compressed to 3/4 in the horizontal direction is obtained.

In addition, the control signals HP, c generated by the read clock generation circuit (29) shown in FIG. 12 are
,D, each display mode (mode O~3)
, the area of the video to be displayed in the horizontal direction, that is, the valid display period is logical rH. This control signal HP, C
is inverted in polarity by an inverter (32) and supplied to the frame data addition circuit (24) as a switching control signal. This frame data addition circuit (24) is composed of a switch circuit, and selects the line memory (23) when the switching control signal is logic "L",
When the switching control signal is logic rH, select the frame data output section (33) and add frame data to a portion of the video data read out from the line memory (23) other than the effective video display area. .

Further, the control signals P and W generated by the countdown circuit (30) become logical rHJ in the area of the image to be displayed in the vertical direction, that is, in the effective display period. The generation timing of the control signal VP, , changes depending on the display mode (mode O) in the first method described above and the display mode (modes 1 to 3) in other methods.

The control signals VP and c, which indicate this valid display period in the vertical direction as logic rH, are inverted in polarity by an inverter (34), and then controlled by the read clock generation circuit (29) by an OR gate (34). A logical sum with signal HBLk is taken. The logical sum output from this OR gate <34) is -the blanking dequi 1 addition circuit (25
) as a switching control signal.

This blanking data addition circuit (26) is constituted by a switch circuit, and when the switching control signal is logic "L", it selects the frame data I 1 addition circuit (25), and the switching control signal is logic "L". 11'', the blanking data output section (35) is selected. The video data to which the frame data has been added by the frame data addition circuit (25) is processed by the blanking data addition circuit (25).
6) adds vertical and horizontal blanking data.

The output data from the blanking data addition circuit (26) is converted into analog data by the D/A converter (26), anti-aliased by the low-pass filter (27), and displayed in each of the above displays. Mode (mode O~3)
is output as a video signal.

Further, the horizontal effective display section formed by the read clock generation circuit (29) is set to logic rH.

The control signals HP, c and the countdown circuit shown in
(30)) The vertical effective display section formed by
3), logical product is taken. This AND get (33)
The logical product output by
The valid display period of the video signal of 3) is indicated by a logic "■", and is supplied as operation control signals P and C to the control input terminal (IOA) of the autopedestal processing circuit (10).

As a result, the autopedestal processing circuit (10) operates only during the valid display period of the video signal in each of the display modes (modes O to 3), so it cannot detect signals during the invalid display period other than the valid display period. The automatic pedestal can always perform proper autopedestal processing without malfunctioning.

H1 Effects of the Invention As described above, in the image display device according to the present invention, the autopedestal processing section is operated only during the effective display period for the input video signal by being controlled by the control section. By applying the present invention, it is possible to effectively utilize the dynamic range of the display means to display images with good quality without causing malfunctions due to the detection of signals during other invalid display periods. Even in an image display device configured to display a wide aspect ratio image and a standard aspect ratio image using a display means of a wide aspect ratio display screen, it is possible to display images by effectively utilizing the dynamic range of the display means. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image display device according to the present invention. FIG. 2 is a block diagram showing a specific configuration of the aspect ratio conversion circuit of the image display device shown in FIG. 1. FIG. 3 is a block diagram showing a specific configuration of the write clock generation circuit of the aspect ratio conversion circuit shown in FIG. 2, and FIG. 4 is a time chart for explaining the operation of this write clock generation circuit. It is. FIG. 5 is a block diagram showing a specific configuration of the readout clock generation circuit of the aspect ratio conversion circuit shown in FIG. 2 above, and FIG. 6 is a time chart for explaining the operation of this readout clock generation circuit. It is. FIG. 7 is a block diagram showing the specific configuration of the line memory of the aspect ratio conversion circuit shown in FIG. 2, and FIG. 8 is a time chart for explaining the data read operation for this line memory. be. FIG. 9 is a block diagram showing a specific configuration of the down counter circuit of the aspect ratio conversion circuit shown in FIG. 2, and FIG. 1O is a time chart for explaining the operation of this down counter circuit. . FIG. 11 is a time chart for explaining the operation of the aspect ratio conversion circuit shown in FIG. 2 in each display mode. A, B, C, and D in FIG. 12 are the generation of control signals that operate the autopedestal processing circuit during the effective display period for the video signal of each display mode in the image display device shown in the first part above. FIG. 4 is a schematic waveform diagram for explaining the position. A, B, C, and D in FIG. 13 are front views schematically showing images displayed by various methods for displaying an image with a standard aspect ratio on a display screen with a wide aspect It. (1... (2...) (7...... (8... (14) Image display device Picture tube frame Double speed conversion circuit Asparagus I/Ratio conversion circuit O/I/Pedestal processing circuit System controller Deflection circuit

Claims (1)

[Scope of Claims] An autopedestal processing unit that detects a minimum signal level of an input video signal and controls the signal level of the video signal based on the detection result, and performs the autopedestal processing on the input video signal during an effective display period. An image display device comprising: a control section that operates a control section.