JPH0472931A - Symbol timing extraction circuit - Google Patents

Abstract

PURPOSE:To realize stable synchronization by extracting an independent timing for each time slot so as to avoid the effect of a transient response of simultaneous locking from appearing on an information signal part of a reception signal. CONSTITUTION:A frequency control variable f1 of a slot 1 of a succeeding frame is generated by a symbol timing error 1 and a symbol timing error or the like caused in the symbol timing synchronization of the slot 1 and stored as a frequency control variable with respect to the said succeeding frame slot 1 till a reception timing of the succeeding frame slot 1. Moreover, either the frequency control variable of the slot 1 of the succeeding frame stored in a storage circuit 3 or a frequency control variable at a final point of time of the slot 1 outputted from a DPLL circuit 2 is inputted a frequency variable oscillation circuit 4 in a reception timing of the frame slot 1 of the succeeding frame to control the oscillating frequency and the clock is applied to the DPLL circuit 2 as an operating clock and a symbol timing of the slot 1 is extracted stably by the frequency division output.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to TDMA (Time Division)
Multiple Access: Time division multiple access)
The present invention relates to a symbol timing extraction circuit that is used in a reception demodulation circuit that receives a periodic burst reception signal of data, such as a data reception method or an intermittent data reception method, and stably extracts symbol timing of a burst reception signal.

(Prior art and its problems) As a symbol timing extraction circuit used in a reception demodulation circuit of a transmission system assuming periodic burst reception,
Conventionally, for example, synchronization of symbol timing was performed using a PLL.
(Phase-locked loop) A method is used to extract symbol timing by constructing an instant closed loop using a circuit.

However, in the conventional method, it is generally necessary to add a training signal for the purpose of synchronization acquisition to the leading edge of the burst signal, which has the disadvantage of reducing information transmission efficiency. Furthermore, if the training signal is shortened, a problem arises in that the influence of the synchronization pull-in transient response appears in the information portion of the received signal.

(Object of the Invention) The present invention provides a symbol timing extraction circuit that can eliminate the problem of the reduction in information transmission efficiency and the influence of synchronization pull-in transient response that occur in the conventional method, and can also obtain stable symbol timing extraction operation. The purpose is to provide.

(Configuration of the Invention) FIG. 1 is a side view of one configuration of a symbol timing extraction circuit according to the present invention. In the figure, reference numeral 1 denotes an asynchronous detection circuit that receives a digitally modulated periodic burst signal and performs an asynchronous detection operation.

2 is a digital PLL (DPL) that performs synchronized operation of the operating clock pulse according to the phase change point of the detection output using the detection output of the asynchronous detection circuit l and the operating clock pulse.
L) It is a circuit. 3 inputs the timing error information of each time slot for each frame obtained in the synchronous operation of the DPLL circuit 2, and stores the frequency control amount corrected by the timing error information for a certain period, while controlling the frequency control amount. This is a memory circuit that sequentially outputs data at each fixed period. 4 is the frequency control amount or DP from the memory circuit 3
The DPLL uses an oscillation output whose frequency is controlled by the frequency control amount from the LL circuit 2 as an operating clock pulse.
A variable frequency oscillator circuit that supplies the frequency to the circuit and outputs the divided output to the outside as symbol timing output.
For example, VCO, NGO, etc.).

FIG. 2 is a side view of the structure of the storage circuit 3 which is a part of the present invention, and the subtracter 32 is a frequency control oil amount storage circuit (for example, an N-stage shift register).

(Function) FIG. 3 is a time chart 1 example showing the operation when the symbol timing extraction circuit of the present invention shown in FIGS. 1 and 2 is applied to a TDMA receiver. T
This figure shows a case where attention is paid to time slot 1 (hereinafter simply referred to as slot) of a DMA frame. In the figure, (2) indicates a state in which the asynchronous detection circuit is receiving a digital signal of an arbitrary frame.

2 indicates that there is an error (Δf,) in the symbol timing of each slot (1-N) of the frame.

(2) indicates that the error Δf1 of the thrower l-1 is detected and the frequency control amount (ΔF+) is generated from that value.

■ is the frequency control amount ΔF, and the slot l of the next frame.
This indicates that it will be stored until it is received.

(2) indicates that frequency control is performed using the frequency control amount ΔF generated in the previous frame, and symbol timing of slot 1 is extracted.

The operation of the symbol timing extraction circuit of the present invention based on the configuration example shown in FIGS. 1 and 2 will be explained in detail below using FIG. 3.

First, the asynchronous detection circuit 1 performs asynchronous detection of the digital signal of the thrower I□1. (■ in Figure 3) Next, DP
The asynchronous detection output and the operation clock from the variable frequency oscillation circuit 4 are input to the LL circuit 2, and the symbol timing synchronization operation of slot l is performed.

This synchronous operation in the DPLL circuit 2 can be realized by a known method such as switching the clock, adding and canceling pulses to the clock, switching the phase of the clock, or software processing equivalent to these.

Next, the symbol timing error △f+ (■ in Fig. 3) generated by the symbol timing synchronization operation of slot 1 is
The frequency control amount ΔF for slot 1 of the next frame is generated from the symbol timing error generated in frame slot 1 (■ in FIG. 3). As a specific example, when the synchronous operation of the DPLL circuit 2 is performed by adding and erasing pulses to the operating clock, the average value (symbol timing error) of the number of pulses added and erasing that occurs and the frequency control amount of the frame corresponding to the average value. is input to the subtracter 31,
Is it possible to consider a circuit that outputs the difference as the frequency control amount for the next frame?Is it possible to input the output from not only the subtracter but also the DPLL circuit and the stored frequency control amount, and use the former to correct the latter? Anything that generates a new frequency control amount may be used.

Next, it is stored as a frequency control amount for the next frame slot 1 until the reception timing of the next frame slot 1. (■ in Fig. 3) As an example of the frequency control amount storage circuit 32, N stages of registers (1), (2)...
(N), each of which stores the frequency control amount of each slot. Further, as a method of synchronizing the stored frequency control amount of each slot with each reception slot, for example, the register of the frequency control amount storage circuit 32 may be configured with a shift register, and a shift operation may be performed when switching reception of each slot. There is a method in which the overflow output is sequentially supplied to the variable frequency oscillation circuit 4 as a frequency control amount for each slot.

Next, at the reception timing of slot 1 of the next frame,
The variable frequency oscillation circuit 4 receives the frequency control amount of slot 1 of the next frame stored in the storage circuit 3, or the DPLL.
Input one of the frequency control amounts at the final time of slot 1 output from circuit 2 to control the oscillation frequency (
3), it is supplied to the DPLL circuit 2 as an operating clock, and the symbol timing of slot 1 is stably extracted using the divided output (symbol timing output).

The operating clock supplied to this DPLL circuit 2 depends on the input to the variable frequency oscillation circuit 4.

The input is the frequency control amount (
(generated when the previous frame was received) does not depend on the control frequencies of slots other than the slot that was received immediately before, so the influence of the synchronization pull-in transient response can be removed.

Furthermore, if the input is the frequency control amount output from the DPLL circuit 2, instant closed loop control similar to the conventional one is performed, and the synchronized operation is quickly performed.

As an example of switching the input to the variable frequency oscillator circuit 4, control is performed using the frequency control amount stored in the storage circuit 3 at the start of reception of each slot to remove the influence of the synchronization pull-in transient response, and then the DPLL circuit Synchronous operation can be quickly performed by switching to control based on frequency control from step 2.

Thereafter, the above operation is repeated for each TDMA DMA frame. Similar operations are performed in parallel with respect to the other slots 2 to N, with a delay of one slot from each other.

As described above, in the present invention, the timing synchronization operation, storage of the timing error detection 1 frequency control amount, and frequency control (symbol timing extraction) are repeatedly performed for each corresponding time slot of the TDMA frame, and the immediate closed loop operation as in the conventional method is performed. Only control is not performed. Therefore, in the synchronous operation, the influence of transient response does not become apparent, and stable synchronous operation can be realized.

The above is an explanation of the operation when the present invention is used in a TDMA receiving device, but the same operation will be performed when applied to a device that receives periodic bursts of data such as an intermittent receiving method. it is obvious.

(Effects of the Invention) As explained in detail above, according to the present invention, independent timing extraction is possible for each time slot, so that the influence of synchronization pull-in transient response does not appear in the information part of the received signal. This not only makes it possible to realize stable synchronized operation, but also makes it possible to omit redundant training signals that are not related to the original information transmission. In addition, the parts from detection to control can be easily converted into software, which has the advantage of being suitable for miniaturization.

[Brief explanation of the drawing]

FIG. 1 shows a side view of a structure of a symbol timing extraction circuit according to the present invention, FIG. 2 shows a side view of a structure of a storage circuit 3 according to the present invention, and FIG. 3 shows a side view of an operation flow of the present invention. 1...Asynchronous detection circuit, 2...DPLL circuit, 3...
...Memory circuit, 4...Variable frequency oscillation circuit, 31...
- Subtractor, 32... variable frequency oscillation circuit. agent

Claims (1)

[Claims] An asynchronous detection circuit that performs an asynchronous detection operation on the received signal in order to extract symbol timing from the digitally modulated periodic burst reception signal, and a detection output and operation of the asynchronous detection circuit. A digital PLL circuit receives a clock pulse and outputs timing error information of each time slot for each frame caused by synchronization of the detected output, and a frequency control amount corrected by the timing error information from the digital PLL circuit. a memory circuit that sequentially outputs data in units of time slots and corrects and stores a frequency control amount for the next frame based on the output, and controls an oscillation frequency using the frequency control amount from the memory circuit at the start of reception of each time slot; After that, the oscillation frequency is controlled by the output from the digital PLL circuit, and the oscillation output is supplied to the digital PLL circuit as the operation clock pulse, and the frequency-divided output is output as the symbol timing. A symbol timing extraction circuit with an oscillator.