JPH0473253U

JPH0473253U -

Info

Publication number: JPH0473253U
Application number: JP11259090U
Authority: JP
Priority date: 1990-10-26
Filing date: 1990-10-26
Publication date: 1992-06-26

Description

[Brief explanation of drawings]

第１図はこの考案に係るマルチプロセツサ装置
のブロツク構成図、第２図はこの考案に係るマル
チプロセツサ装置を適用したグラフイツクデイス
プレイ装置の要部ブロツク構成図、第３図は同グ
ラフイツクデイスプレイ装置のバスインタフエー
ス回路の具体例を示すブロツク構成図、第４図は
この考案に係るプロセツサ部の他の実施例を示す
ブロツク構成図、第５図は共有メモリを備えた従
来のマルチプロセツサ装置のブロツク構成図、第
６図は従来の他の構成を示すブロツク構成図であ
る。１０……マルチプロセツサ装置、１１，１２，
１３……プロセツサ部、１１Ｐ，１２Ｐ，１３Ｐ
，４０Ｐ……プロセツサ、１１ＣＭ，１２ＣＭ，
１３ＣＭ……共有メモリ、１１Ｉ，１２Ｉ，１３
Ｉ，２１Ｉ，２２Ｉ，２３Ｉ，２４Ｉ，４０Ｉ…
…バスインタフエース（バスＩ／Ｆ）回路、１１
Ｂ，１２Ｂ，１３Ｂ，２１Ｂ，２２，２３Ｂ，２
４Ｂ，４０Ｂ……内部バス（プロセツサのバス）
、２１Ｐ……主プロセツサ、２２Ｐ，２３Ｐ，２
４Ｐ……画像メモリ、２２ＣＭ，２３ＣＭ，２４
ＣＭ……ワーク・共有メモリ、ＣＢ……共通バス
。 Fig. 1 is a block diagram of a multiprocessor device according to this invention, Fig. 2 is a block diagram of main parts of a graphic display device to which the multiprocessor device according to this invention is applied, and Fig. 3 is a block diagram of the same graphic display device. FIG. 4 is a block configuration diagram showing a specific example of a bus interface circuit of a display device, FIG. 4 is a block configuration diagram showing another embodiment of the processor section according to this invention, and FIG. FIG. 6 is a block diagram showing another conventional configuration of the setter device. 10...multiprocessor device, 11, 12,
13... Processor section, 11P, 12P, 13P
, 40P...Processor, 11CM, 12CM,
13CM...Shared memory, 11I, 12I, 13
I, 21I, 22I, 23I, 24I, 40I...
...Bus interface (bus I/F) circuit, 11
B, 12B, 13B, 21B, 22, 23B, 2
4B, 40B...Internal bus (processor bus)
, 21P...main processor, 22P, 23P, 2
4P...Image memory, 22CM, 23CM, 24
CM...work/shared memory, CB...common bus.

Claims

[Scope of utility model registration request]

In a multiprocessor device in which a plurality of processors are connected to a common bus via a bus interface circuit provided for each processor, a shared processor stores data commonly used by the processors on the bus of each processor. Each of the processors reads data from the shared memory via its processor bus, and writes data to each of the shared memories by simultaneously accessing all shared memories via the bus interface circuits. A multiprocessor device characterized in that it is configured to.