JPH0473301B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a junction field effect transistor having large mutual conductance and low noise characteristics.

Conventional structure and its problems Junction field effect transistor (hereinafter referred to as J-FET)
) are widely used as high input impedance circuit elements, low noise amplification elements, or switching elements.

By the way, the structure of a conventional J-FET is, for example, as shown in the cross-sectional structure in FIG. It has ^{a +} type isolation diffusion region 3, a P ⁺ type upper gate diffusion region 4, and an N ⁺ type source/drain region 5, 6, and furthermore, the upper gate diffusion region 4 and the silicon substrate 1 are structurally connected, and the external It has a structure in which source, gate, and drain electrodes 7, 8, and 9 are arranged as electrodes.
Note that 10 is a surface protective film.

The drawback of the conventional J-FET having this structure is that although the active region has a large planar area, the mutual conductance gm is low. On the other hand, in order to obtain a large GM, it is necessary to increase the gate width, but this requires a considerably large area, leading to a decrease in yield and an increase in cost. Furthermore, even if we try to increase the power with high current and high withstand voltage, there is a limit. It has drawbacks such as the inability to obtain electricity.

The structure of a static induction transistor (hereinafter abbreviated as SIT), which is attracting attention next, is, for example, as shown in ^FIG . N ⁺
The type semiconductor substrate 11a is used as a drain region, and N ⁺
A P-type buried gate region 12 is provided near the main surface of the type epitaxial region 11b so as to partially surround the region.
A P ⁺ type isolation diffusion region 13 is formed in contact with this, and an N ⁺ type source diffusion region 16 is provided in an N type epitaxial region 11b surrounded by these P type regions 12 and 13. as,
Source, gate, and drain electrodes 17, 18,
It is a structure in which 19 are arranged.

However, in this SIT structure, the carrier flows in a direction perpendicular to the substrate surface, and the current control by the gate is not sufficient, so the drain current does not saturate. Therefore, the drain voltage-current characteristic is similar to that of a triode. have.

Purpose of the Invention The present invention is different from the structure and characteristics of the SIT, and is aimed at solving the problems of the conventional J-FET as described above. That is, the present invention has pentode characteristics or similar characteristics like the conventional J-FET, and has a much higher gm per unit area than the conventional example.
An ideal J-
The aim is to realize FET.

Configuration of the Invention To summarize, the present invention provides a plurality of distributed low resistivity first electrode regions of the same conductivity type on one main surface of a semiconductor substrate of the same conductivity type, and An isolation region of opposite conductivity type is provided surrounding the electrode region, and a buried region is provided in the semiconductor substrate in contact with the isolation region and between the first electrode regions, and the isolation region and the buried region are An upper gate diffusion region of an opposite conductivity type is provided in a region of the surrounded semiconductor substrate surface located above the opening, the upper gate diffusion region is conductively connected to the isolation region, and the upper gate diffusion region is conductively connected to the isolation region; The present invention provides a junction field effect transistor having a structure in which a second electrode region of the same conductivity type as the semiconductor substrate is provided on a main surface.

That is, the feature of the present invention is that the channel cross section per area is enlarged by creating a structure in which the flow of the carrier is first directed parallel to the substrate surface and then directed perpendicularly. The source and gate regions are provided on one main surface of the substrate as in the conventional method, but the drain region is formed on the opposite main surface of the substrate, and the carrier flow is from the source to the upper gate diffusion in the lateral direction parallel to the main surface of the substrate. The flow is made to flow under the area, and then flow downward perpendicular to the substrate surface between the gates.
The mutual conductance gm can be significantly increased.

DESCRIPTION OF EMBODIMENTS An example of the structure of the J-FET of the present invention will be described in detail with reference to FIGS. 3, 4, and 5. In the J-FET of the present invention shown in FIG. 3, an N type epitaxial layer 11b is formed on an N ⁺ type silicon substrate 11a which becomes a second electrode region. Next, a P-type buried gate region 12 is formed in a part of the N-type epitaxial layer 11b, and an N-type epitaxial layer 11c is formed thereon so as to reach the P-type buried gate region 12 therein. The formed P ⁺ type isolation diffusion region 13, the P ⁺ type upper gate diffusion region 15 whose tip portion overlaps and is connected to the isolation diffusion region 13, as shown in FIG. N+ type source diffusion regions 16, which become first electrode regions, are dispersedly formed in the ^N type epitaxial layer 11c. The external electrodes have a structure in which source, gate, and drain electrodes 17, 18, and 19 are arranged for these. In FIG. 3, the source diffusion regions 16 are distributed and the upper gate diffusion region 15 is made single. Also, at this time, one end of the P type buried ^gate region 12 is placed at any position shown in a, b, or c in FIGS. The N ⁺ type source diffusion region 16 is located so as to have an opening.
This structure is located directly above the P-type buried gate region 12 at a depth within the range shown by d and e in the figure. Note that FIG. 4 shows the upper gate diffusion region 15.
are arranged in a cross pattern, and Figure 5 shows the -'
FIG. Further, the planar shape of the upper gate diffusion region 15 may be not only the cross shape shown in the figure but also a net shape.

In the J-FET of the present invention having the above configuration, the source gate structure is basically the same as that of the conventional one, and the carrier is first parallel to the substrate surface from the source diffusion region 16, and laterally extends from the upper gate diffusion region 15 to the upper gate diffusion region 15. The carriers flowing under the upper gate diffusion region 15 converge in the open channel region of the P-type buried gate region 12 located under the gate, and flow downward in a direction perpendicular to the substrate surface. It was made to flow.

According to this structure, the gate width can be increased and the actual gate length can be shortened, so the mutual conductance can be reduced.
It is possible to significantly increase GM and achieve ultra-low noise.
In addition, by increasing the specific resistance of the N-type epitaxial layer 11b, high current, high voltage and high power J-
Enables FETT. Furthermore, the length of the channel from source to drain can be made longer than in conventional J-FETs, and the electric field within the channel is weakened even when a high voltage is applied between the source and drain. As a result, gate leakage current is reduced, making it possible to use a voltage close to the withstand voltage. In addition, J-
In the FET structure, as shown in FIGS. 3, 4, and 5, if the source diffusion regions 16 are provided in a distributed manner, the number of source/gate units can be considerably increased, which effectively reduces the gate width. The gate length can be made as long as possible, the gate length can be made as short as possible, and a high gm can be achieved. In addition, it may be located directly under or in the vicinity of the upper gate diffusion region 15 and have the same or similar planar shape to the upper gate diffusion region. The J-FET of this example has the following steps in the normal manufacturing process:
It can be fabricated by simply adding a diffusion process to form the opposite conductivity type in the epitaxial region. In addition, in the past, in order to increase gm, the gate length was reduced to 1 to 2 μm or submicron, and it was difficult to form that thin line convergence, but the gate length of this example is
As shown in FIG. 5, instead of having a thin dimension of 1 to 2 μ, it may be 3 to 5 μ or more, and the actual gate length is longer than the length of the upper gate diffusion region 15. Depending on the area 12, dimensions as small as 1-2 microns or even sub-microns are possible and easy to manufacture.

The above explanation is based on N-channel J-FET.
However, the present invention is of course applicable to a P-channel J-FET.

Effects of the Invention As described above, although the present invention has pentode characteristics or characteristics close to them, the gm per unit area is much higher than that of the conventional one, and noise can be reduced.
Furthermore, when using the circuit, the gate leakage current is reduced, making it possible to use a voltage close to the withstand voltage, especially for high gm, low noise amplification or high output junction field effect transistors. It is useful for realization, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a conventional general junction field effect transistor, FIG. 2 is a sectional view showing the structure of a vertical static induction transistor, and FIGS. 3 and 4 are a sectional view of a conventional junction field effect transistor. A sectional view and a plan view for explaining the structure of an embodiment of the effect transistor, FIG. 5 is a sectional view taken along the line -' in FIG. 4. 1...P type silicon substrate, 2...N type epitaxial layer, 3...P ⁺ type isolation diffusion region, 4...P ⁺
Type upper gate diffusion region, 5...N ⁺ type source region,
6...N ⁺ type drain region, 7, 8, 9... electrode,
DESCRIPTION OF SYMBOLS 10...Surface protective film, 11a...N ⁺ type silicon substrate, 11b, 11c...N type epitaxial layer, 12...P type buried gate region, 13...
P ⁺ type isolation diffusion region, 15...P ⁺ type upper gate diffusion region, 16...N ⁺ type source region, 17...source electrode, 18...gate electrode, 19...drain electrode.

Claims (1)

[Claims] 1. A plurality of low resistivity first electrode regions of the same conductivity type as the semiconductor substrate are distributed and provided on the surface of a semiconductor substrate of one conductivity type, and the first electrode regions are an isolation region of an opposite conductivity type is provided in a surface region of the semiconductor substrate surrounding the semiconductor substrate; further a buried region is provided in the semiconductor substrate in contact with the isolation region and having an opening between the first electrode regions; An upper gate region of an opposite conductivity type is provided on the surface of the semiconductor substrate located above the opening, the upper gate region is conductively connected to the isolation region, and an upper gate region of the same conductivity type as the semiconductor substrate is provided on the opposite surface of the semiconductor substrate. A junction field effect transistor having a low resistivity second electrode region of the type. 2. The junction field effect transistor according to claim 1, wherein the shape of the opening in the buried region is the same or similar to the planar shape of the upper gate region. 3. The junction field effect transistor according to claim 1, wherein the shape of the opening of the buried region and the upper gate region is a cross shape or a mesh shape.