JPH0473358B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase control circuit for video signals, and is particularly suitable for application to a color signal processing circuit in a video tape recorder (VTR).

[Background technology and its problems]

When a video signal is recorded on a tape without a guard band in a VTR, it is inevitable that crosstalk will occur in the reproduced video signal when reproducing the low frequency converted color signal recorded on each track. Therefore, in conventional color signal processing circuits, in order to cancel this crosstalk color signal component and prevent it from occurring in the reproduced output, the color signal processing circuit uses PI processing (phase inversion processing) or PS processing (phase shift processing). ). For example, when performing PS processing, the phase of the low-frequency conversion color signal is changed when recording the video signal.
The phase is shifted by 90 degrees every 1H, and adjacent tracks are recorded so that they are in opposite phases, so that the crosstalk components mixed into the reproduced low-frequency conversion color signal during reproduction are sequentially in opposite phases. In this way, crosstalk components can be canceled during playback.

In this manner, in order to shift the phase of the low frequency conversion color signal by 90 degrees every 1H during recording and reproduction, it is necessary to form a selection signal for selecting a four-phase signal in the recording circuit and reproduction circuit. Therefore, conventionally, horizontal synchronizing signals are counted in a quaternary counter and the count output is used as a four-phase signal selection signal. However, if this is done, if a pulse drop occurs in the horizontal synchronizing signal, the quaternary counter will no longer be able to count in a predetermined manner, and hence the phase shift order will become abnormal, resulting in a shift in hue.

In addition to this problem, in the case of a playback circuit, for example, the phase of the horizontal synchronization signal included in the playback video signal is rapidly shifted due to jitter, etc., so when counting this signal with a quaternary counter, it is necessary to consider the responsiveness of the circuit. However, if this is done, there is a risk that the operation will become unstable in response to noise when it is mixed in.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and
The phase shift order is not disrupted even if a pulse is missing in the horizontal synchronization signal, and the response operation is stable even if there is a phase deviation (i.e. fluctuation) in each pulse of the horizontal synchronization signal. This paper attempts to propose a phase control circuit for video signals.

[Summary of the invention]

In order to achieve this purpose, the present invention includes:
A first PLL circuit with a relatively large time constant that generates decoded output pulses having the same frequency as a horizontal synchronization signal separated from the input video signal, an n-ary counter that counts the decoded output pulses, and a count output of the first PLL circuit. A second latch circuit with a relatively small time constant that generates a decode pulse output having the same frequency as the horizontal sync signal.
A phase shift control signal is obtained based on the output of the latch circuit by applying the decoded pulse output of the second PLL circuit to the latch circuit as a latch command signal.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a PS system color signal reproducing circuit.
f _S ) is the local signal S in the frequency conversion circuit 1
2 (frequency f _S +f _C ), and is converted into a carrier color signal S3 having a frequency of f _C . The thus obtained carrier color signal S3 passes through the bandpass filter 2, is added to the output of the 1H delay circuit 3 in the adder circuit 20, and is sent to the subsequent circuit as a reproduced carrier color signal S0.

This carrier color signal S0 is applied to a burst sampling circuit 4, and the extracted burst signal S4 is applied to a phase comparator circuit 5 where the phase is compared with the output S5 of a crystal oscillator 6 having the frequency f _C of the color subcarrier. The phase error signal S6 is supplied to the voltage controlled crystal oscillator circuit 7.
The oscillation frequency f _S is given to the error signal S6
control in the direction that becomes 0. The output S7 of the oscillation circuit 7 obtained in this way is given to the frequency conversion circuit 8, and together with the output S5 of the oscillator 6, a carrier signal S8 having a frequency f _S +f _C , which is the sum of the frequencies, is sent out. This carrier signal S8 is given to the phase shift control circuit 9, subjected to PS processing, and then sent to the frequency conversion circuit 1 as a local signal S2.

Thus, the phase of the carrier color signal S0 is controlled in the phase comparison circuit 5 so as to match the phase of the output S5 of the oscillator 6 as a reference. At that time, the oscillation circuit 7 oscillates at a sufficiently low frequency f _S before obtaining the carrier signal S8 in the frequency conversion circuit 8.
By controlling the error signal S6 of the phase comparison circuit 5, automatic phase control can be performed easily and stably.

The phase shift control circuit 9 includes a carrier phase shift circuit 11 and a phase control circuit 12 for controlling the phase shift of the carrier phase shift circuit 11. A horizontal synchronization signal S11 (frequency f _H ) separated from the reproduced video signal S10 by a horizontal synchronization separation circuit 13 is applied to the phase control circuit 12 together with a head switching signal S12.

Here, the configuration shown in FIG. 2 can be applied as the phase control circuit 12. The horizontal synchronization signal S11 is the first
PLL circuit (phase lock loop circuit) 21
given to. This PLL circuit 21 has a sufficiently large time constant against pulsed noise that may be mixed into the horizontal synchronizing signal S11, and combines the outputs of the respective frequency division stages of the frequency division circuit as shown in FIG. 3B. As shown, a decoded output signal S21 consisting of a pulse generated at a time point before the rise of each pulse of the horizontal synchronizing signal S11 (FIG. 3A) is sent out.

This decoded output signal S21 is output from the quaternary counter 2.
2, and a count output S22 (FIG. 3C) representing the count contents is supplied to the latch circuit 23. The latch circuit 23 has a latch command signal S.
The decode output signal of the second PLL circuit 24 is provided as 23 (FIG. 3D). This second
The PLL circuit 224 is configured to have a small time constant to the extent that it can sufficiently respond to the speed of swing (that is, fluctuation) of the horizontal synchronizing signal S11.
11, the latch command signal S23
It is designed to send out.

The latch circuit 23 latches the count output S22 coming from the quaternary counter 22 when the latch command signal S23 is applied, and sends the latch output to the four-phase carrier forming circuit 25 as a selector signal S24 (E in FIG. 3). give.

The 4-phase carrier forming circuit 25 generates 4-phase outputs whose phases are shifted by 90°, that is, 0°, 90°, 180°, and 270° carriers, and converts the carrier signal specified by the selector signal S24 into the frequency conversion circuit 1. (Figure 1)
It is sent out as a local signal S2 for the local signal S2. Thus, as shown in FIG. 3F, the local signal S2 sequentially sends out carrier signals of the corresponding phase each time the content of the selector signal S24 (FIG. 3E) changes.

A carrier color signal S3 obtained by frequency-converting the reproduced low frequency converted color signal S1 using this local signal S2 is applied to a 1H delay circuit 3 through a bandpass filter 2, and the carrier color signal delayed by 1H is sent to an adding circuit. At step 20, it is added to the undelayed carrier color signal S3, thereby obtaining a carrier color signal S0 in which crosstalk components from adjacent drugs are mutually canceled.

In the above configuration, if there is no missing pulse in the horizontal synchronizing signal S11 (FIG. 3A), the first PLL circuit 21 decodes the pulse at time _t1 before the pulse of the horizontal synchronizing signal S11 arrives at time _t3 . The output signal S21 is obtained (FIG. 3B), and the count content of the quaternary counter 22 increments to [1] (FIG. 3C). The contents of this count are latched in the latch circuit 23 (FIG. 3E) by the generation of the latch command signal S23 (FIG. 3D) from the second PLL circuit 24 at a subsequent time point _t2 . Therefore, the four-phase carrier forming circuit 25 is [1]
In response to the selector signal S24 whose content is
The local signal S2 of phase (phase is 0°) is sent out (FIG. 3F).

Then, at time _t3 , a pulse of the horizontal synchronizing signal S11 arrives, and then at time _t4 , the first
A decode output signal S21 is generated from the PLL circuit 21, and the contents of the quaternary counter 22 are incremented to [2]. Then, at a subsequent time point t5, a latch command signal S23 is generated from the second PLL circuit 24, and the content [2] of the output S22 of the quaternary counter 22 is latched in the latch circuit 23. Therefore, the content of the four-phase carrier forming circuit 25 is [2] at this time.
In response to the selected selector signal S24, the local signal S2 of the second phase (90° phase) is sent out.

Similarly, the second PLL is activated at time t ₇ and t ₁₀ .
Every time the decode output signal S21 is generated from the circuit 21, the quaternary counter 22 performs a step-by-step operation and provides the count output S22 with the contents of [3] and [4] to the latch circuit 23, and then at the subsequent time _t8. , t ₁₁ , the second PLL circuit 24 generates the latch command signal S23, so that the count output signal S22 is
are sequentially latched in the latch circuit 23. Therefore, the contents of the four-phase carrier forming circuit 25 are sequentially [3] and [4].
In response to the selector signal S24, the local signal S2 consisting of the third phase (180°) and fourth phase (270°) outputs is sequentially transmitted.

In this way, the content of the local signal S2 goes around in the order of the first phase, second phase, third phase, and fourth phase output, and as a result, the phase of the carrier color signal S3 frequency-converted in the frequency conversion circuit 1 changes by 90 degrees. phase shift,
As a result, a carrier color signal with the crosstalk component canceled is sent to the output side of the adder circuit 20.

Such a phase shift operation of the local signal S2 is performed by the first PLL circuit 21 at a subsequent time point _t13 .
When the decoded output signal S21 is generated, it is repeated again, and in the same manner, the phase of the carrier color signal S3 frequency-converted in the frequency conversion circuit 1 is continuously shifted by 90 degrees, and as a result, A signal in which crosstalk components are continuously canceled is obtained as the carrier color signal S0 at the output end of the adder circuit 20.

The above has described the operation when there is no pulse omission in each pulse of the horizontal synchronization signal _S11 , but as shown in _FIG . , the first and second PLL circuits 21 and 24 do not stop the oscillation operation itself even if the pulse of the horizontal synchronizing signal S11 is missing, and maintain the previous lock state while outputting the decoded output signal S21 and the latch. Each command signal S23 is sent out. Therefore, even if the pulse is missing, the quaternary counter 22 continues to count, and the latch circuit 23 latches the count contents.As a result, the four-phase carrier forming circuit 5 receives the contents latched by the latch circuit 23. Since the selection operation of the phase output is continued using the selector signal S24 having .

In this way, according to the configuration shown in FIG. 2, even if a pulse drop occurs in the horizontal synchronizing signal S11, the phase switching order as the local signal S2 is not changed and is continuously shifted by a predetermined phase amount. It is possible to obtain a signal, and therefore, it is possible to effectively avoid the possibility of color shift occurring in an image.

In addition, according to the configuration shown in FIG. 2, a long time constant is used as the first PLL circuit 21 that determines the phase switching timing based on the horizontal synchronization signal S11, and the specified phase switching order is The second PLL circuit 2 with a short time constant
4, it is possible to change the phase order even if the horizontal synchronizing signal S11 contains pulse noise.
The PLL circuit 21 makes it possible not to react to the noise, and if the generation point of the horizontal synchronizing signal S11 fluctuates due to, for example, jitter, the PLL circuit 24 ensures that it responds to the fluctuation and corrects it. By switching the four-phase carrier forming circuit 25 at the timing of the fluctuation, the phase of the local signal S2 can be switched.

Note that if the horizontal synchronization signal S11 contains pulse noise and the latch command signal S23 based on this is generated from the second PLL circuit 24, the contents of the quaternary counter 22 at this time is the horizontal synchronizing signal S11 without being caused by noisy pulses.
This is the same as a counting operation performed solely by the oscilloscope, and has no adverse effect on the phase shift operation.

In the above, a case has been described in which the local signal S2 is obtained by sequentially shifting the phase of the carrier color signal S3 by 90 degrees, but this is not limited to 360 degrees/n.
The present invention can be applied in exactly the same manner to the case of obtaining the local signal S2 whose phase is gradually shifted. In this case, the quaternary counter 22 in FIG.
can be replaced with an n-ary counter. For example n=2
If this is selected, the phase shift amount of the local signal S2 will be 90°, and thus the present invention can be applied even when so-called PI processing (phase inversion processing) is performed.

Furthermore, in the above description, the phase control circuit according to the present invention has been described as an example in which the phase control circuit according to the present invention is applied to a reproduction circuit, but when recording a low-frequency conversion color signal in a recording circuit, the phase of the carrier is determined based on the recording horizontal synchronization signal. It can be applied in the same way when shifting.

〔Effect of the invention〕

As described above, according to the present invention, even if a pulse is missing in the horizontal synchronizing signal, the phase shift order is not adversely affected, and even if a noisy pulse is mixed in the horizontal synchronizing signal, this will not affect the phase shift order. It is possible to easily obtain a phase control signal that does not react to the pulses of the horizontal synchronizing signal and can sufficiently follow and shift the phase when each pulse of the horizontal synchronizing signal swings.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal phase control circuit according to the present invention, FIG. 2 is a block diagram showing the detailed configuration of the main parts thereof, and FIGS.
The figure is a signal waveform diagram showing the signals of each part in FIG. 2. 1, 8...Frequency conversion circuit, 9...Phase shift control circuit, 11...Carrier phase shift circuit, 12...Phase control circuit, 21, 24...PLL circuit, 22...4
advance counter, 23...latch circuit, 25...4-phase carrier formation circuit.

Claims (1)

[Claims] 1. The phase of color signals is sequentially shifted and recorded on one track, and when the recorded color signals are reproduced, crosstalk between color signals recorded adjacent to each other is eliminated. In a video signal recording and reproducing device configured to cancel a video signal, (a) receiving a horizontal synchronizing signal separated from an input video signal including the color signal and generating a decoded output pulse having the same frequency as the horizontal synchronizing signal; and has a relatively large time constant.
(b) an n-ary counter that performs a counting operation in response to the decoded output pulse of the first PLL circuit; (c) a latch circuit that receives the count output of the n-ary counter as an input to be latched; (d) receiving the horizontal synchronization signal and generating a decode pulse output having the same frequency as the horizontal synchronization signal and having a relatively small time constant, and sending the decode pulse output as a latch command signal to the latch circuit; A phase control circuit for a video signal, comprising: a second PLL circuit; and obtaining a phase shift control signal based on the output of the latch circuit.