JPS6058788A - Phase control circuit of video signal - Google Patents

Abstract

PURPOSE:To make quick correction possible so that the inverted state of colors is not continued hereafter even if pulse drop-out occurs in horizontal synchronizing pulses, by latching the level of an inverted data signal with a latch circuit which receives a horizontal synchronizing signal and the second decoder output pulse as trigger signals and obtaining a phase shift control signal for a carrier on a basis of this latch output. CONSTITUTION:A phase error signal S6 is given to a voltage control quartz oscillating circuit 7, and its oscillation frequency fs is controlled in such direction that the error signal S6 becomes ''0''. An output S7 of the oscillating circuit 7 obtained in this manner is given to a frequency converting circuit 8, and a carrier signal S8 having a frequency fs+fc of the sum of the frequency of the output S7 and the frequency of an output S5 of an oscillator 6 is transmitted. This carrier signal S8 is applied to a phase shift control circuit 9 and is subjected to phase inversion (PI) processing and is transmitted as a local signal S2 to a frequency converting circuit 1. Thus, the phase of a chrominance signal S0 is controlled by a phase comparing circuit 5 so that it coincides with the phase of the output S5 of the oscillator 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase control circuit for video signals, and is suitable for application to, for example, forming a PI double signal PS signal in a video tape recorder (VTR). be.

[Background technology and its problems]

When forming tracks on a VTR without providing a guard band between video tracks formed on a tape, low-frequency conversion is performed on each track to prevent color crosstalk between adjacent tracks. Color signal processing using a PI (phase inversion) method or a PS (phase shift) method is used in which the phase of a color carrier wave is inverted for each IH section of the color signal.

However, in conventional VTRs, when inverting the phase of the color carrier wave, a horizontal synchronization signal is used to obtain a phase shift control signal whose logic level changes every time the horizontal synchronization pulse arrives, and the logic level of this phase shift control signal changes. The carrier phase shift circuit is operated to shift the phase according to the phase change. However, if this is done, there is a risk that the level transition order of the phase shift control signal will be reversed if the horizontal synchronizing pulse is missing, and if such a change occurs, the colors on the playback screen will be in a complementary color relationship. This will result in you stumbling around.

[Purpose of the Invention] The present invention has been made with the above-mentioned considerations in mind. Even if a pulse omission occurs in the horizontal synchronizing pulse, it is possible to promptly correct the color inversion so that it does not continue. This paper attempts to propose a phase control circuit for video signals.

[Summary of ``release ψ'']

What purpose? ff, in the present invention, the PLL
In the circuit, first and second decode output pulses having the same frequency as the horizontal synchronization signal and different phases are obtained, and in response to the first decode output pulse, the inverted data signal forming circuit generates the horizontal synchronization signal. An inverted data signal that inverts at the same period is obtained, the level of the inverted data signal is latched by a latch circuit that receives the first horizontal synchronizing signal and the second decoded output pulse as a trigger signal, and the carrier crystallizes on this latch output. The phase shift control circuit signal for is obtained.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings. 1st
The diagram in the south shows an embodiment in which the present invention is applied to a PI system color@number reproduction circuit, in which a reproduced low-pass converted color signal 81 (frequency f,) reproduced from a tape is local 48 in the frequency conversion circuit 1. The frequency is converted by No. 82 (frequency f8+f.) to the frequency f. is converted into a carrier color signal S3. The carrier color signal S3 obtained by the sniffing is passed through a bandpass filter 2, and then added to the output of the IH delay circuit 3 in an adder circuit to generate a reproduced carrier color signal SQ in the subsequent circuit 1c.
Sent as .

This carrier color signal SO is given to the burst sampling circuit 4,
The extracted burst signal is given to the phase comparator circuit 5, and the color amount is 1. The number of revolutions of the conveying drum is f. The phase is compared with the output S5 of the crystal oscillator 6 having a The phase error signal S6 is given to the voltage controlled crystal oscillator circuit 7 and its oscillation frequency is f8.
is controlled so that the error signal S6 becomes O. The output S7 of the oscillator #57 thus obtained is given to the frequency conversion circuit 8, and together with the output S5 of the oscillator 6, the sum of the frequencies is a wave ifs ten. The carrier signal S8 is sent out.

This carrier signal S8 is given to the phase shift control circuit 9 and P
After being subjected to I processing, it is sent to the frequency conversion circuit 1 as a local signal S2.

In this way, the phase of the carrier color signal SO is matched with the phase of the output S5 of the oscillator 6 in the phase comparator circuit 5.
The phase is controlled so that At that time, before obtaining the carrier signal S8 in the frequency conversion circuit 8, the same wave number f is sufficiently low.
The oscillation circuit 7 that oscillates at 8 is the error signal of the phase comparator circuit 5 @
By controlling by S6, automatic phase control can be performed easily and stably.

The phase shift control circuit 9 includes a carrier inversion circuit 11 and a phase control circuit 12 that performs inversion control of the carrier inversion circuit 11. Phase control circuit 12
A horizontal synchronization signal 511 (frequency fH) separated from the Nyu video @ SIO in the horizontal synchronization separation circuit 10 is given together with a head switching signal 812 .

Here, the phase control 11 path 12 has the configuration shown in FIG.

That is, the phase control circuit 12 outputs the horizontal synchronization signal 811 to the phase comparison circuit 13A [9] and the timing signal generation PLL (
The output of the phase comparator circuit 13A is passed through a low-pass filter (LPF') 13B.
Voltage controlled oscillator (VCO) 1 after converting to free current at 1
Give to 3C. The frequency output of this oscillation circuit 13C is frequency-divided in the divider 13 D Vl and then sent to the phase comparator circuit 13.
AVc feedback and thus the phase of the frequency output generated in the oscillator 13C is horizontal synchronization 1 - Q.
SilK is locked.

Here, the frequency divider 13D combines the outputs of the respective frequency division stages as necessary to generate the horizontal synchronizing signal 511 (see FIG. 3 (4).
)) two decode output pulses DP with the same frequency as
I (Fig. 3 ■) and DP2 (Fig. 3 (0)) are generated.

The first and second decode output pulses DPI and DP2 are configured to occur at times delayed by mutually different delay times T1 and T2 with respect to each pulse of the horizontal synchronizing signal 811.

The first decode output pulse DPI is given as a trigger signal to the inverted data forming circuit 14, and the inverted data forming circuit 14 outputs an inverted data signal whose logic level is inverted by the decoded output pulse DPI as shown in FIG. 814 is sent.

This inverted data signal 814 is applied to latch circuit 15.

The latch circuit 15 operates using the rising edge of the horizontal synchronizing signal 811 or the rising edge of the decode output pulse DP2 as a trigger signal, and is configured to latch the logic level of the inverted data signal 814 sent from the inverted data forming circuit 14.
Thus, as shown in FIG. 3F, the signal is applied to the carrier inversion circuit 11 as an output phase shift control signal 813 of the phase control circuit 12 representing a change in the latched logic level. Note that a head switching signal 812 is applied to the inverted data forming circuit 14 and the latch circuit 15 so that an output having a level can be sent from the inverted data forming circuit 14 and the latch circuit 15.

The carrier inversion circuit 11 is configured to invert or non-invert the phase of the carrier signal S8 given from the frequency conversion circuit 8 depending on the logic level of the phase shift control signal 813, and in this embodiment, for example, the phase shift control When the logic level of signal 813 is logic rHJ, the phase of carrier signal S8 is inverted and sent as local signal S2.

In the above-described interception, if there is no missing pulse in the horizontal synchronizing signal S11 as shown in FIG. 3(4), when the horizontal synchronizing signal 811 rises at time t1 in FIG. Output 514 (Figure 3a) is logic rHJ
If so, this is latched by the latch circuit 15, and the logic level of the phase shift control signal 513 (■ in FIG. 3) becomes rHJ.

Then at time t2 a second decode output pulse D
P2 (When (0) in FIG. 3 occurs, the latch circuit 15 attempts to latch the logic level of the inverted data signal 814 at this time, but at this time the latch circuit 15 has already been latched to logic "H". Therefore, the logic level of the phase shift control signal 813 does not change and remains at logic rHJ.

When the first decode output pulse DPI (third output) is generated at subsequent time point t3, the inverted data signal S14 of the inverted data forming circuit 140 is inverted to logic "L".

Thereafter, at time t4, when the next pulse of the horizontal synchronizing signal Sll arrives, this causes the latch circuit 15 to latch the level of the inverted data signal 814, ie, rLJ. Therefore, the phase shift control signal 813 falls from logic rHJ to logic rLJ at this time. When the second decode output pulse DP2 arrives at a subsequent time point t5, it causes the latch circuit 15 to latch the logic level "L" of the inverted data signal 814. However, at this time, since the latch circuit 15 is already latched to the logic rLJ, the phase shift control signal 81.3 continues to maintain the logic rLJ state.

Since the first decode output pulse DPI arrives at the subsequent time point t6, the inverted data signal 814 of the inverted data forming circuit 14 rises from the logic rLJ to the logic rHJ.

At the subsequent time point t7, when the next pulse of the horizontal direction signal S11 arrives, the corresponding logic rHJ level of the inverted data signal 814 is latched by the latch circuit 15, and thus the phase shift control signal 813 changes from the logic rLJ to the logic rHJ. climb. Thereafter, in the same way, the inversion data forming circuit 14 repeats the inversion operation one after another in response to the first decode output pulse DPI that arrives at the same period as the horizontal synchronization signal Sll, and the horizontal synchronization signal that arrives each time this operation is repeated. The inverted logic level is latched in the latch circuit 15 by each pulse of 811. On the other hand, in the case of Figure 3, the second
Since the decoded output pulse DI)2 arrives after the inverted data forming circuit 14 performs an inverting operation by each pulse of the horizontal synchronizing signal S11, it does not actually cause the latched state of the latch circuit 15 to be inverted.

Thus, the phase shift control signal 513 (Fig. 3) has its logic level inverted by the rising edge of the horizontal synchronizing signal Sll, and thereby the carrier inversion circuit 11 (Fig. 1) has a predetermined P.
I processing can be performed.

On the other hand, if the pulse of the horizontal synchronizing signal 811 is lost at time t11 in FIG. 4(2), the output 813 of the latch circuit 15 changes from logic rHJ to logic "L" as shown by the dotted line in FIG. The latch circuit 15 cannot be caused to perform such a latch operation even though the condition is such that the phase shift control signal 813 maintains the logic rHJ level. However, at this time, the second decode output pulse DP2 at time L1□
arrives and causes the latch circuit 15 to perform a latching operation. At this time, since the inverted data signal 814 is at the logic rLJ, the logic level of the phase shift control signal S13 falls from the logic rHJ to the logic rLJ. Since this operation is executed before the next pulse of the horizontal synchronization signal 8110 arrives at time t14, the period W(t1) in which the logic level of the phase shift control signal 813 is incorrect
1 to t1□) is only a part of one period of the horizontal synchronizing signal S11, and as a result, the portion where the colors on the screen are inverted is limited to an extremely small portion.

In addition, in the case of FIG. 4, the response operation in the case where one pulse of the horizontal synchronizing signal Sll is missing is described.
Even if the counting pulses are missed one after another, the inversion operation of the latch circuit 15 can be performed at the same period as the horizontal synchronization signal 811, so that the phase inversion order of the carrier waves in the local signal S2 can be set in the correct order. can be maintained.

Incidentally, the first and second decode output pulses DPI.

Since DP2 can be generated as the decoded output of the frequency divider 13D of the PLL circuit 13 with almost the same period as the horizontal synchronizing signal Sll regardless of the presence or absence of the horizontal synchronizing signal 811, the inverted data forming circuit 140 The 8140 inversion operation can also be performed in the same period as one period of the horizontal synchronization signal S11, and thus the phase shift control signal 8
130 inversion order can be maintained in the correct order.

In this way, the reproduced low-frequency converted color signal S1 is frequency-converted to the carrier color signal S3 based on the local signal S2 whose phase is inverted for each IH seed 1, so that the reproduced low-frequency converted color signal S1 has a high frequency when recording. The color signals whose phases have been inverted for each IH are matched in phase, and then added to the carrier color signal delayed in the IH delay circuit 3 in the adder circuit, thereby canceling the crosstalk component. Become.

In the above description, the present invention has been described as an example in which the present invention is applied when a reproduction circuit converts a reproduced low-pass converted color signal into a carrier color signal, but it is also possible to frequency-convert a low-pass converted color signal into a carrier color signal in a recording circuit. The present invention can be applied to a circuit that performs #disposal processing.

Furthermore, in the above embodiment, the embodiment was applied to obtain a PI multiplied signal (phase inverted signal) according to the present invention.
It can also be applied when obtaining a signal (phase shift signal). For example, if you want to obtain a PS signal whose phase shifts by 90 degrees for each IH, the second (2) phase shift control value = 813 is input to a quaternary counter (() to create a four-phase selection signal. , 0', 90°, ] by this four-phase selection signal sequentially
It is only necessary to select the 800.2700 phase and I phase amount. In short, the present invention can be widely applied to the case of obtaining n-phase phase signals whose phases are shifted by "L".

〔Effect of the invention〕

As described above, according to the present invention, even if each pulse of the horizontal synchronization signal is missed, a phase control circuit that can actually correct the change order to the correct change order during one fiid period of the horizontal synchronization signal can be easily created. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the video GG phase control circuit according to the present invention, FIG. 28 is a block diagram showing the detailed configuration of its main parts, and FIGS. Signals of each part are shown (G waveform diagram. 1... Frequency conversion circuit, 9... Phase shift control circuit, 11
...Carrier inversion circuit, ■2...Phase control circuit, 1
3... PLL circuit, 14... Inverted data formation circuit,
15...Latch circuit. (15)

Claims (1)

[Claims] Color signals are recorded on one track with their phases shifted sequentially, and when the recorded color signals are reproduced, crosstalk between color signals recorded adjacent to each other is canceled. In the video signal recording and reproducing apparatus, the video signal recording and reproducing apparatus (at) receives a horizontal synchronizing signal separated from an input video signal including the color signal and outputs a signal having the same frequency as the horizontal synchronizing signal and having different phases from each other. (b) an inverted data signal forming circuit that generates an inverted data signal that is inverted at the same period as the horizontal synchronization signal in response to the first decoded output pulse; and (cl) a latch circuit that receives the horizontal synchronization signal and the second decoded output pulse as a trigger signal and latches the level of the inverted data signal, and generates a phase shift control signal based on the output of the latch circuit. 1. A video signal phase control circuit characterized in that: